1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/net/ti-dp83867.h> 13 14#include "imx8mp.dtsi" 15 16/ { 17 model = "Gateworks Venice GW74xx i.MX8MP board"; 18 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; 19 20 aliases { 21 ethernet0 = &eqos; 22 ethernet1 = &fec; 23 ethernet2 = &lan1; 24 ethernet3 = &lan2; 25 ethernet4 = &lan3; 26 ethernet5 = &lan4; 27 ethernet6 = &lan5; 28 rtc0 = &gsc_rtc; 29 rtc1 = &snvs_rtc; 30 }; 31 32 chosen { 33 stdout-path = &uart2; 34 }; 35 36 memory@40000000 { 37 device_type = "memory"; 38 reg = <0x0 0x40000000 0 0x80000000>; 39 }; 40 41 connector { 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_usbcon1>; 44 compatible = "gpio-usb-b-connector", "usb-b-connector"; 45 type = "micro"; 46 label = "Type-C"; 47 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 48 49 port { 50 usb_dr_connector: endpoint { 51 remote-endpoint = <&usb3_dwc>; 52 }; 53 }; 54 }; 55 56 gpio-keys { 57 compatible = "gpio-keys"; 58 59 key-0 { 60 label = "user_pb"; 61 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 62 linux,code = <BTN_0>; 63 }; 64 65 key-1 { 66 label = "user_pb1x"; 67 linux,code = <BTN_1>; 68 interrupt-parent = <&gsc>; 69 interrupts = <0>; 70 }; 71 72 key-2 { 73 label = "key_erased"; 74 linux,code = <BTN_2>; 75 interrupt-parent = <&gsc>; 76 interrupts = <1>; 77 }; 78 79 key-3 { 80 label = "eeprom_wp"; 81 linux,code = <BTN_3>; 82 interrupt-parent = <&gsc>; 83 interrupts = <2>; 84 }; 85 86 key-4 { 87 label = "tamper"; 88 linux,code = <BTN_4>; 89 interrupt-parent = <&gsc>; 90 interrupts = <5>; 91 }; 92 93 key-5 { 94 label = "switch_hold"; 95 linux,code = <BTN_5>; 96 interrupt-parent = <&gsc>; 97 interrupts = <7>; 98 }; 99 }; 100 101 led-controller { 102 compatible = "gpio-leds"; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_gpio_leds>; 105 106 led-0 { 107 function = LED_FUNCTION_HEARTBEAT; 108 color = <LED_COLOR_ID_GREEN>; 109 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 110 default-state = "on"; 111 linux,default-trigger = "heartbeat"; 112 }; 113 114 led-1 { 115 function = LED_FUNCTION_STATUS; 116 color = <LED_COLOR_ID_RED>; 117 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 118 default-state = "off"; 119 }; 120 }; 121 122 pcie0_refclk: pcie0-refclk { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <100000000>; 126 }; 127 128 pps { 129 compatible = "pps-gpio"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_pps>; 132 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 133 }; 134 135 reg_usb2_vbus: regulator-usb2 { 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_reg_usb2>; 138 compatible = "regulator-fixed"; 139 regulator-name = "usb_usb2_vbus"; 140 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; 141 enable-active-high; 142 regulator-min-microvolt = <5000000>; 143 regulator-max-microvolt = <5000000>; 144 }; 145 146 reg_can1_stby: regulator-can1-stby { 147 compatible = "regulator-fixed"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_reg_can1>; 150 regulator-name = "can1_stby"; 151 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 }; 155 156 reg_can2_stby: regulator-can2-stby { 157 compatible = "regulator-fixed"; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_reg_can2>; 160 regulator-name = "can2_stby"; 161 gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 }; 165 166 reg_wifi_en: regulator-wifi-en { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_reg_wifi>; 169 compatible = "regulator-fixed"; 170 regulator-name = "wl"; 171 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 172 startup-delay-us = <70000>; 173 enable-active-high; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 }; 177}; 178 179&A53_0 { 180 cpu-supply = <®_arm>; 181}; 182 183&A53_1 { 184 cpu-supply = <®_arm>; 185}; 186 187&A53_2 { 188 cpu-supply = <®_arm>; 189}; 190 191&A53_3 { 192 cpu-supply = <®_arm>; 193}; 194 195&ecspi1 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_spi1>; 198 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 199 status = "okay"; 200 201 tpm@0 { 202 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 203 reg = <0x0>; 204 spi-max-frequency = <36000000>; 205 }; 206}; 207 208/* off-board header */ 209&ecspi2 { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_spi2>; 212 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 213 status = "okay"; 214}; 215 216&eqos { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_eqos>; 219 phy-mode = "rgmii-id"; 220 phy-handle = <ðphy0>; 221 status = "okay"; 222 223 mdio { 224 compatible = "snps,dwmac-mdio"; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 228 ethphy0: ethernet-phy@0 { 229 compatible = "ethernet-phy-ieee802.3-c22"; 230 reg = <0x0>; 231 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 232 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 233 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 234 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 235 236 leds { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 240 led@1 { 241 reg = <1>; 242 color = <LED_COLOR_ID_AMBER>; 243 function = LED_FUNCTION_LAN; 244 default-state = "keep"; 245 }; 246 247 led@2 { 248 reg = <2>; 249 color = <LED_COLOR_ID_GREEN>; 250 function = LED_FUNCTION_LAN; 251 default-state = "keep"; 252 }; 253 }; 254 }; 255 }; 256}; 257 258&fec { 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_fec>; 261 phy-mode = "rgmii-id"; 262 local-mac-address = [00 00 00 00 00 00]; 263 status = "okay"; 264 265 fixed-link { 266 speed = <1000>; 267 full-duplex; 268 }; 269}; 270 271&flexcan1 { 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_flexcan1>; 274 xceiver-supply = <®_can1_stby>; 275 status = "okay"; 276}; 277 278&flexcan2 { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_flexcan2>; 281 xceiver-supply = <®_can2_stby>; 282 status = "okay"; 283}; 284 285&gpio1 { 286 gpio-line-names = 287 "", "", "", "", "", "", "", "", 288 "", "dio0", "", "dio1", "", "", "", "", 289 "", "", "", "", "", "", "", "", 290 "", "", "", "", "", "", "", ""; 291}; 292 293&gpio2 { 294 gpio-line-names = 295 "", "", "", "", "", "", "m2_pin20", "", 296 "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", 297 "", "", "pcie2_wdis#", "", "", "", "", "", 298 "", "", "", "", "", "", "", ""; 299}; 300 301&gpio3 { 302 gpio-line-names = 303 "", "", "", "", "", "", "m2_rst", "", 304 "", "", "", "", "", "", "m2_gpio10", "", 305 "", "", "", "", "", "", "", "", 306 "", "", "", "", "", "", "", ""; 307}; 308 309&gpio4 { 310 gpio-line-names = 311 "", "", "m2_off#", "", "", "", "", "", 312 "", "", "", "", "", "", "", "", 313 "", "", "m2_wdis#", "", "", "", "", "", 314 "", "", "", "", "", "", "", "rs485_en"; 315}; 316 317&gpio5 { 318 gpio-line-names = 319 "rs485_hd", "rs485_term", "", "", "", "", "", "", 320 "", "", "", "", "", "", "", "", 321 "", "", "", "", "", "", "", "", 322 "", "", "", "", "", "", "", ""; 323}; 324 325&i2c1 { 326 clock-frequency = <100000>; 327 pinctrl-names = "default", "gpio"; 328 pinctrl-0 = <&pinctrl_i2c1>; 329 pinctrl-1 = <&pinctrl_i2c1_gpio>; 330 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 331 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 332 status = "okay"; 333 334 gsc: gsc@20 { 335 compatible = "gw,gsc"; 336 reg = <0x20>; 337 pinctrl-0 = <&pinctrl_gsc>; 338 interrupt-parent = <&gpio4>; 339 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 340 interrupt-controller; 341 #interrupt-cells = <1>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 345 adc { 346 compatible = "gw,gsc-adc"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 350 channel@6 { 351 gw,mode = <0>; 352 reg = <0x06>; 353 label = "temp"; 354 }; 355 356 channel@8 { 357 gw,mode = <3>; 358 reg = <0x08>; 359 label = "vdd_bat"; 360 }; 361 362 channel@16 { 363 gw,mode = <4>; 364 reg = <0x16>; 365 label = "fan_tach"; 366 }; 367 368 channel@82 { 369 gw,mode = <2>; 370 reg = <0x82>; 371 label = "vdd_adc1"; 372 gw,voltage-divider-ohms = <10000 10000>; 373 }; 374 375 channel@84 { 376 gw,mode = <2>; 377 reg = <0x84>; 378 label = "vdd_adc2"; 379 gw,voltage-divider-ohms = <10000 10000>; 380 }; 381 382 channel@86 { 383 gw,mode = <2>; 384 reg = <0x86>; 385 label = "vdd_vin"; 386 gw,voltage-divider-ohms = <22100 1000>; 387 }; 388 389 channel@88 { 390 gw,mode = <2>; 391 reg = <0x88>; 392 label = "vdd_3p3"; 393 gw,voltage-divider-ohms = <10000 10000>; 394 }; 395 396 channel@8c { 397 gw,mode = <2>; 398 reg = <0x8c>; 399 label = "vdd_2p5"; 400 gw,voltage-divider-ohms = <10000 10000>; 401 }; 402 403 channel@90 { 404 gw,mode = <2>; 405 reg = <0x90>; 406 label = "vdd_soc"; 407 }; 408 409 channel@92 { 410 gw,mode = <2>; 411 reg = <0x92>; 412 label = "vdd_arm"; 413 }; 414 415 channel@98 { 416 gw,mode = <2>; 417 reg = <0x98>; 418 label = "vdd_1p8"; 419 }; 420 421 channel@9a { 422 gw,mode = <2>; 423 reg = <0x9a>; 424 label = "vdd_1p2"; 425 }; 426 427 channel@9c { 428 gw,mode = <2>; 429 reg = <0x9c>; 430 label = "vdd_dram"; 431 }; 432 433 channel@9e { 434 gw,mode = <2>; 435 reg = <0x9e>; 436 label = "vdd_1p0"; 437 }; 438 439 channel@a2 { 440 gw,mode = <2>; 441 reg = <0xa2>; 442 label = "vdd_gsc"; 443 gw,voltage-divider-ohms = <10000 10000>; 444 }; 445 }; 446 447 fan-controller@a { 448 compatible = "gw,gsc-fan"; 449 reg = <0x0a>; 450 }; 451 }; 452 453 gpio: gpio@23 { 454 compatible = "nxp,pca9555"; 455 reg = <0x23>; 456 gpio-controller; 457 #gpio-cells = <2>; 458 interrupt-parent = <&gsc>; 459 interrupts = <4>; 460 }; 461 462 eeprom@50 { 463 compatible = "atmel,24c02"; 464 reg = <0x50>; 465 pagesize = <16>; 466 }; 467 468 eeprom@51 { 469 compatible = "atmel,24c02"; 470 reg = <0x51>; 471 pagesize = <16>; 472 }; 473 474 eeprom@52 { 475 compatible = "atmel,24c02"; 476 reg = <0x52>; 477 pagesize = <16>; 478 }; 479 480 eeprom@53 { 481 compatible = "atmel,24c02"; 482 reg = <0x53>; 483 pagesize = <16>; 484 }; 485 486 gsc_rtc: rtc@68 { 487 compatible = "dallas,ds1672"; 488 reg = <0x68>; 489 }; 490}; 491 492&i2c2 { 493 clock-frequency = <400000>; 494 pinctrl-names = "default", "gpio"; 495 pinctrl-0 = <&pinctrl_i2c2>; 496 pinctrl-1 = <&pinctrl_i2c2_gpio>; 497 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 498 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 499 status = "okay"; 500 501 accelerometer@19 { 502 compatible = "st,lis2de12"; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&pinctrl_accel>; 505 reg = <0x19>; 506 st,drdy-int-pin = <1>; 507 interrupt-parent = <&gpio1>; 508 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 509 }; 510 511 switch: switch@5f { 512 compatible = "microchip,ksz9897"; 513 reg = <0x5f>; 514 pinctrl-0 = <&pinctrl_ksz>; 515 interrupt-parent = <&gpio4>; 516 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 517 518 ports { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 522 lan1: port@0 { 523 reg = <0>; 524 label = "lan1"; 525 phy-mode = "internal"; 526 local-mac-address = [00 00 00 00 00 00]; 527 }; 528 529 lan2: port@1 { 530 reg = <1>; 531 label = "lan2"; 532 phy-mode = "internal"; 533 local-mac-address = [00 00 00 00 00 00]; 534 }; 535 536 lan3: port@2 { 537 reg = <2>; 538 label = "lan3"; 539 phy-mode = "internal"; 540 local-mac-address = [00 00 00 00 00 00]; 541 }; 542 543 lan4: port@3 { 544 reg = <3>; 545 label = "lan4"; 546 phy-mode = "internal"; 547 local-mac-address = [00 00 00 00 00 00]; 548 }; 549 550 lan5: port@4 { 551 reg = <4>; 552 label = "lan5"; 553 phy-mode = "internal"; 554 local-mac-address = [00 00 00 00 00 00]; 555 }; 556 557 port@5 { 558 reg = <5>; 559 ethernet = <&fec>; 560 phy-mode = "rgmii-id"; 561 562 fixed-link { 563 speed = <1000>; 564 full-duplex; 565 }; 566 }; 567 }; 568 }; 569}; 570 571&i2c3 { 572 clock-frequency = <400000>; 573 pinctrl-names = "default", "gpio"; 574 pinctrl-0 = <&pinctrl_i2c3>; 575 pinctrl-1 = <&pinctrl_i2c3_gpio>; 576 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 577 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 578 status = "okay"; 579 580 pmic@25 { 581 compatible = "nxp,pca9450c"; 582 reg = <0x25>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pinctrl_pmic>; 585 interrupt-parent = <&gpio3>; 586 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 587 588 regulators { 589 BUCK1 { 590 regulator-name = "BUCK1"; 591 regulator-min-microvolt = <720000>; 592 regulator-max-microvolt = <1000000>; 593 regulator-boot-on; 594 regulator-always-on; 595 regulator-ramp-delay = <3125>; 596 }; 597 598 reg_arm: BUCK2 { 599 regulator-name = "BUCK2"; 600 regulator-min-microvolt = <720000>; 601 regulator-max-microvolt = <1025000>; 602 regulator-boot-on; 603 regulator-always-on; 604 regulator-ramp-delay = <3125>; 605 nxp,dvs-run-voltage = <950000>; 606 nxp,dvs-standby-voltage = <850000>; 607 }; 608 609 BUCK4 { 610 regulator-name = "BUCK4"; 611 regulator-min-microvolt = <3000000>; 612 regulator-max-microvolt = <3600000>; 613 regulator-boot-on; 614 regulator-always-on; 615 }; 616 617 BUCK5 { 618 regulator-name = "BUCK5"; 619 regulator-min-microvolt = <1650000>; 620 regulator-max-microvolt = <1950000>; 621 regulator-boot-on; 622 regulator-always-on; 623 }; 624 625 BUCK6 { 626 regulator-name = "BUCK6"; 627 regulator-min-microvolt = <1045000>; 628 regulator-max-microvolt = <1155000>; 629 regulator-boot-on; 630 regulator-always-on; 631 }; 632 633 LDO1 { 634 regulator-name = "LDO1"; 635 regulator-min-microvolt = <1650000>; 636 regulator-max-microvolt = <1950000>; 637 regulator-boot-on; 638 regulator-always-on; 639 }; 640 641 LDO3 { 642 regulator-name = "LDO3"; 643 regulator-min-microvolt = <1710000>; 644 regulator-max-microvolt = <1890000>; 645 regulator-boot-on; 646 regulator-always-on; 647 }; 648 649 LDO5 { 650 regulator-name = "LDO5"; 651 regulator-min-microvolt = <1800000>; 652 regulator-max-microvolt = <3300000>; 653 regulator-boot-on; 654 regulator-always-on; 655 }; 656 }; 657 }; 658}; 659 660/* off-board header */ 661&i2c4 { 662 clock-frequency = <400000>; 663 pinctrl-names = "default", "gpio"; 664 pinctrl-0 = <&pinctrl_i2c4>; 665 pinctrl-1 = <&pinctrl_i2c4_gpio>; 666 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 667 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 668 status = "okay"; 669}; 670 671&pcie_phy { 672 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 673 fsl,clkreq-unsupported; 674 clocks = <&pcie0_refclk>; 675 clock-names = "ref"; 676 status = "okay"; 677}; 678 679&pcie { 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_pcie0>; 682 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; 683 status = "okay"; 684}; 685 686/* GPS / off-board header */ 687&uart1 { 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pinctrl_uart1>; 690 status = "okay"; 691}; 692 693/* RS232 console */ 694&uart2 { 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_uart2>; 697 status = "okay"; 698}; 699 700/* bluetooth HCI */ 701&uart3 { 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 704 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 705 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 706 status = "okay"; 707 708 bluetooth { 709 compatible = "brcm,bcm4330-bt"; 710 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; 711 }; 712}; 713 714&uart4 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_uart4>; 717 status = "okay"; 718}; 719 720/* USB1 - Type C front panel */ 721&usb3_0 { 722 pinctrl-names = "default"; 723 pinctrl-0 = <&pinctrl_usb1>; 724 fsl,over-current-active-low; 725 status = "okay"; 726}; 727 728&usb3_phy0 { 729 status = "okay"; 730}; 731 732&usb_dwc3_0 { 733 /* dual role is implemented but not a full featured OTG */ 734 adp-disable; 735 hnp-disable; 736 srp-disable; 737 dr_mode = "otg"; 738 usb-role-switch; 739 role-switch-default-mode = "peripheral"; 740 status = "okay"; 741 742 port { 743 usb3_dwc: endpoint { 744 remote-endpoint = <&usb_dr_connector>; 745 }; 746 }; 747}; 748 749/* USB2 - USB3.0 Hub */ 750&usb3_phy1 { 751 vbus-supply = <®_usb2_vbus>; 752 status = "okay"; 753}; 754 755&usb3_1 { 756 fsl,permanently-attached; 757 fsl,disable-port-power-control; 758 status = "okay"; 759}; 760 761&usb_dwc3_1 { 762 dr_mode = "host"; 763 status = "okay"; 764}; 765 766/* SDIO WiFi */ 767&usdhc1 { 768 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 769 pinctrl-0 = <&pinctrl_usdhc1>; 770 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 771 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 772 bus-width = <4>; 773 non-removable; 774 vmmc-supply = <®_wifi_en>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 status = "okay"; 778 779 wifi@0 { 780 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 781 reg = <0>; 782 }; 783}; 784 785/* eMMC */ 786&usdhc3 { 787 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 788 assigned-clock-rates = <400000000>; 789 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 790 pinctrl-0 = <&pinctrl_usdhc3>; 791 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 792 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 793 bus-width = <8>; 794 non-removable; 795 status = "okay"; 796}; 797 798&wdog1 { 799 pinctrl-names = "default"; 800 pinctrl-0 = <&pinctrl_wdog>; 801 fsl,ext-reset-output; 802 status = "okay"; 803}; 804 805&iomuxc { 806 pinctrl-names = "default"; 807 pinctrl-0 = <&pinctrl_hog>; 808 809 pinctrl_hog: hoggrp { 810 fsl,pins = < 811 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ 812 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ 813 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ 814 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ 815 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ 816 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ 817 MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ 818 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 819 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 820 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 821 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */ 822 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 823 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 824 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ 825 >; 826 }; 827 828 pinctrl_accel: accelgrp { 829 fsl,pins = < 830 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 831 >; 832 }; 833 834 pinctrl_eqos: eqosgrp { 835 fsl,pins = < 836 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 837 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 838 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 839 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 840 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 841 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 842 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 843 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 844 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 845 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 846 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 847 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 848 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 849 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 850 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ 851 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ 852 >; 853 }; 854 855 pinctrl_fec: fecgrp { 856 fsl,pins = < 857 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 858 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 859 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 860 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 861 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 862 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 863 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 864 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 865 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 866 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 867 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 868 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 869 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 870 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 871 >; 872 }; 873 874 pinctrl_flexcan1: flexcan1grp { 875 fsl,pins = < 876 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 877 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 878 >; 879 }; 880 881 pinctrl_flexcan2: flexcan2grp { 882 fsl,pins = < 883 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 884 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 885 >; 886 }; 887 888 pinctrl_gsc: gscgrp { 889 fsl,pins = < 890 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 891 >; 892 }; 893 894 pinctrl_i2c1: i2c1grp { 895 fsl,pins = < 896 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 897 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 898 >; 899 }; 900 901 pinctrl_i2c1_gpio: i2c1gpiogrp { 902 fsl,pins = < 903 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 904 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 905 >; 906 }; 907 908 pinctrl_i2c2: i2c2grp { 909 fsl,pins = < 910 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 911 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 912 >; 913 }; 914 915 pinctrl_i2c2_gpio: i2c2gpiogrp { 916 fsl,pins = < 917 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 918 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 919 >; 920 }; 921 922 pinctrl_i2c3: i2c3grp { 923 fsl,pins = < 924 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 925 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 926 >; 927 }; 928 929 pinctrl_i2c3_gpio: i2c3gpiogrp { 930 fsl,pins = < 931 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 932 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 933 >; 934 }; 935 936 pinctrl_i2c4: i2c4grp { 937 fsl,pins = < 938 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 939 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 940 >; 941 }; 942 943 pinctrl_i2c4_gpio: i2c4gpiogrp { 944 fsl,pins = < 945 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 946 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 947 >; 948 }; 949 950 pinctrl_ksz: kszgrp { 951 fsl,pins = < 952 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ 953 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ 954 >; 955 }; 956 957 pinctrl_gpio_leds: ledgrp { 958 fsl,pins = < 959 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 960 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 961 >; 962 }; 963 964 pinctrl_pcie0: pciegrp { 965 fsl,pins = < 966 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 967 >; 968 }; 969 970 pinctrl_pmic: pmicgrp { 971 fsl,pins = < 972 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 973 >; 974 }; 975 976 pinctrl_pps: ppsgrp { 977 fsl,pins = < 978 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 979 >; 980 }; 981 982 pinctrl_reg_can1: regcan1grp { 983 fsl,pins = < 984 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 985 >; 986 }; 987 988 pinctrl_reg_can2: regcan2grp { 989 fsl,pins = < 990 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 991 >; 992 }; 993 994 pinctrl_reg_usb2: regusb2grp { 995 fsl,pins = < 996 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 997 >; 998 }; 999 1000 pinctrl_reg_wifi: regwifigrp { 1001 fsl,pins = < 1002 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 1003 >; 1004 }; 1005 1006 pinctrl_spi1: spi1grp { 1007 fsl,pins = < 1008 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 1009 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 1010 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 1011 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 1012 >; 1013 }; 1014 1015 pinctrl_spi2: spi2grp { 1016 fsl,pins = < 1017 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 1018 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 1019 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 1020 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 1021 >; 1022 }; 1023 1024 pinctrl_uart1: uart1grp { 1025 fsl,pins = < 1026 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 1027 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 1028 >; 1029 }; 1030 1031 pinctrl_uart2: uart2grp { 1032 fsl,pins = < 1033 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 1034 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 1035 >; 1036 }; 1037 1038 pinctrl_uart3: uart3grp { 1039 fsl,pins = < 1040 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 1041 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 1042 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 1043 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 1044 >; 1045 }; 1046 1047 pinctrl_uart3_gpio: uart3gpiogrp { 1048 fsl,pins = < 1049 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 1050 >; 1051 }; 1052 1053 pinctrl_uart4: uart4grp { 1054 fsl,pins = < 1055 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 1056 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 1057 >; 1058 }; 1059 1060 pinctrl_usb1: usb1grp { 1061 fsl,pins = < 1062 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 1063 >; 1064 }; 1065 1066 pinctrl_usbcon1: usb1congrp { 1067 fsl,pins = < 1068 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 1069 >; 1070 }; 1071 1072 pinctrl_usdhc1: usdhc1grp { 1073 fsl,pins = < 1074 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 1075 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 1076 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 1077 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 1078 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 1079 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 1080 >; 1081 }; 1082 1083 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1084 fsl,pins = < 1085 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 1086 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 1087 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 1088 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 1089 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 1090 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 1091 >; 1092 }; 1093 1094 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1095 fsl,pins = < 1096 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 1097 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 1098 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 1099 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 1100 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 1101 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 1102 >; 1103 }; 1104 1105 pinctrl_usdhc3: usdhc3grp { 1106 fsl,pins = < 1107 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1108 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1109 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1110 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1111 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1112 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1113 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1114 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1115 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1116 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1117 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1118 >; 1119 }; 1120 1121 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1122 fsl,pins = < 1123 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1124 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1125 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1126 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1127 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1128 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1129 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1130 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1131 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1132 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1133 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1134 >; 1135 }; 1136 1137 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1138 fsl,pins = < 1139 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1140 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1141 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1142 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1143 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1144 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1145 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1146 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1147 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1148 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1149 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1150 >; 1151 }; 1152 1153 pinctrl_wdog: wdoggrp { 1154 fsl,pins = < 1155 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 1156 >; 1157 }; 1158}; 1159