xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts (revision 90d32e92011eaae8e70a9169b4e7acf4ca8f9d3a) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mp.dtsi"
14
15/ {
16	model = "Gateworks Venice GW74xx i.MX8MP board";
17	compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
18
19	aliases {
20		ethernet0 = &eqos;
21		ethernet1 = &fec;
22		ethernet2 = &lan1;
23		ethernet3 = &lan2;
24		ethernet4 = &lan3;
25		ethernet5 = &lan4;
26		ethernet6 = &lan5;
27	};
28
29	chosen {
30		stdout-path = &uart2;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0 0x80000000>;
36	};
37
38	connector {
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_usbcon1>;
41		compatible = "gpio-usb-b-connector", "usb-b-connector";
42		type = "micro";
43		label = "Type-C";
44		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
45
46		port {
47			usb_dr_connector: endpoint {
48				remote-endpoint = <&usb3_dwc>;
49			};
50		};
51	};
52
53	gpio-keys {
54		compatible = "gpio-keys";
55
56		key-0 {
57			label = "user_pb";
58			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
59			linux,code = <BTN_0>;
60		};
61
62		key-1 {
63			label = "user_pb1x";
64			linux,code = <BTN_1>;
65			interrupt-parent = <&gsc>;
66			interrupts = <0>;
67		};
68
69		key-2 {
70			label = "key_erased";
71			linux,code = <BTN_2>;
72			interrupt-parent = <&gsc>;
73			interrupts = <1>;
74		};
75
76		key-3 {
77			label = "eeprom_wp";
78			linux,code = <BTN_3>;
79			interrupt-parent = <&gsc>;
80			interrupts = <2>;
81		};
82
83		key-4 {
84			label = "tamper";
85			linux,code = <BTN_4>;
86			interrupt-parent = <&gsc>;
87			interrupts = <5>;
88		};
89
90		key-5 {
91			label = "switch_hold";
92			linux,code = <BTN_5>;
93			interrupt-parent = <&gsc>;
94			interrupts = <7>;
95		};
96	};
97
98	led-controller {
99		compatible = "gpio-leds";
100		pinctrl-names = "default";
101		pinctrl-0 = <&pinctrl_gpio_leds>;
102
103		led-0 {
104			function = LED_FUNCTION_HEARTBEAT;
105			color = <LED_COLOR_ID_GREEN>;
106			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
107			default-state = "on";
108			linux,default-trigger = "heartbeat";
109		};
110
111		led-1 {
112			function = LED_FUNCTION_STATUS;
113			color = <LED_COLOR_ID_RED>;
114			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
115			default-state = "off";
116		};
117	};
118
119	pcie0_refclk: pcie0-refclk {
120		compatible = "fixed-clock";
121		#clock-cells = <0>;
122		clock-frequency = <100000000>;
123	};
124
125	pps {
126		compatible = "pps-gpio";
127		pinctrl-names = "default";
128		pinctrl-0 = <&pinctrl_pps>;
129		gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
130	};
131
132	reg_usb2_vbus: regulator-usb2 {
133		pinctrl-names = "default";
134		pinctrl-0 = <&pinctrl_reg_usb2>;
135		compatible = "regulator-fixed";
136		regulator-name = "usb_usb2_vbus";
137		gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
138		enable-active-high;
139		regulator-min-microvolt = <5000000>;
140		regulator-max-microvolt = <5000000>;
141	};
142
143	reg_can1_stby: regulator-can1-stby {
144		compatible = "regulator-fixed";
145		pinctrl-names = "default";
146		pinctrl-0 = <&pinctrl_reg_can1>;
147		regulator-name = "can1_stby";
148		gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
149		regulator-min-microvolt = <3300000>;
150		regulator-max-microvolt = <3300000>;
151	};
152
153	reg_can2_stby: regulator-can2-stby {
154		compatible = "regulator-fixed";
155		pinctrl-names = "default";
156		pinctrl-0 = <&pinctrl_reg_can2>;
157		regulator-name = "can2_stby";
158		gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
159		regulator-min-microvolt = <3300000>;
160		regulator-max-microvolt = <3300000>;
161	};
162
163	reg_wifi_en: regulator-wifi-en {
164		pinctrl-names = "default";
165		pinctrl-0 = <&pinctrl_reg_wifi>;
166		compatible = "regulator-fixed";
167		regulator-name = "wl";
168		gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
169		startup-delay-us = <70000>;
170		enable-active-high;
171		regulator-min-microvolt = <3300000>;
172		regulator-max-microvolt = <3300000>;
173	};
174};
175
176&A53_0 {
177	cpu-supply = <&reg_arm>;
178};
179
180&A53_1 {
181	cpu-supply = <&reg_arm>;
182};
183
184&A53_2 {
185	cpu-supply = <&reg_arm>;
186};
187
188&A53_3 {
189	cpu-supply = <&reg_arm>;
190};
191
192&ecspi1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_spi1>;
195	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
196	status = "okay";
197
198	tpm@0 {
199		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
200		reg = <0x0>;
201		spi-max-frequency = <36000000>;
202	};
203};
204
205/* off-board header */
206&ecspi2 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_spi2>;
209	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
210	status = "okay";
211};
212
213&eqos {
214	pinctrl-names = "default";
215	pinctrl-0 = <&pinctrl_eqos>;
216	phy-mode = "rgmii-id";
217	phy-handle = <&ethphy0>;
218	status = "okay";
219
220	mdio {
221		compatible = "snps,dwmac-mdio";
222		#address-cells = <1>;
223		#size-cells = <0>;
224
225		ethphy0: ethernet-phy@0 {
226			compatible = "ethernet-phy-ieee802.3-c22";
227			reg = <0x0>;
228		};
229	};
230};
231
232&fec {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_fec>;
235	phy-mode = "rgmii-id";
236	local-mac-address = [00 00 00 00 00 00];
237	status = "okay";
238
239	fixed-link {
240		speed = <1000>;
241		full-duplex;
242	};
243};
244
245&flexcan1 {
246	pinctrl-names = "default";
247	pinctrl-0 = <&pinctrl_flexcan1>;
248	xceiver-supply = <&reg_can1_stby>;
249	status = "okay";
250};
251
252&flexcan2 {
253	pinctrl-names = "default";
254	pinctrl-0 = <&pinctrl_flexcan2>;
255	xceiver-supply = <&reg_can2_stby>;
256	status = "okay";
257};
258
259&gpio1 {
260	gpio-line-names =
261		"", "", "", "", "", "", "", "",
262		"", "dio0", "", "dio1", "", "", "", "",
263		"", "", "", "", "", "", "", "",
264		"", "", "", "", "", "", "", "";
265};
266
267&gpio2 {
268	gpio-line-names =
269		"", "", "", "", "", "", "m2_pin20", "",
270		"", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
271		"", "", "pcie2_wdis#", "", "", "", "", "",
272		"", "", "", "", "", "", "", "";
273};
274
275&gpio3 {
276	gpio-line-names =
277		"", "", "", "", "", "", "m2_rst", "",
278		"", "", "", "", "", "", "", "",
279		"", "", "", "", "", "", "", "",
280		"", "", "", "", "", "", "", "";
281};
282
283&gpio4 {
284	gpio-line-names =
285		"", "", "m2_off#", "", "", "", "", "",
286		"", "", "", "", "", "", "", "",
287		"", "", "m2_wdis#", "", "", "", "", "",
288		"", "", "", "", "", "", "", "rs485_en";
289};
290
291&gpio5 {
292	gpio-line-names =
293		"rs485_hd", "rs485_term", "", "", "", "", "", "",
294		"", "", "", "", "", "", "", "",
295		"", "", "", "", "", "", "", "",
296		"", "", "", "", "", "", "", "";
297};
298
299&i2c1 {
300	clock-frequency = <100000>;
301	pinctrl-names = "default", "gpio";
302	pinctrl-0 = <&pinctrl_i2c1>;
303	pinctrl-1 = <&pinctrl_i2c1_gpio>;
304	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
305	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
306	status = "okay";
307
308	gsc: gsc@20 {
309		compatible = "gw,gsc";
310		reg = <0x20>;
311		pinctrl-0 = <&pinctrl_gsc>;
312		interrupt-parent = <&gpio4>;
313		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
314		interrupt-controller;
315		#interrupt-cells = <1>;
316		#address-cells = <1>;
317		#size-cells = <0>;
318
319		adc {
320			compatible = "gw,gsc-adc";
321			#address-cells = <1>;
322			#size-cells = <0>;
323
324			channel@6 {
325				gw,mode = <0>;
326				reg = <0x06>;
327				label = "temp";
328			};
329
330			channel@8 {
331				gw,mode = <3>;
332				reg = <0x08>;
333				label = "vdd_bat";
334			};
335
336			channel@16 {
337				gw,mode = <4>;
338				reg = <0x16>;
339				label = "fan_tach";
340			};
341
342			channel@82 {
343				gw,mode = <2>;
344				reg = <0x82>;
345				label = "vdd_adc1";
346				gw,voltage-divider-ohms = <10000 10000>;
347			};
348
349			channel@84 {
350				gw,mode = <2>;
351				reg = <0x84>;
352				label = "vdd_adc2";
353				gw,voltage-divider-ohms = <10000 10000>;
354			};
355
356			channel@86 {
357				gw,mode = <2>;
358				reg = <0x86>;
359				label = "vdd_vin";
360				gw,voltage-divider-ohms = <22100 1000>;
361			};
362
363			channel@88 {
364				gw,mode = <2>;
365				reg = <0x88>;
366				label = "vdd_3p3";
367				gw,voltage-divider-ohms = <10000 10000>;
368			};
369
370			channel@8c {
371				gw,mode = <2>;
372				reg = <0x8c>;
373				label = "vdd_2p5";
374				gw,voltage-divider-ohms = <10000 10000>;
375			};
376
377			channel@90 {
378				gw,mode = <2>;
379				reg = <0x90>;
380				label = "vdd_soc";
381			};
382
383			channel@92 {
384				gw,mode = <2>;
385				reg = <0x92>;
386				label = "vdd_arm";
387			};
388
389			channel@98 {
390				gw,mode = <2>;
391				reg = <0x98>;
392				label = "vdd_1p8";
393			};
394
395			channel@9a {
396				gw,mode = <2>;
397				reg = <0x9a>;
398				label = "vdd_1p2";
399			};
400
401			channel@9c {
402				gw,mode = <2>;
403				reg = <0x9c>;
404				label = "vdd_dram";
405			};
406
407			channel@9e {
408				gw,mode = <2>;
409				reg = <0x9e>;
410				label = "vdd_1p0";
411			};
412
413			channel@a2 {
414				gw,mode = <2>;
415				reg = <0xa2>;
416				label = "vdd_gsc";
417				gw,voltage-divider-ohms = <10000 10000>;
418			};
419		};
420
421		fan-controller@a {
422			compatible = "gw,gsc-fan";
423			reg = <0x0a>;
424		};
425	};
426
427	gpio: gpio@23 {
428		compatible = "nxp,pca9555";
429		reg = <0x23>;
430		gpio-controller;
431		#gpio-cells = <2>;
432		interrupt-parent = <&gsc>;
433		interrupts = <4>;
434	};
435
436	eeprom@50 {
437		compatible = "atmel,24c02";
438		reg = <0x50>;
439		pagesize = <16>;
440	};
441
442	eeprom@51 {
443		compatible = "atmel,24c02";
444		reg = <0x51>;
445		pagesize = <16>;
446	};
447
448	eeprom@52 {
449		compatible = "atmel,24c02";
450		reg = <0x52>;
451		pagesize = <16>;
452	};
453
454	eeprom@53 {
455		compatible = "atmel,24c02";
456		reg = <0x53>;
457		pagesize = <16>;
458	};
459
460	rtc@68 {
461		compatible = "dallas,ds1672";
462		reg = <0x68>;
463	};
464};
465
466&i2c2 {
467	clock-frequency = <400000>;
468	pinctrl-names = "default", "gpio";
469	pinctrl-0 = <&pinctrl_i2c2>;
470	pinctrl-1 = <&pinctrl_i2c2_gpio>;
471	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
472	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
473	status = "okay";
474
475	accelerometer@19 {
476		compatible = "st,lis2de12";
477		pinctrl-names = "default";
478		pinctrl-0 = <&pinctrl_accel>;
479		reg = <0x19>;
480		st,drdy-int-pin = <1>;
481		interrupt-parent = <&gpio1>;
482		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
483	};
484
485	switch: switch@5f {
486		compatible = "microchip,ksz9897";
487		reg = <0x5f>;
488		pinctrl-0 = <&pinctrl_ksz>;
489		interrupt-parent = <&gpio4>;
490		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
491
492		ports {
493			#address-cells = <1>;
494			#size-cells = <0>;
495
496			lan1: port@0 {
497				reg = <0>;
498				label = "lan1";
499				phy-mode = "internal";
500				local-mac-address = [00 00 00 00 00 00];
501			};
502
503			lan2: port@1 {
504				reg = <1>;
505				label = "lan2";
506				phy-mode = "internal";
507				local-mac-address = [00 00 00 00 00 00];
508			};
509
510			lan3: port@2 {
511				reg = <2>;
512				label = "lan3";
513				phy-mode = "internal";
514				local-mac-address = [00 00 00 00 00 00];
515			};
516
517			lan4: port@3 {
518				reg = <3>;
519				label = "lan4";
520				phy-mode = "internal";
521				local-mac-address = [00 00 00 00 00 00];
522			};
523
524			lan5: port@4 {
525				reg = <4>;
526				label = "lan5";
527				phy-mode = "internal";
528				local-mac-address = [00 00 00 00 00 00];
529			};
530
531			port@5 {
532				reg = <5>;
533				ethernet = <&fec>;
534				phy-mode = "rgmii-id";
535
536				fixed-link {
537					speed = <1000>;
538					full-duplex;
539				};
540			};
541		};
542	};
543};
544
545&i2c3 {
546	clock-frequency = <400000>;
547	pinctrl-names = "default", "gpio";
548	pinctrl-0 = <&pinctrl_i2c3>;
549	pinctrl-1 = <&pinctrl_i2c3_gpio>;
550	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
551	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
552	status = "okay";
553
554	pmic@25 {
555		compatible = "nxp,pca9450c";
556		reg = <0x25>;
557		pinctrl-names = "default";
558		pinctrl-0 = <&pinctrl_pmic>;
559		interrupt-parent = <&gpio3>;
560		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
561
562		regulators {
563			BUCK1 {
564				regulator-name = "BUCK1";
565				regulator-min-microvolt = <720000>;
566				regulator-max-microvolt = <1000000>;
567				regulator-boot-on;
568				regulator-always-on;
569				regulator-ramp-delay = <3125>;
570			};
571
572			reg_arm: BUCK2 {
573				regulator-name = "BUCK2";
574				regulator-min-microvolt = <720000>;
575				regulator-max-microvolt = <1025000>;
576				regulator-boot-on;
577				regulator-always-on;
578				regulator-ramp-delay = <3125>;
579				nxp,dvs-run-voltage = <950000>;
580				nxp,dvs-standby-voltage = <850000>;
581			};
582
583			BUCK4 {
584				regulator-name = "BUCK4";
585				regulator-min-microvolt = <3000000>;
586				regulator-max-microvolt = <3600000>;
587				regulator-boot-on;
588				regulator-always-on;
589			};
590
591			BUCK5 {
592				regulator-name = "BUCK5";
593				regulator-min-microvolt = <1650000>;
594				regulator-max-microvolt = <1950000>;
595				regulator-boot-on;
596				regulator-always-on;
597			};
598
599			BUCK6 {
600				regulator-name = "BUCK6";
601				regulator-min-microvolt = <1045000>;
602				regulator-max-microvolt = <1155000>;
603				regulator-boot-on;
604				regulator-always-on;
605			};
606
607			LDO1 {
608				regulator-name = "LDO1";
609				regulator-min-microvolt = <1650000>;
610				regulator-max-microvolt = <1950000>;
611				regulator-boot-on;
612				regulator-always-on;
613			};
614
615			LDO3 {
616				regulator-name = "LDO3";
617				regulator-min-microvolt = <1710000>;
618				regulator-max-microvolt = <1890000>;
619				regulator-boot-on;
620				regulator-always-on;
621			};
622
623			LDO5 {
624				regulator-name = "LDO5";
625				regulator-min-microvolt = <1800000>;
626				regulator-max-microvolt = <3300000>;
627				regulator-boot-on;
628				regulator-always-on;
629			};
630		};
631	};
632};
633
634/* off-board header */
635&i2c4 {
636	clock-frequency = <400000>;
637	pinctrl-names = "default", "gpio";
638	pinctrl-0 = <&pinctrl_i2c4>;
639	pinctrl-1 = <&pinctrl_i2c4_gpio>;
640	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
641	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
642	status = "okay";
643};
644
645&pcie_phy {
646	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
647	fsl,clkreq-unsupported;
648	clocks = <&pcie0_refclk>;
649	clock-names = "ref";
650	status = "okay";
651};
652
653&pcie {
654	pinctrl-names = "default";
655	pinctrl-0 = <&pinctrl_pcie0>;
656	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
657	status = "okay";
658};
659
660/* GPS / off-board header */
661&uart1 {
662	pinctrl-names = "default";
663	pinctrl-0 = <&pinctrl_uart1>;
664	status = "okay";
665};
666
667/* RS232 console */
668&uart2 {
669	pinctrl-names = "default";
670	pinctrl-0 = <&pinctrl_uart2>;
671	status = "okay";
672};
673
674/* bluetooth HCI */
675&uart3 {
676	pinctrl-names = "default";
677	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
678	cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
679	rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
680	status = "okay";
681
682	bluetooth {
683		compatible = "brcm,bcm4330-bt";
684		shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
685	};
686};
687
688&uart4 {
689	pinctrl-names = "default";
690	pinctrl-0 = <&pinctrl_uart4>;
691	status = "okay";
692};
693
694/* USB1 - Type C front panel */
695&usb3_0 {
696	pinctrl-names = "default";
697	pinctrl-0 = <&pinctrl_usb1>;
698	fsl,over-current-active-low;
699	status = "okay";
700};
701
702&usb3_phy0 {
703	status = "okay";
704};
705
706&usb_dwc3_0 {
707	/* dual role is implemented but not a full featured OTG */
708	adp-disable;
709	hnp-disable;
710	srp-disable;
711	dr_mode = "otg";
712	usb-role-switch;
713	role-switch-default-mode = "peripheral";
714	status = "okay";
715
716	port {
717		usb3_dwc: endpoint {
718			remote-endpoint = <&usb_dr_connector>;
719		};
720	};
721};
722
723/* USB2 - USB3.0 Hub */
724&usb3_phy1 {
725	vbus-supply = <&reg_usb2_vbus>;
726	status = "okay";
727};
728
729&usb3_1 {
730	fsl,permanently-attached;
731	fsl,disable-port-power-control;
732	status = "okay";
733};
734
735&usb_dwc3_1 {
736	dr_mode = "host";
737	status = "okay";
738};
739
740/* SDIO WiFi */
741&usdhc1 {
742	pinctrl-names = "default", "state_100mhz", "state_200mhz";
743	pinctrl-0 = <&pinctrl_usdhc1>;
744	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
745	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
746	bus-width = <4>;
747	non-removable;
748	vmmc-supply = <&reg_wifi_en>;
749	#address-cells = <1>;
750	#size-cells = <0>;
751	status = "okay";
752
753	wifi@0 {
754		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
755		reg = <0>;
756	};
757};
758
759/* eMMC */
760&usdhc3 {
761	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
762	assigned-clock-rates = <400000000>;
763	pinctrl-names = "default", "state_100mhz", "state_200mhz";
764	pinctrl-0 = <&pinctrl_usdhc3>;
765	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
766	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
767	bus-width = <8>;
768	non-removable;
769	status = "okay";
770};
771
772&wdog1 {
773	pinctrl-names = "default";
774	pinctrl-0 = <&pinctrl_wdog>;
775	fsl,ext-reset-output;
776	status = "okay";
777};
778
779&iomuxc {
780	pinctrl-names = "default";
781	pinctrl-0 = <&pinctrl_hog>;
782
783	pinctrl_hog: hoggrp {
784		fsl,pins = <
785			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */
786			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */
787			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x40000040 /* M2SKT_OFF# */
788			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS# */
789			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40000040 /* M2SKT_PIN20 */
790			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11	0x40000040 /* M2SKT_PIN22 */
791			MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13	0x40000150 /* PCIE1_WDIS# */
792			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */
793			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */
794			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */
795			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */
796			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */
797			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */
798		>;
799	};
800
801	pinctrl_accel: accelgrp {
802		fsl,pins = <
803			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150
804		>;
805	};
806
807	pinctrl_eqos: eqosgrp {
808		fsl,pins = <
809			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
810			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
811			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
812			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
813			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
814			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
815			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
816			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
817			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
818			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
819			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
820			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
821			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
822			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
823			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */
824			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */
825		>;
826	};
827
828	pinctrl_fec: fecgrp {
829		fsl,pins = <
830			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
831			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
832			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
833			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
834			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
835			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
836			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
837			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
838			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
839			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
840			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
841			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
842			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140
843			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140
844		>;
845	};
846
847	pinctrl_flexcan1: flexcan1grp {
848		fsl,pins = <
849			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX		0x154
850			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX		0x154
851		>;
852	};
853
854	pinctrl_flexcan2: flexcan2grp {
855		fsl,pins = <
856			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
857			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
858		>;
859	};
860
861	pinctrl_gsc: gscgrp {
862		fsl,pins = <
863			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150
864		>;
865	};
866
867	pinctrl_i2c1: i2c1grp {
868		fsl,pins = <
869			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
870			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
871		>;
872	};
873
874	pinctrl_i2c1_gpio: i2c1gpiogrp {
875		fsl,pins = <
876			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
877			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
878		>;
879	};
880
881	pinctrl_i2c2: i2c2grp {
882		fsl,pins = <
883			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
884			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
885		>;
886	};
887
888	pinctrl_i2c2_gpio: i2c2gpiogrp {
889		fsl,pins = <
890			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c3
891			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c3
892		>;
893	};
894
895	pinctrl_i2c3: i2c3grp {
896		fsl,pins = <
897			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
898			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
899		>;
900	};
901
902	pinctrl_i2c3_gpio: i2c3gpiogrp {
903		fsl,pins = <
904			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c3
905			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c3
906		>;
907	};
908
909	pinctrl_i2c4: i2c4grp {
910		fsl,pins = <
911			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2
912			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2
913		>;
914	};
915
916	pinctrl_i2c4_gpio: i2c4gpiogrp {
917		fsl,pins = <
918			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x400001c3
919			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x400001c3
920		>;
921	};
922
923	pinctrl_ksz: kszgrp {
924		fsl,pins = <
925			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */
926			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */
927		>;
928	};
929
930	pinctrl_gpio_leds: ledgrp {
931		fsl,pins = <
932			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10
933			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10
934		>;
935	};
936
937	pinctrl_pcie0: pciegrp {
938		fsl,pins = <
939			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x106
940		>;
941	};
942
943	pinctrl_pmic: pmicgrp {
944		fsl,pins = <
945			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140
946		>;
947	};
948
949	pinctrl_pps: ppsgrp {
950		fsl,pins = <
951			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140
952		>;
953	};
954
955	pinctrl_reg_can1: regcan1grp {
956		fsl,pins = <
957			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x154
958		>;
959	};
960
961	pinctrl_reg_can2: regcan2grp {
962		fsl,pins = <
963			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x154
964		>;
965	};
966
967	pinctrl_reg_usb2: regusb2grp {
968		fsl,pins = <
969			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140
970		>;
971	};
972
973	pinctrl_reg_wifi: regwifigrp {
974		fsl,pins = <
975			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110
976		>;
977	};
978
979	pinctrl_spi1: spi1grp {
980		fsl,pins = <
981			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x82
982			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x82
983			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x82
984			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x140
985		>;
986	};
987
988	pinctrl_spi2: spi2grp {
989		fsl,pins = <
990			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82
991			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82
992			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82
993			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
994		>;
995	};
996
997	pinctrl_uart1: uart1grp {
998		fsl,pins = <
999			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
1000			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
1001		>;
1002	};
1003
1004	pinctrl_uart2: uart2grp {
1005		fsl,pins = <
1006			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
1007			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
1008		>;
1009	};
1010
1011	pinctrl_uart3: uart3grp {
1012		fsl,pins = <
1013			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
1014			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
1015			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140
1016			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22	0x140
1017		>;
1018	};
1019
1020	pinctrl_uart3_gpio: uart3gpiogrp {
1021		fsl,pins = <
1022			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110
1023		>;
1024	};
1025
1026	pinctrl_uart4: uart4grp {
1027		fsl,pins = <
1028			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140
1029			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140
1030		>;
1031	};
1032
1033	pinctrl_usb1: usb1grp {
1034		fsl,pins = <
1035			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140
1036		>;
1037	};
1038
1039	pinctrl_usbcon1: usb1congrp {
1040		fsl,pins = <
1041			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140
1042		>;
1043	};
1044
1045	pinctrl_usdhc1: usdhc1grp {
1046		fsl,pins = <
1047			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
1048			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
1049			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
1050			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
1051			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
1052			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
1053		>;
1054	};
1055
1056	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1057		fsl,pins = <
1058			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
1059			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
1060			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
1061			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
1062			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
1063			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
1064		>;
1065	};
1066
1067	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1068		fsl,pins = <
1069			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
1070			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
1071			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
1072			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
1073			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
1074			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
1075		>;
1076	};
1077
1078	pinctrl_usdhc3: usdhc3grp {
1079		fsl,pins = <
1080			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
1081			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
1082			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
1083			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
1084			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
1085			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
1086			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
1087			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
1088			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
1089			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
1090			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
1091		>;
1092	};
1093
1094	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1095		fsl,pins = <
1096			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
1097			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
1098			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
1099			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
1100			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
1101			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
1102			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
1103			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
1104			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
1105			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
1106			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
1107		>;
1108	};
1109
1110	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1111		fsl,pins = <
1112			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
1113			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
1114			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
1115			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
1116			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
1117			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
1118			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
1119			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
1120			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
1121			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
1122			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
1123		>;
1124	};
1125
1126	pinctrl_wdog: wdoggrp {
1127		fsl,pins = <
1128			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
1129		>;
1130	};
1131};
1132