xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/phy/phy-imx8-pcie.h>
12
13#include "imx8mp.dtsi"
14
15/ {
16	model = "Gateworks Venice GW74xx i.MX8MP board";
17	compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
18
19	aliases {
20		ethernet0 = &eqos;
21		ethernet1 = &fec;
22		ethernet2 = &lan1;
23		ethernet3 = &lan2;
24		ethernet4 = &lan3;
25		ethernet5 = &lan4;
26		ethernet6 = &lan5;
27	};
28
29	chosen {
30		stdout-path = &uart2;
31	};
32
33	memory@40000000 {
34		device_type = "memory";
35		reg = <0x0 0x40000000 0 0x80000000>;
36	};
37
38	gpio-keys {
39		compatible = "gpio-keys";
40
41		key-0 {
42			label = "user_pb";
43			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
44			linux,code = <BTN_0>;
45		};
46
47		key-1 {
48			label = "user_pb1x";
49			linux,code = <BTN_1>;
50			interrupt-parent = <&gsc>;
51			interrupts = <0>;
52		};
53
54		key-2 {
55			label = "key_erased";
56			linux,code = <BTN_2>;
57			interrupt-parent = <&gsc>;
58			interrupts = <1>;
59		};
60
61		key-3 {
62			label = "eeprom_wp";
63			linux,code = <BTN_3>;
64			interrupt-parent = <&gsc>;
65			interrupts = <2>;
66		};
67
68		key-4 {
69			label = "tamper";
70			linux,code = <BTN_4>;
71			interrupt-parent = <&gsc>;
72			interrupts = <5>;
73		};
74
75		key-5 {
76			label = "switch_hold";
77			linux,code = <BTN_5>;
78			interrupt-parent = <&gsc>;
79			interrupts = <7>;
80		};
81	};
82
83	led-controller {
84		compatible = "gpio-leds";
85		pinctrl-names = "default";
86		pinctrl-0 = <&pinctrl_gpio_leds>;
87
88		led-0 {
89			function = LED_FUNCTION_HEARTBEAT;
90			color = <LED_COLOR_ID_GREEN>;
91			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
92			default-state = "on";
93			linux,default-trigger = "heartbeat";
94		};
95
96		led-1 {
97			function = LED_FUNCTION_STATUS;
98			color = <LED_COLOR_ID_RED>;
99			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
100			default-state = "off";
101		};
102	};
103
104	pcie0_refclk: pcie0-refclk {
105		compatible = "fixed-clock";
106		#clock-cells = <0>;
107		clock-frequency = <100000000>;
108	};
109
110	pps {
111		compatible = "pps-gpio";
112		pinctrl-names = "default";
113		pinctrl-0 = <&pinctrl_pps>;
114		gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
115	};
116
117	reg_usb2_vbus: regulator-usb2 {
118		pinctrl-names = "default";
119		pinctrl-0 = <&pinctrl_reg_usb2>;
120		compatible = "regulator-fixed";
121		regulator-name = "usb_usb2_vbus";
122		gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
123		enable-active-high;
124		regulator-min-microvolt = <5000000>;
125		regulator-max-microvolt = <5000000>;
126	};
127
128	reg_can1_stby: regulator-can1-stby {
129		compatible = "regulator-fixed";
130		pinctrl-names = "default";
131		pinctrl-0 = <&pinctrl_reg_can1>;
132		regulator-name = "can1_stby";
133		gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
134		regulator-min-microvolt = <3300000>;
135		regulator-max-microvolt = <3300000>;
136	};
137
138	reg_can2_stby: regulator-can2-stby {
139		compatible = "regulator-fixed";
140		pinctrl-names = "default";
141		pinctrl-0 = <&pinctrl_reg_can2>;
142		regulator-name = "can2_stby";
143		gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
144		regulator-min-microvolt = <3300000>;
145		regulator-max-microvolt = <3300000>;
146	};
147
148	reg_wifi_en: regulator-wifi-en {
149		pinctrl-names = "default";
150		pinctrl-0 = <&pinctrl_reg_wifi>;
151		compatible = "regulator-fixed";
152		regulator-name = "wl";
153		gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
154		startup-delay-us = <70000>;
155		enable-active-high;
156		regulator-min-microvolt = <3300000>;
157		regulator-max-microvolt = <3300000>;
158	};
159};
160
161&A53_0 {
162	cpu-supply = <&reg_arm>;
163};
164
165&A53_1 {
166	cpu-supply = <&reg_arm>;
167};
168
169&A53_2 {
170	cpu-supply = <&reg_arm>;
171};
172
173&A53_3 {
174	cpu-supply = <&reg_arm>;
175};
176
177&ecspi1 {
178	pinctrl-names = "default";
179	pinctrl-0 = <&pinctrl_spi1>;
180	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
181	status = "okay";
182
183	tpm@0 {
184		compatible = "tcg,tpm_tis-spi";
185		#address-cells = <0x1>;
186		#size-cells = <0x1>;
187		reg = <0x0>;
188		spi-max-frequency = <36000000>;
189	};
190};
191
192/* off-board header */
193&ecspi2 {
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_spi2>;
196	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
197	status = "okay";
198};
199
200&eqos {
201	pinctrl-names = "default";
202	pinctrl-0 = <&pinctrl_eqos>;
203	phy-mode = "rgmii-id";
204	phy-handle = <&ethphy0>;
205	status = "okay";
206
207	mdio {
208		compatible = "snps,dwmac-mdio";
209		#address-cells = <1>;
210		#size-cells = <0>;
211
212		ethphy0: ethernet-phy@0 {
213			compatible = "ethernet-phy-ieee802.3-c22";
214			reg = <0x0>;
215		};
216	};
217};
218
219&fec {
220	pinctrl-names = "default";
221	pinctrl-0 = <&pinctrl_fec>;
222	phy-mode = "rgmii-id";
223	local-mac-address = [00 00 00 00 00 00];
224	status = "okay";
225
226	fixed-link {
227		speed = <1000>;
228		full-duplex;
229	};
230};
231
232&flexcan1 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_flexcan1>;
235	xceiver-supply = <&reg_can1_stby>;
236	status = "okay";
237};
238
239&flexcan2 {
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_flexcan2>;
242	xceiver-supply = <&reg_can2_stby>;
243	status = "okay";
244};
245
246&gpio1 {
247	gpio-line-names =
248		"", "", "", "", "", "", "", "",
249		"", "dio0", "", "dio1", "", "", "", "",
250		"", "", "", "", "", "", "", "",
251		"", "", "", "", "", "", "", "";
252};
253
254&gpio2 {
255	gpio-line-names =
256		"", "", "", "", "", "", "m2_pin20", "",
257		"", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
258		"", "", "pcie2_wdis#", "", "", "", "", "",
259		"", "", "", "", "", "", "", "";
260};
261
262&gpio3 {
263	gpio-line-names =
264		"", "", "", "", "", "", "m2_rst", "",
265		"", "", "", "", "", "", "", "",
266		"", "", "", "", "", "", "", "",
267		"", "", "", "", "", "", "", "";
268};
269
270&gpio4 {
271	gpio-line-names =
272		"", "", "m2_off#", "", "", "", "", "",
273		"", "", "", "", "", "", "", "",
274		"", "", "m2_wdis#", "", "", "", "", "",
275		"", "", "", "", "", "", "", "rs485_en";
276};
277
278&gpio5 {
279	gpio-line-names =
280		"rs485_hd", "rs485_term", "", "", "", "", "", "",
281		"", "", "", "", "", "", "", "",
282		"", "", "", "", "", "", "", "",
283		"", "", "", "", "", "", "", "";
284};
285
286&i2c1 {
287	clock-frequency = <100000>;
288	pinctrl-names = "default", "gpio";
289	pinctrl-0 = <&pinctrl_i2c1>;
290	pinctrl-1 = <&pinctrl_i2c1_gpio>;
291	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
292	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
293	status = "okay";
294
295	gsc: gsc@20 {
296		compatible = "gw,gsc";
297		reg = <0x20>;
298		pinctrl-0 = <&pinctrl_gsc>;
299		interrupt-parent = <&gpio4>;
300		interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
301		interrupt-controller;
302		#interrupt-cells = <1>;
303		#address-cells = <1>;
304		#size-cells = <0>;
305
306		adc {
307			compatible = "gw,gsc-adc";
308			#address-cells = <1>;
309			#size-cells = <0>;
310
311			channel@6 {
312				gw,mode = <0>;
313				reg = <0x06>;
314				label = "temp";
315			};
316
317			channel@8 {
318				gw,mode = <3>;
319				reg = <0x08>;
320				label = "vdd_bat";
321			};
322
323			channel@16 {
324				gw,mode = <4>;
325				reg = <0x16>;
326				label = "fan_tach";
327			};
328
329			channel@82 {
330				gw,mode = <2>;
331				reg = <0x82>;
332				label = "vdd_adc1";
333				gw,voltage-divider-ohms = <10000 10000>;
334			};
335
336			channel@84 {
337				gw,mode = <2>;
338				reg = <0x84>;
339				label = "vdd_adc2";
340				gw,voltage-divider-ohms = <10000 10000>;
341			};
342
343			channel@86 {
344				gw,mode = <2>;
345				reg = <0x86>;
346				label = "vdd_vin";
347				gw,voltage-divider-ohms = <22100 1000>;
348			};
349
350			channel@88 {
351				gw,mode = <2>;
352				reg = <0x88>;
353				label = "vdd_3p3";
354				gw,voltage-divider-ohms = <10000 10000>;
355			};
356
357			channel@8c {
358				gw,mode = <2>;
359				reg = <0x8c>;
360				label = "vdd_2p5";
361				gw,voltage-divider-ohms = <10000 10000>;
362			};
363
364			channel@90 {
365				gw,mode = <2>;
366				reg = <0x90>;
367				label = "vdd_soc";
368			};
369
370			channel@92 {
371				gw,mode = <2>;
372				reg = <0x92>;
373				label = "vdd_arm";
374			};
375
376			channel@98 {
377				gw,mode = <2>;
378				reg = <0x98>;
379				label = "vdd_1p8";
380			};
381
382			channel@9a {
383				gw,mode = <2>;
384				reg = <0x9a>;
385				label = "vdd_1p2";
386			};
387
388			channel@9c {
389				gw,mode = <2>;
390				reg = <0x9c>;
391				label = "vdd_dram";
392			};
393
394			channel@a2 {
395				gw,mode = <2>;
396				reg = <0xa2>;
397				label = "vdd_gsc";
398				gw,voltage-divider-ohms = <10000 10000>;
399			};
400		};
401
402		fan-controller@a {
403			compatible = "gw,gsc-fan";
404			reg = <0x0a>;
405		};
406	};
407
408	gpio: gpio@23 {
409		compatible = "nxp,pca9555";
410		reg = <0x23>;
411		gpio-controller;
412		#gpio-cells = <2>;
413		interrupt-parent = <&gsc>;
414		interrupts = <4>;
415	};
416
417	eeprom@50 {
418		compatible = "atmel,24c02";
419		reg = <0x50>;
420		pagesize = <16>;
421	};
422
423	eeprom@51 {
424		compatible = "atmel,24c02";
425		reg = <0x51>;
426		pagesize = <16>;
427	};
428
429	eeprom@52 {
430		compatible = "atmel,24c02";
431		reg = <0x52>;
432		pagesize = <16>;
433	};
434
435	eeprom@53 {
436		compatible = "atmel,24c02";
437		reg = <0x53>;
438		pagesize = <16>;
439	};
440
441	rtc@68 {
442		compatible = "dallas,ds1672";
443		reg = <0x68>;
444	};
445};
446
447&i2c2 {
448	clock-frequency = <400000>;
449	pinctrl-names = "default", "gpio";
450	pinctrl-0 = <&pinctrl_i2c2>;
451	pinctrl-1 = <&pinctrl_i2c2_gpio>;
452	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
454	status = "okay";
455
456	accelerometer@19 {
457		compatible = "st,lis2de12";
458		pinctrl-names = "default";
459		pinctrl-0 = <&pinctrl_accel>;
460		reg = <0x19>;
461		st,drdy-int-pin = <1>;
462		interrupt-parent = <&gpio1>;
463		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
464		interrupt-names = "INT1";
465	};
466
467	switch: switch@5f {
468		compatible = "microchip,ksz9897";
469		reg = <0x5f>;
470		pinctrl-0 = <&pinctrl_ksz>;
471		interrupt-parent = <&gpio4>;
472		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
473
474		ports {
475			#address-cells = <1>;
476			#size-cells = <0>;
477
478			lan1: port@0 {
479				reg = <0>;
480				label = "lan1";
481				phy-mode = "internal";
482				local-mac-address = [00 00 00 00 00 00];
483			};
484
485			lan2: port@1 {
486				reg = <1>;
487				label = "lan2";
488				phy-mode = "internal";
489				local-mac-address = [00 00 00 00 00 00];
490			};
491
492			lan3: port@2 {
493				reg = <2>;
494				label = "lan3";
495				phy-mode = "internal";
496				local-mac-address = [00 00 00 00 00 00];
497			};
498
499			lan4: port@3 {
500				reg = <3>;
501				label = "lan4";
502				phy-mode = "internal";
503				local-mac-address = [00 00 00 00 00 00];
504			};
505
506			lan5: port@4 {
507				reg = <4>;
508				label = "lan5";
509				phy-mode = "internal";
510				local-mac-address = [00 00 00 00 00 00];
511			};
512
513			port@5 {
514				reg = <5>;
515				label = "cpu";
516				ethernet = <&fec>;
517				phy-mode = "rgmii-id";
518
519				fixed-link {
520					speed = <1000>;
521					full-duplex;
522				};
523			};
524		};
525	};
526};
527
528&i2c3 {
529	clock-frequency = <400000>;
530	pinctrl-names = "default", "gpio";
531	pinctrl-0 = <&pinctrl_i2c3>;
532	pinctrl-1 = <&pinctrl_i2c3_gpio>;
533	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
534	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
535	status = "okay";
536
537	pmic@25 {
538		compatible = "nxp,pca9450c";
539		reg = <0x25>;
540		pinctrl-names = "default";
541		pinctrl-0 = <&pinctrl_pmic>;
542		interrupt-parent = <&gpio3>;
543		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
544
545		regulators {
546			BUCK1 {
547				regulator-name = "BUCK1";
548				regulator-min-microvolt = <720000>;
549				regulator-max-microvolt = <1000000>;
550				regulator-boot-on;
551				regulator-always-on;
552				regulator-ramp-delay = <3125>;
553			};
554
555			reg_arm: BUCK2 {
556				regulator-name = "BUCK2";
557				regulator-min-microvolt = <720000>;
558				regulator-max-microvolt = <1025000>;
559				regulator-boot-on;
560				regulator-always-on;
561				regulator-ramp-delay = <3125>;
562				nxp,dvs-run-voltage = <950000>;
563				nxp,dvs-standby-voltage = <850000>;
564			};
565
566			BUCK4 {
567				regulator-name = "BUCK4";
568				regulator-min-microvolt = <3000000>;
569				regulator-max-microvolt = <3600000>;
570				regulator-boot-on;
571				regulator-always-on;
572			};
573
574			BUCK5 {
575				regulator-name = "BUCK5";
576				regulator-min-microvolt = <1650000>;
577				regulator-max-microvolt = <1950000>;
578				regulator-boot-on;
579				regulator-always-on;
580			};
581
582			BUCK6 {
583				regulator-name = "BUCK6";
584				regulator-min-microvolt = <1045000>;
585				regulator-max-microvolt = <1155000>;
586				regulator-boot-on;
587				regulator-always-on;
588			};
589
590			LDO1 {
591				regulator-name = "LDO1";
592				regulator-min-microvolt = <1650000>;
593				regulator-max-microvolt = <1950000>;
594				regulator-boot-on;
595				regulator-always-on;
596			};
597
598			LDO3 {
599				regulator-name = "LDO3";
600				regulator-min-microvolt = <1710000>;
601				regulator-max-microvolt = <1890000>;
602				regulator-boot-on;
603				regulator-always-on;
604			};
605
606			LDO5 {
607				regulator-name = "LDO5";
608				regulator-min-microvolt = <1800000>;
609				regulator-max-microvolt = <3300000>;
610				regulator-boot-on;
611				regulator-always-on;
612			};
613		};
614	};
615};
616
617/* off-board header */
618&i2c4 {
619	clock-frequency = <400000>;
620	pinctrl-names = "default", "gpio";
621	pinctrl-0 = <&pinctrl_i2c4>;
622	pinctrl-1 = <&pinctrl_i2c4_gpio>;
623	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
624	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
625	status = "okay";
626};
627
628&pcie_phy {
629	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
630	fsl,clkreq-unsupported;
631	clocks = <&pcie0_refclk>;
632	clock-names = "ref";
633	status = "okay";
634};
635
636&pcie {
637	pinctrl-names = "default";
638	pinctrl-0 = <&pinctrl_pcie0>;
639	reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
640	status = "okay";
641};
642
643/* GPS / off-board header */
644&uart1 {
645	pinctrl-names = "default";
646	pinctrl-0 = <&pinctrl_uart1>;
647	status = "okay";
648};
649
650/* RS232 console */
651&uart2 {
652	pinctrl-names = "default";
653	pinctrl-0 = <&pinctrl_uart2>;
654	status = "okay";
655};
656
657/* bluetooth HCI */
658&uart3 {
659	pinctrl-names = "default";
660	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
661	cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
662	rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
663	status = "okay";
664
665	bluetooth {
666		compatible = "brcm,bcm4330-bt";
667		shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
668	};
669};
670
671&uart4 {
672	pinctrl-names = "default";
673	pinctrl-0 = <&pinctrl_uart4>;
674	status = "okay";
675};
676
677/* USB1 - Type C front panel */
678&usb3_0 {
679	pinctrl-names = "default";
680	pinctrl-0 = <&pinctrl_usb1>;
681	fsl,over-current-active-low;
682	status = "okay";
683};
684
685&usb3_phy0 {
686	status = "okay";
687};
688
689&usb_dwc3_0 {
690	/* dual role is implemented but not a full featured OTG */
691	adp-disable;
692	hnp-disable;
693	srp-disable;
694	dr_mode = "otg";
695	usb-role-switch;
696	role-switch-default-mode = "peripheral";
697	status = "okay";
698
699	connector {
700		pinctrl-names = "default";
701		pinctrl-0 = <&pinctrl_usbcon1>;
702		compatible = "gpio-usb-b-connector", "usb-b-connector";
703		type = "micro";
704		label = "Type-C";
705		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
706	};
707};
708
709/* USB2 - USB3.0 Hub */
710&usb3_phy1 {
711	vbus-supply = <&reg_usb2_vbus>;
712	status = "okay";
713};
714
715&usb3_1 {
716	fsl,permanently-attached;
717	fsl,disable-port-power-control;
718	status = "okay";
719};
720
721&usb_dwc3_1 {
722	dr_mode = "host";
723	status = "okay";
724};
725
726/* SDIO WiFi */
727&usdhc1 {
728	pinctrl-names = "default", "state_100mhz", "state_200mhz";
729	pinctrl-0 = <&pinctrl_usdhc1>;
730	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
731	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
732	bus-width = <4>;
733	non-removable;
734	vmmc-supply = <&reg_wifi_en>;
735	#address-cells = <1>;
736	#size-cells = <0>;
737	status = "okay";
738
739	wifi@0 {
740		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
741		reg = <0>;
742	};
743};
744
745/* eMMC */
746&usdhc3 {
747	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
748	assigned-clock-rates = <400000000>;
749	pinctrl-names = "default", "state_100mhz", "state_200mhz";
750	pinctrl-0 = <&pinctrl_usdhc3>;
751	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
752	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
753	bus-width = <8>;
754	non-removable;
755	status = "okay";
756};
757
758&wdog1 {
759	pinctrl-names = "default";
760	pinctrl-0 = <&pinctrl_wdog>;
761	fsl,ext-reset-output;
762	status = "okay";
763};
764
765&iomuxc {
766	pinctrl-names = "default";
767	pinctrl-0 = <&pinctrl_hog>;
768
769	pinctrl_hog: hoggrp {
770		fsl,pins = <
771			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */
772			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */
773			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x40000040 /* M2SKT_OFF# */
774			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS# */
775			MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06	0x40000040 /* M2SKT_PIN20 */
776			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11	0x40000040 /* M2SKT_PIN22 */
777			MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13	0x40000150 /* PCIE1_WDIS# */
778			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */
779			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */
780			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */
781			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */
782			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */
783			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */
784		>;
785	};
786
787	pinctrl_accel: accelgrp {
788		fsl,pins = <
789			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150
790		>;
791	};
792
793	pinctrl_eqos: eqosgrp {
794		fsl,pins = <
795			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
796			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
797			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
798			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
799			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
800			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
801			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
802			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
803			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
804			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
805			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
806			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
807			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
808			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
809			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */
810			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */
811		>;
812	};
813
814	pinctrl_fec: fecgrp {
815		fsl,pins = <
816			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90
817			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90
818			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90
819			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90
820			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90
821			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90
822			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16
823			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16
824			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16
825			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16
826			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16
827			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16
828			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140
829			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140
830		>;
831	};
832
833	pinctrl_flexcan1: flexcan1grp {
834		fsl,pins = <
835			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX		0x154
836			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX		0x154
837		>;
838	};
839
840	pinctrl_flexcan2: flexcan2grp {
841		fsl,pins = <
842			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
843			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
844		>;
845	};
846
847	pinctrl_gsc: gscgrp {
848		fsl,pins = <
849			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150
850		>;
851	};
852
853	pinctrl_i2c1: i2c1grp {
854		fsl,pins = <
855			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2
856			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2
857		>;
858	};
859
860	pinctrl_i2c1_gpio: i2c1gpiogrp {
861		fsl,pins = <
862			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14	0x400001c2
863			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15	0x400001c2
864		>;
865	};
866
867	pinctrl_i2c2: i2c2grp {
868		fsl,pins = <
869			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
870			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
871		>;
872	};
873
874	pinctrl_i2c2_gpio: i2c2gpiogrp {
875		fsl,pins = <
876			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x400001c3
877			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x400001c3
878		>;
879	};
880
881	pinctrl_i2c3: i2c3grp {
882		fsl,pins = <
883			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
884			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
885		>;
886	};
887
888	pinctrl_i2c3_gpio: i2c3gpiogrp {
889		fsl,pins = <
890			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18	0x400001c3
891			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19	0x400001c3
892		>;
893	};
894
895	pinctrl_i2c4: i2c4grp {
896		fsl,pins = <
897			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2
898			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2
899		>;
900	};
901
902	pinctrl_i2c4_gpio: i2c4gpiogrp {
903		fsl,pins = <
904			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20	0x400001c3
905			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21	0x400001c3
906		>;
907	};
908
909	pinctrl_ksz: kszgrp {
910		fsl,pins = <
911			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */
912			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */
913		>;
914	};
915
916	pinctrl_gpio_leds: ledgrp {
917		fsl,pins = <
918			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10
919			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10
920		>;
921	};
922
923	pinctrl_pcie0: pciegrp {
924		fsl,pins = <
925			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x106
926		>;
927	};
928
929	pinctrl_pmic: pmicgrp {
930		fsl,pins = <
931			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140
932		>;
933	};
934
935	pinctrl_pps: ppsgrp {
936		fsl,pins = <
937			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140
938		>;
939	};
940
941	pinctrl_reg_can1: regcan1grp {
942		fsl,pins = <
943			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19	0x154
944		>;
945	};
946
947	pinctrl_reg_can2: regcan2grp {
948		fsl,pins = <
949			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05	0x154
950		>;
951	};
952
953	pinctrl_reg_usb2: regusb2grp {
954		fsl,pins = <
955			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140
956		>;
957	};
958
959	pinctrl_reg_wifi: regwifigrp {
960		fsl,pins = <
961			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110
962		>;
963	};
964
965	pinctrl_spi1: spi1grp {
966		fsl,pins = <
967			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK	0x82
968			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI	0x82
969			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO	0x82
970			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x140
971		>;
972	};
973
974	pinctrl_spi2: spi2grp {
975		fsl,pins = <
976			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x82
977			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x82
978			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x82
979			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
980		>;
981	};
982
983	pinctrl_uart1: uart1grp {
984		fsl,pins = <
985			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
986			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
987		>;
988	};
989
990	pinctrl_uart2: uart2grp {
991		fsl,pins = <
992			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
993			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
994		>;
995	};
996
997	pinctrl_uart3: uart3grp {
998		fsl,pins = <
999			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
1000			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
1001			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140
1002			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22	0x140
1003		>;
1004	};
1005
1006	pinctrl_uart3_gpio: uart3gpiogrp {
1007		fsl,pins = <
1008			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110
1009		>;
1010	};
1011
1012	pinctrl_uart4: uart4grp {
1013		fsl,pins = <
1014			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140
1015			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140
1016		>;
1017	};
1018
1019	pinctrl_usb1: usb1grp {
1020		fsl,pins = <
1021			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140
1022		>;
1023	};
1024
1025	pinctrl_usbcon1: usb1congrp {
1026		fsl,pins = <
1027			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x140
1028		>;
1029	};
1030
1031	pinctrl_usdhc1: usdhc1grp {
1032		fsl,pins = <
1033			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
1034			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
1035			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
1036			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
1037			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
1038			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
1039		>;
1040	};
1041
1042	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1043		fsl,pins = <
1044			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x194
1045			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d4
1046			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d4
1047			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d4
1048			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d4
1049			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d4
1050		>;
1051	};
1052
1053	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1054		fsl,pins = <
1055			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x196
1056			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d6
1057			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d6
1058			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d6
1059			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d6
1060			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d6
1061		>;
1062	};
1063
1064	pinctrl_usdhc3: usdhc3grp {
1065		fsl,pins = <
1066			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x190
1067			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d0
1068			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d0
1069			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d0
1070			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d0
1071			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d0
1072			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d0
1073			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d0
1074			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d0
1075			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d0
1076			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x190
1077		>;
1078	};
1079
1080	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1081		fsl,pins = <
1082			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x194
1083			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d4
1084			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4
1085			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4
1086			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4
1087			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4
1088			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4
1089			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4
1090			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4
1091			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d4
1092			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x194
1093		>;
1094	};
1095
1096	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1097		fsl,pins = <
1098			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK	0x196
1099			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD	0x1d6
1100			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d6
1101			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d6
1102			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d6
1103			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d6
1104			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d6
1105			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d6
1106			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d6
1107			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7	0x1d6
1108			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x196
1109		>;
1110	};
1111
1112	pinctrl_wdog: wdoggrp {
1113		fsl,pins = <
1114			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
1115		>;
1116	};
1117};
1118