1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 15 16 led-0 { 17 function = LED_FUNCTION_STATUS; 18 color = <LED_COLOR_ID_GREEN>; 19 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 20 default-state = "on"; 21 linux,default-trigger = "heartbeat"; 22 }; 23 24 led-1 { 25 function = LED_FUNCTION_STATUS; 26 color = <LED_COLOR_ID_RED>; 27 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 28 default-state = "off"; 29 }; 30 }; 31 32 pcie0_refclk: clock-pcie0 { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <100000000>; 36 }; 37 38 pps { 39 compatible = "pps-gpio"; 40 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_pps>; 42 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 43 status = "okay"; 44 }; 45 46 reg_usb1_vbus: regulator-usb1 { 47 compatible = "regulator-fixed"; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_reg_usb1_en>; 50 regulator-name = "usb1_vbus"; 51 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 }; 56 57 reg_usb2_vbus: regulator-usb2 { 58 compatible = "regulator-fixed"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_reg_usb2_en>; 61 regulator-name = "usb2_vbus"; 62 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 regulator-min-microvolt = <5000000>; 65 regulator-max-microvolt = <5000000>; 66 }; 67 68 reg_wifi_en: regulator-wifi-en { 69 compatible = "regulator-fixed"; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pinctrl_reg_wl>; 72 regulator-name = "wl"; 73 gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; 74 startup-delay-us = <100>; 75 enable-active-high; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 }; 79 80 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 81 compatible = "regulator-fixed"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 84 regulator-name = "VDD_3V3_SD"; 85 enable-active-high; 86 gpio = <&gpio2 19 0>; /* SD2_RESET */ 87 off-on-delay-us = <12000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-min-microvolt = <3300000>; 90 startup-delay-us = <100>; 91 }; 92}; 93 94/* off-board header */ 95&ecspi2 { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_spi2>; 98 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 99 <&gpio1 10 GPIO_ACTIVE_LOW>; 100 status = "okay"; 101 102 tpm@1 { 103 compatible = "tcg,tpm_tis-spi"; 104 reg = <0x1>; 105 spi-max-frequency = <36000000>; 106 }; 107}; 108 109&gpio4 { 110 gpio-line-names = 111 "", "", "", "", 112 "", "", "", "", 113 "dio1", "", "", "dio0", 114 "", "", "pci_usb_sel", "", 115 "", "", "", "", 116 "", "", "rs485_en", "rs485_term", 117 "", "", "", "rs485_half", 118 "pci_wdis#", "", "", ""; 119}; 120 121&i2c2 { 122 clock-frequency = <400000>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_i2c2>; 125 status = "okay"; 126 127 accelerometer@19 { 128 compatible = "st,lis2de12"; 129 reg = <0x19>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_accel>; 132 st,drdy-int-pin = <1>; 133 interrupt-parent = <&gpio4>; 134 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 135 }; 136}; 137 138&pcie_phy { 139 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 140 fsl,clkreq-unsupported; 141 clocks = <&pcie0_refclk>; 142 clock-names = "ref"; 143 status = "okay"; 144}; 145 146&pcie { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_pcie0>; 149 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 150 status = "okay"; 151}; 152 153/* GPS */ 154&uart1 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_uart1>; 157 status = "okay"; 158}; 159 160/* bluetooth HCI */ 161&uart3 { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; 164 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 165 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 166 status = "okay"; 167 168 bluetooth { 169 compatible = "brcm,bcm4330-bt"; 170 shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 171 }; 172}; 173 174/* RS232 */ 175&uart4 { 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_uart4>; 178 status = "okay"; 179}; 180 181/* USB1 - OTG */ 182&usb3_0 { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_usb1>; 185 fsl,over-current-active-low; 186 status = "okay"; 187}; 188 189&usb3_phy0 { 190 vbus-supply = <®_usb1_vbus>; 191 status = "okay"; 192}; 193 194&usb_dwc3_0 { 195 /* dual role is implemented but not a full featured OTG */ 196 adp-disable; 197 hnp-disable; 198 srp-disable; 199 dr_mode = "otg"; 200 usb-role-switch; 201 role-switch-default-mode = "peripheral"; 202 status = "okay"; 203 204 connector { 205 compatible = "gpio-usb-b-connector", "usb-b-connector"; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_usbcon1>; 208 type = "micro"; 209 label = "otg"; 210 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 211 }; 212}; 213 214/* USB2 - USB3.0 Hub */ 215&usb3_1 { 216 fsl,permanently-attached; 217 fsl,disable-port-power-control; 218 status = "okay"; 219}; 220 221&usb3_phy1 { 222 vbus-supply = <®_usb2_vbus>; 223 status = "okay"; 224}; 225 226&usb_dwc3_1 { 227 dr_mode = "host"; 228 status = "okay"; 229}; 230 231/* SDIO WiFi */ 232&usdhc1 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_usdhc1>; 235 bus-width = <4>; 236 non-removable; 237 vmmc-supply = <®_wifi_en>; 238 status = "okay"; 239}; 240 241/* microSD */ 242&usdhc2 { 243 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 244 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 245 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 246 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 247 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 248 bus-width = <4>; 249 vmmc-supply = <®_usdhc2_vmmc>; 250 status = "okay"; 251}; 252 253&iomuxc { 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_hog>; 256 257 pinctrl_hog: hoggrp { 258 fsl,pins = < 259 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 260 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 261 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ 262 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 263 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 264 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 265 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ 266 >; 267 }; 268 269 pinctrl_accel: accelgrp { 270 fsl,pins = < 271 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ 272 >; 273 }; 274 275 pinctrl_bten: btengrp { 276 fsl,pins = < 277 MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 278 >; 279 }; 280 281 pinctrl_gpio_leds: gpioledgrp { 282 fsl,pins = < 283 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 284 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 285 >; 286 }; 287 288 pinctrl_pcie0: pcie0grp { 289 fsl,pins = < 290 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 291 >; 292 }; 293 294 pinctrl_pps: ppsgrp { 295 fsl,pins = < 296 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 297 >; 298 }; 299 300 pinctrl_reg_wl: regwlgrp { 301 fsl,pins = < 302 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 303 >; 304 }; 305 306 pinctrl_reg_usb1_en: regusb1grp { 307 fsl,pins = < 308 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ 309 >; 310 }; 311 312 pinctrl_usb1: usb1grp { 313 fsl,pins = < 314 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ 315 >; 316 }; 317 318 pinctrl_usbcon1: usbcon1grp { 319 fsl,pins = < 320 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ 321 >; 322 }; 323 324 pinctrl_reg_usb2_en: regusb2grp { 325 fsl,pins = < 326 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 327 >; 328 }; 329 330 pinctrl_spi2: spi2grp { 331 fsl,pins = < 332 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 333 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 334 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 335 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 336 >; 337 }; 338 339 pinctrl_uart1: uart1grp { 340 fsl,pins = < 341 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 342 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 343 >; 344 }; 345 346 pinctrl_uart3: uart3grp { 347 fsl,pins = < 348 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 349 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 350 MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 351 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 352 >; 353 }; 354 355 pinctrl_uart4: uart4grp { 356 fsl,pins = < 357 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 358 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 359 >; 360 }; 361 362 pinctrl_usdhc1: usdhc1grp { 363 fsl,pins = < 364 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 365 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 366 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 367 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 368 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 369 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 370 >; 371 }; 372 373 pinctrl_usdhc2: usdhc2grp { 374 fsl,pins = < 375 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 376 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 377 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 378 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 379 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 380 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 381 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 382 >; 383 }; 384 385 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 386 fsl,pins = < 387 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 388 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 389 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 390 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 391 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 392 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 393 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 394 >; 395 }; 396 397 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 398 fsl,pins = < 399 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 400 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 401 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 402 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 403 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 404 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 405 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 406 >; 407 }; 408 409 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 410 fsl,pins = < 411 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 412 >; 413 }; 414 415 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 416 fsl,pins = < 417 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 418 >; 419 }; 420}; 421