xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi (revision 40ccd6aa3e2e05be93394e3cd560c718dedfcc77)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2023 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/leds/common.h>
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10/ {
11	aliases {
12		ethernet1 = &eth1;
13	};
14
15	connector {
16		compatible = "gpio-usb-b-connector", "usb-b-connector";
17		pinctrl-names = "default";
18		pinctrl-0 = <&pinctrl_usbcon1>;
19		type = "micro";
20		label = "otg";
21		vbus-supply = <&reg_usb1_vbus>;
22		id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
23
24		port {
25			usb_dr_connector: endpoint {
26				remote-endpoint = <&usb3_dwc>;
27			};
28		};
29	};
30
31	led-controller {
32		compatible = "gpio-leds";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_gpio_leds>;
35
36		led-0 {
37			function = LED_FUNCTION_STATUS;
38			color = <LED_COLOR_ID_GREEN>;
39			gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
40			default-state = "on";
41			linux,default-trigger = "heartbeat";
42		};
43
44		led-1 {
45			function = LED_FUNCTION_STATUS;
46			color = <LED_COLOR_ID_RED>;
47			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
48			default-state = "off";
49		};
50	};
51
52	pcie0_refclk: clock-pcie0 {
53		compatible = "fixed-clock";
54		#clock-cells = <0>;
55		clock-frequency = <100000000>;
56	};
57
58	pps {
59		compatible = "pps-gpio";
60		pinctrl-names = "default";
61		pinctrl-0 = <&pinctrl_pps>;
62		gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
63		status = "okay";
64	};
65
66	reg_usb1_vbus: regulator-usb1 {
67		compatible = "regulator-fixed";
68		pinctrl-names = "default";
69		pinctrl-0 = <&pinctrl_reg_usb1_en>;
70		regulator-name = "usb1_vbus";
71		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
72		enable-active-high;
73		regulator-min-microvolt = <5000000>;
74		regulator-max-microvolt = <5000000>;
75	};
76
77	reg_usb2_vbus: regulator-usb2 {
78		compatible = "regulator-fixed";
79		pinctrl-names = "default";
80		pinctrl-0 = <&pinctrl_reg_usb2_en>;
81		regulator-name = "usb2_vbus";
82		gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
83		enable-active-high;
84		regulator-min-microvolt = <5000000>;
85		regulator-max-microvolt = <5000000>;
86	};
87
88	reg_wifi_en: regulator-wifi-en {
89		compatible = "regulator-fixed";
90		pinctrl-names = "default";
91		pinctrl-0 = <&pinctrl_reg_wl>;
92		regulator-name = "wl";
93		gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
94		startup-delay-us = <100>;
95		enable-active-high;
96		regulator-min-microvolt = <3300000>;
97		regulator-max-microvolt = <3300000>;
98	};
99
100	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
101		compatible = "regulator-fixed";
102		pinctrl-names = "default";
103		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
104		regulator-name = "VDD_3V3_SD";
105		enable-active-high;
106		gpio = <&gpio2 19 0>; /* SD2_RESET */
107		off-on-delay-us = <12000>;
108		regulator-max-microvolt = <3300000>;
109		regulator-min-microvolt = <3300000>;
110		startup-delay-us = <100>;
111	};
112};
113
114/* off-board header */
115&ecspi2 {
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_spi2>;
118	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
119		   <&gpio1 10 GPIO_ACTIVE_LOW>;
120	status = "okay";
121
122	tpm@1 {
123		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
124		reg = <0x1>;
125		spi-max-frequency = <36000000>;
126	};
127};
128
129&gpio4 {
130	gpio-line-names =
131		"", "", "", "",
132		"", "", "", "",
133		"dio1", "", "", "dio0",
134		"", "", "pci_usb_sel", "",
135		"", "", "", "",
136		"", "", "rs485_en", "rs485_term",
137		"", "", "", "rs485_half",
138		"pci_wdis#", "", "", "";
139};
140
141&i2c2 {
142	clock-frequency = <400000>;
143	pinctrl-names = "default";
144	pinctrl-0 = <&pinctrl_i2c2>;
145	status = "okay";
146
147	accelerometer@19 {
148		compatible = "st,lis2de12";
149		reg = <0x19>;
150		pinctrl-names = "default";
151		pinctrl-0 = <&pinctrl_accel>;
152		st,drdy-int-pin = <1>;
153		interrupt-parent = <&gpio4>;
154		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
155	};
156};
157
158&pcie_phy {
159	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
160	fsl,clkreq-unsupported;
161	clocks = <&pcie0_refclk>;
162	clock-names = "ref";
163	status = "okay";
164};
165
166&pcie {
167	pinctrl-names = "default";
168	pinctrl-0 = <&pinctrl_pcie0>;
169	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
170	status = "okay";
171
172	pcie@0,0 {
173		reg = <0x0000 0 0 0 0>;
174		device_type = "pci";
175		#address-cells = <3>;
176		#size-cells = <2>;
177		ranges;
178
179		pcie@0,0 {
180			reg = <0x0000 0 0 0 0>;
181			device_type = "pci";
182			#address-cells = <3>;
183			#size-cells = <2>;
184			ranges;
185
186			pcie@4,0 {
187				reg = <0x2000 0 0 0 0>;
188				device_type = "pci";
189				#address-cells = <3>;
190				#size-cells = <2>;
191				ranges;
192
193				eth1: ethernet@0,0 {
194					reg = <0x0000 0 0 0 0>;
195					#address-cells = <3>;
196					#size-cells = <2>;
197					ranges;
198					local-mac-address = [00 00 00 00 00 00];
199				};
200			};
201		};
202	};
203};
204
205/* GPS */
206&uart1 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&pinctrl_uart1>;
209	status = "okay";
210};
211
212/* bluetooth HCI */
213&uart3 {
214	pinctrl-names = "default";
215	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
216	cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
217	rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
218	status = "okay";
219
220	bluetooth {
221		compatible = "brcm,bcm4330-bt";
222		shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
223	};
224};
225
226/* RS232 */
227&uart4 {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_uart4>;
230	status = "okay";
231};
232
233/* USB1 - OTG */
234&usb3_0 {
235	pinctrl-names = "default";
236	pinctrl-0 = <&pinctrl_usb1>;
237	fsl,over-current-active-low;
238	status = "okay";
239};
240
241&usb3_phy0 {
242	status = "okay";
243};
244
245&usb_dwc3_0 {
246	/* dual role is implemented but not a full featured OTG */
247	adp-disable;
248	hnp-disable;
249	srp-disable;
250	dr_mode = "otg";
251	usb-role-switch;
252	role-switch-default-mode = "peripheral";
253	status = "okay";
254
255	port {
256		usb3_dwc: endpoint {
257			remote-endpoint = <&usb_dr_connector>;
258		};
259	};
260};
261
262/* USB2 - USB3.0 Hub */
263&usb3_1 {
264	fsl,permanently-attached;
265	fsl,disable-port-power-control;
266	status = "okay";
267};
268
269&usb3_phy1 {
270	vbus-supply = <&reg_usb2_vbus>;
271	status = "okay";
272};
273
274&usb_dwc3_1 {
275	dr_mode = "host";
276	status = "okay";
277};
278
279/* SDIO WiFi */
280&usdhc1 {
281	pinctrl-names = "default";
282	pinctrl-0 = <&pinctrl_usdhc1>;
283	bus-width = <4>;
284	non-removable;
285	vmmc-supply = <&reg_wifi_en>;
286	status = "okay";
287};
288
289/* microSD */
290&usdhc2 {
291	pinctrl-names = "default", "state_100mhz", "state_200mhz";
292	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
293	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
294	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
295	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
296	bus-width = <4>;
297	vmmc-supply = <&reg_usdhc2_vmmc>;
298	status = "okay";
299};
300
301&iomuxc {
302	pinctrl-names = "default";
303	pinctrl-0 = <&pinctrl_hog>;
304
305	pinctrl_hog: hoggrp {
306		fsl,pins = <
307			MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08	0x40000146 /* DIO1 */
308			MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11	0x40000146 /* DIO0 */
309			MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14	0x40000106 /* PCIE_USBSEL */
310			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27	0x40000106 /* RS485_HALF */
311			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x40000106 /* RS485_EN */
312			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23	0x40000106 /* RS485_TERM */
313			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x40000106 /* PCIE_WDIS# */
314		>;
315	};
316
317	pinctrl_accel: accelgrp {
318		fsl,pins = <
319			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x150	/* IRQ */
320		>;
321	};
322
323	pinctrl_bten: btengrp {
324		fsl,pins = <
325			MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16	0x146
326		>;
327	};
328
329	pinctrl_gpio_leds: gpioledgrp {
330		fsl,pins = <
331			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x6	/* LEDG */
332			MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05	0x6	/* LEDR */
333		>;
334	};
335
336	pinctrl_pcie0: pcie0grp {
337		fsl,pins = <
338			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x106
339		>;
340	};
341
342	pinctrl_pps: ppsgrp {
343		fsl,pins = <
344			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x146
345		>;
346	};
347
348	pinctrl_reg_wl: regwlgrp {
349		fsl,pins = <
350			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x146
351		>;
352	};
353
354	pinctrl_reg_usb1_en: regusb1grp {
355		fsl,pins = <
356			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x146 /* USB1_EN */
357		>;
358	};
359
360	pinctrl_usb1: usb1grp {
361		fsl,pins = <
362			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC	0x140 /* USB1_FLT# */
363		>;
364	};
365
366	pinctrl_usbcon1: usbcon1grp {
367		fsl,pins = <
368			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x140 /* USB1_ID */
369		>;
370	};
371
372	pinctrl_reg_usb2_en: regusb2grp {
373		fsl,pins = <
374			MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12	0x146 /* USBHUB_RST# */
375		>;
376	};
377
378	pinctrl_spi2: spi2grp {
379		fsl,pins = <
380			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK	0x140
381			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI	0x140
382			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO	0x140
383			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13	0x140
384		>;
385	};
386
387	pinctrl_uart1: uart1grp {
388		fsl,pins = <
389			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
390			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
391		>;
392	};
393
394	pinctrl_uart3: uart3grp {
395		fsl,pins = <
396			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
397			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
398			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08	0x140
399			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09	0x140
400		>;
401	};
402
403	pinctrl_uart4: uart4grp {
404		fsl,pins = <
405			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX	0x140
406			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX	0x140
407		>;
408	};
409
410	pinctrl_usdhc1: usdhc1grp {
411		fsl,pins = <
412			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK	0x190
413			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD	0x1d0
414			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0	0x1d0
415			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1	0x1d0
416			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2	0x1d0
417			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3	0x1d0
418		>;
419	};
420
421	pinctrl_usdhc2: usdhc2grp {
422		fsl,pins = <
423			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
424			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
425			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
426			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
427			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
428			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
429			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
430		>;
431	};
432
433	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
434		fsl,pins = <
435			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
436			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
437			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
438			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
439			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
440			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
441			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
442		>;
443	};
444
445	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
446		fsl,pins = <
447			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
448			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
449			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
450			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
451			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
452			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
453			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc1
454		>;
455	};
456
457	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
458		fsl,pins = <
459			MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B	0x1d0
460		>;
461	};
462
463	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
464		fsl,pins = <
465			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4
466		>;
467	};
468};
469