1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7#include "imx8mp.dtsi" 8 9/ { 10 model = "TQ-Systems i.MX8MPlus TQMa8MPxL"; 11 compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 12 13 memory@40000000 { 14 device_type = "memory"; 15 reg = <0x0 0x40000000 0 0x80000000>; 16 }; 17 18 /* identical to buck4_reg, but should never change */ 19 reg_vcc3v3: regulator-vcc3v3 { 20 compatible = "regulator-fixed"; 21 regulator-name = "VCC3V3"; 22 regulator-min-microvolt = <3300000>; 23 regulator-max-microvolt = <3300000>; 24 regulator-always-on; 25 }; 26 27 /* e-MMC IO, needed for HS modes */ 28 reg_vcc1v8: regulator-vcc1v8 { 29 compatible = "regulator-fixed"; 30 regulator-name = "VCC1V8"; 31 regulator-min-microvolt = <1800000>; 32 regulator-max-microvolt = <1800000>; 33 regulator-always-on; 34 }; 35}; 36 37&A53_0 { 38 cpu-supply = <&buck2_reg>; 39}; 40 41&flexspi { 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_flexspi0>; 44 status = "okay"; 45 46 flash0: flash@0 { 47 reg = <0>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "jedec,spi-nor"; 51 spi-max-frequency = <80000000>; 52 spi-tx-bus-width = <1>; 53 spi-rx-bus-width = <4>; 54 }; 55}; 56 57&i2c1 { 58 clock-frequency = <384000>; 59 pinctrl-names = "default", "gpio"; 60 pinctrl-0 = <&pinctrl_i2c1>; 61 pinctrl-1 = <&pinctrl_i2c1_gpio>; 62 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 63 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 64 status = "okay"; 65 66 se97: temperature-sensor@1b { 67 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 68 reg = <0x1b>; 69 }; 70 71 pmic: pmic@25 { 72 reg = <0x25>; 73 compatible = "nxp,pca9450c"; 74 75 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 76 pinctrl-0 = <&pinctrl_pmic>; 77 pinctrl-names = "default"; 78 interrupt-parent = <&gpio1>; 79 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 80 81 regulators { 82 /* V_0V85_SOC: 0.85 .. 0.95 */ 83 buck1_reg: BUCK1 { 84 regulator-name = "BUCK1"; 85 regulator-min-microvolt = <850000>; 86 regulator-max-microvolt = <950000>; 87 regulator-boot-on; 88 regulator-always-on; 89 regulator-ramp-delay = <3125>; 90 }; 91 92 /* VDD_ARM */ 93 buck2_reg: BUCK2 { 94 regulator-name = "BUCK2"; 95 regulator-min-microvolt = <850000>; 96 regulator-max-microvolt = <1000000>; 97 regulator-boot-on; 98 regulator-always-on; 99 nxp,dvs-run-voltage = <950000>; 100 nxp,dvs-standby-voltage = <850000>; 101 regulator-ramp-delay = <3125>; 102 }; 103 104 /* VCC3V3 -> VMMC, ... must not be changed */ 105 buck4_reg: BUCK4 { 106 regulator-name = "BUCK4"; 107 regulator-min-microvolt = <3300000>; 108 regulator-max-microvolt = <3300000>; 109 regulator-boot-on; 110 regulator-always-on; 111 }; 112 113 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 114 buck5_reg: BUCK5 { 115 regulator-name = "BUCK5"; 116 regulator-min-microvolt = <1800000>; 117 regulator-max-microvolt = <1800000>; 118 regulator-boot-on; 119 regulator-always-on; 120 }; 121 122 /* V_1V1 -> RAM, ... must not be changed */ 123 buck6_reg: BUCK6 { 124 regulator-name = "BUCK6"; 125 regulator-min-microvolt = <1100000>; 126 regulator-max-microvolt = <1100000>; 127 regulator-boot-on; 128 regulator-always-on; 129 }; 130 131 /* V_1V8_SNVS */ 132 ldo1_reg: LDO1 { 133 regulator-name = "LDO1"; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <1800000>; 136 regulator-boot-on; 137 regulator-always-on; 138 }; 139 140 /* V_1V8_ANA */ 141 ldo3_reg: LDO3 { 142 regulator-name = "LDO3"; 143 regulator-min-microvolt = <1800000>; 144 regulator-max-microvolt = <1800000>; 145 regulator-boot-on; 146 regulator-always-on; 147 }; 148 149 /* unused */ 150 ldo4_reg: LDO4 { 151 regulator-name = "LDO4"; 152 regulator-min-microvolt = <800000>; 153 regulator-max-microvolt = <3300000>; 154 }; 155 156 /* VCC SD IO - switched using SD2 VSELECT */ 157 ldo5_reg: LDO5 { 158 regulator-name = "LDO5"; 159 regulator-min-microvolt = <1800000>; 160 regulator-max-microvolt = <3300000>; 161 }; 162 }; 163 }; 164 165 pcf85063: rtc@51 { 166 compatible = "nxp,pcf85063a"; 167 reg = <0x51>; 168 }; 169 170 at24c02: eeprom@53 { 171 compatible = "nxp,se97b", "atmel,24c02"; 172 read-only; 173 reg = <0x53>; 174 pagesize = <16>; 175 vcc-supply = <®_vcc3v3>; 176 }; 177 178 m24c64: eeprom@57 { 179 compatible = "atmel,24c64"; 180 reg = <0x57>; 181 pagesize = <32>; 182 vcc-supply = <®_vcc3v3>; 183 }; 184}; 185 186&usdhc3 { 187 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 188 pinctrl-0 = <&pinctrl_usdhc3>; 189 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 190 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 191 bus-width = <8>; 192 non-removable; 193 no-sd; 194 no-sdio; 195 vmmc-supply = <®_vcc3v3>; 196 vqmmc-supply = <®_vcc1v8>; 197 status = "okay"; 198}; 199 200&wdog1 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_wdog>; 203 fsl,ext-reset-output; 204 status = "okay"; 205}; 206 207&iomuxc { 208 pinctrl_flexspi0: flexspi0grp { 209 fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x142>, 210 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, 211 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, 212 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, 213 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, 214 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>; 215 }; 216 217 pinctrl_i2c1: i2c1grp { 218 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e2>, 219 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e2>; 220 }; 221 222 pinctrl_i2c1_gpio: i2c1-gpiogrp { 223 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001e2>, 224 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001e2>; 225 }; 226 227 pinctrl_pmic: pmicirqgrp { 228 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x1c0>; 229 }; 230 231 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 232 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>; 233 }; 234 235 pinctrl_usdhc3: usdhc3grp { 236 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 237 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 238 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 239 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 240 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 241 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 242 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 243 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 244 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 245 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 246 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 247 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 248 }; 249 250 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 251 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 252 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 253 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 254 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 255 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 256 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 257 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 258 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 259 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 260 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 261 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 262 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 263 }; 264 265 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 266 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 267 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>, 268 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 269 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 270 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 271 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 272 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 273 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 274 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 275 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 276 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x84>, 277 <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x84>; 278 }; 279 280 pinctrl_wdog: wdoggrp { 281 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x1c4>; 282 }; 283}; 284