xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi (revision 8a5f956a9fb7d74fff681145082acfad5afa6bb8) 
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
12	compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
13
14	memory@40000000 {
15		device_type = "memory";
16		reg = <0x0 0x40000000 0 0x80000000>;
17	};
18
19	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
20		compatible = "regulator-gpio";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
23		regulator-name = "V_SD2";
24		regulator-min-microvolt = <1800000>;
25		regulator-max-microvolt = <3300000>;
26		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
27		states = <1800000 0x1>,
28			 <3300000 0x0>;
29		vin-supply = <&ldo5_reg>;
30		status = "disabled";
31	};
32};
33
34&A53_0 {
35	cpu-supply = <&buck2_reg>;
36};
37
38&easrc {
39	status = "okay";
40};
41
42&flexspi {
43	pinctrl-names = "default";
44	pinctrl-0 = <&pinctrl_flexspi0>;
45	status = "okay";
46
47	flash0: flash@0 {
48		reg = <0>;
49		compatible = "jedec,spi-nor";
50		spi-max-frequency = <80000000>;
51		spi-tx-bus-width = <1>;
52		spi-rx-bus-width = <4>;
53		vcc-supply = <&buck5_reg>;
54
55		partitions {
56			compatible = "fixed-partitions";
57			#address-cells = <1>;
58			#size-cells = <1>;
59		};
60	};
61};
62
63&i2c1 {
64	clock-frequency = <384000>;
65	pinctrl-names = "default", "gpio";
66	pinctrl-0 = <&pinctrl_i2c1>;
67	pinctrl-1 = <&pinctrl_i2c1_gpio>;
68	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
69	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
70	status = "okay";
71
72	se97: temperature-sensor@1b {
73		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
74		reg = <0x1b>;
75	};
76
77	pmic: pmic@25 {
78		reg = <0x25>;
79		compatible = "nxp,pca9450c";
80
81		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
82		pinctrl-0 = <&pinctrl_pmic>;
83		pinctrl-names = "default";
84		interrupt-parent = <&gpio1>;
85		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
86
87		regulators {
88			/* V_0V85_SOC: 0.85 .. 0.95 */
89			buck1_reg: BUCK1 {
90				regulator-name = "BUCK1";
91				regulator-min-microvolt = <850000>;
92				regulator-max-microvolt = <950000>;
93				regulator-boot-on;
94				regulator-always-on;
95				regulator-ramp-delay = <3125>;
96			};
97
98			/* VDD_ARM */
99			buck2_reg: BUCK2 {
100				regulator-name = "BUCK2";
101				regulator-min-microvolt = <850000>;
102				regulator-max-microvolt = <1000000>;
103				regulator-boot-on;
104				regulator-always-on;
105				nxp,dvs-run-voltage = <950000>;
106				nxp,dvs-standby-voltage = <850000>;
107				regulator-ramp-delay = <3125>;
108			};
109
110			/* VCC3V3 -> VMMC, ... must not be changed */
111			buck4_reg: BUCK4 {
112				regulator-name = "BUCK4";
113				regulator-min-microvolt = <3300000>;
114				regulator-max-microvolt = <3300000>;
115				regulator-boot-on;
116				regulator-always-on;
117			};
118
119			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
120			buck5_reg: BUCK5 {
121				regulator-name = "BUCK5";
122				regulator-min-microvolt = <1800000>;
123				regulator-max-microvolt = <1800000>;
124				regulator-boot-on;
125				regulator-always-on;
126			};
127
128			/* V_1V1 -> RAM, ... must not be changed */
129			buck6_reg: BUCK6 {
130				regulator-name = "BUCK6";
131				regulator-min-microvolt = <1100000>;
132				regulator-max-microvolt = <1100000>;
133				regulator-boot-on;
134				regulator-always-on;
135			};
136
137			/* V_1V8_SNVS */
138			ldo1_reg: LDO1 {
139				regulator-name = "LDO1";
140				regulator-min-microvolt = <1800000>;
141				regulator-max-microvolt = <1800000>;
142				regulator-boot-on;
143				regulator-always-on;
144			};
145
146			/* V_1V8_ANA */
147			ldo3_reg: LDO3 {
148				regulator-name = "LDO3";
149				regulator-min-microvolt = <1800000>;
150				regulator-max-microvolt = <1800000>;
151				regulator-boot-on;
152				regulator-always-on;
153			};
154
155			/* unused */
156			ldo4_reg: LDO4 {
157				regulator-name = "LDO4";
158				regulator-min-microvolt = <800000>;
159				regulator-max-microvolt = <3300000>;
160			};
161
162			/* VCC SD IO - switched using SD2 VSELECT */
163			ldo5_reg: LDO5 {
164				regulator-name = "LDO5";
165				regulator-min-microvolt = <1800000>;
166				regulator-max-microvolt = <3300000>;
167			};
168		};
169	};
170
171	pcf85063: rtc@51 {
172		compatible = "nxp,pcf85063a";
173		reg = <0x51>;
174	};
175
176	at24c02: eeprom@53 {
177		compatible = "nxp,se97b", "atmel,24c02";
178		read-only;
179		reg = <0x53>;
180		pagesize = <16>;
181		vcc-supply = <&buck4_reg>;
182	};
183
184	m24c64: eeprom@57 {
185		compatible = "atmel,24c64";
186		reg = <0x57>;
187		pagesize = <32>;
188		vcc-supply = <&buck4_reg>;
189	};
190};
191
192&usdhc2 {
193	vqmmc-supply = <&reg_usdhc2_vqmmc>;
194};
195
196&usdhc3 {
197	pinctrl-names = "default", "state_100mhz", "state_200mhz";
198	pinctrl-0 = <&pinctrl_usdhc3>;
199	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
200	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
201	bus-width = <8>;
202	non-removable;
203	no-sd;
204	no-sdio;
205	vmmc-supply = <&buck4_reg>;
206	vqmmc-supply = <&buck5_reg>;
207	status = "okay";
208};
209
210&wdog1 {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_wdog>;
213	fsl,ext-reset-output;
214	status = "okay";
215};
216
217&iomuxc {
218	pinctrl_flexspi0: flexspi0grp {
219		fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK	0x142>,
220			   <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
221			   <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
222			   <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
223			   <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
224			   <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>;
225	};
226
227	pinctrl_i2c1: i2c1grp {
228		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e2>,
229			   <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e2>;
230	};
231
232	pinctrl_i2c1_gpio: i2c1-gpiogrp {
233		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001e2>,
234			   <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001e2>;
235	};
236
237	pinctrl_pmic: pmicirqgrp {
238		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x1c0>;
239	};
240
241	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
242		fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10>;
243	};
244
245	pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
246		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04		0xc0>;
247	};
248
249	pinctrl_usdhc3: usdhc3grp {
250		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
251			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
252			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
253			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
254			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
255			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
256			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
257			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
258			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
259			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
260			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
261			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
262	};
263
264	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
265		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
266			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
267			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
268			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
269			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
270			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
271			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
272			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
273			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
274			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
275			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
276			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
277	};
278
279	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
280		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
281			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
282			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
283			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
284			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
285			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
286			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
287			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
288			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
289			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
290			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
291			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
292	};
293
294	pinctrl_wdog: wdoggrp {
295		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x1c4>;
296	};
297};
298