1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 chassis-type = "embedded"; 19 20 chosen { 21 stdout-path = &uart4; 22 }; 23 24 iio-hwmon { 25 compatible = "iio-hwmon"; 26 io-channels = <&adc 0>, <&adc 1>; 27 }; 28 29 aliases { 30 mmc0 = &usdhc3; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc1; 33 rtc0 = &pcf85063; 34 rtc1 = &snvs_rtc; 35 spi0 = &flexspi; 36 spi1 = &ecspi1; 37 spi2 = &ecspi2; 38 spi3 = &ecspi3; 39 }; 40 41 backlight_lvds: backlight { 42 compatible = "pwm-backlight"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_backlight>; 45 pwms = <&pwm2 0 5000000 0>; 46 brightness-levels = <0 4 8 16 32 64 128 255>; 47 default-brightness-level = <7>; 48 power-supply = <®_vcc_12v0>; 49 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 50 status = "disabled"; 51 }; 52 53 clk_xtal25: clk-xtal25 { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <25000000>; 57 }; 58 59 connector { 60 compatible = "gpio-usb-b-connector", "usb-b-connector"; 61 type = "micro"; 62 label = "X29"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_usbcon0>; 65 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 66 67 port { 68 usb_dr_connector: endpoint { 69 remote-endpoint = <&usb3_dwc>; 70 }; 71 }; 72 }; 73 74 fan0: pwm-fan { 75 compatible = "pwm-fan"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_pwmfan>; 78 fan-supply = <®_pwm_fan>; 79 #cooling-cells = <2>; 80 /* typical 25 kHz -> 40.000 nsec */ 81 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; 82 cooling-levels = <0 32 64 128 196 240>; 83 pulses-per-revolution = <2>; 84 interrupt-parent = <&gpio5>; 85 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 86 status = "disabled"; 87 }; 88 89 gpio-keys { 90 compatible = "gpio-keys"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_gpiobutton>; 93 autorepeat; 94 95 switch-1 { 96 label = "S12"; 97 linux,code = <BTN_0>; 98 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 99 wakeup-source; 100 }; 101 102 switch-2 { 103 label = "S13"; 104 linux,code = <BTN_1>; 105 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 106 wakeup-source; 107 }; 108 }; 109 110 gpio-leds { 111 compatible = "gpio-leds"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_gpioled>; 114 115 led-0 { 116 color = <LED_COLOR_ID_GREEN>; 117 function = LED_FUNCTION_STATUS; 118 function-enumerator = <0>; 119 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 120 linux,default-trigger = "default-on"; 121 }; 122 123 led-1 { 124 color = <LED_COLOR_ID_GREEN>; 125 function = LED_FUNCTION_HEARTBEAT; 126 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 127 linux,default-trigger = "heartbeat"; 128 }; 129 130 led-2 { 131 color = <LED_COLOR_ID_YELLOW>; 132 function = LED_FUNCTION_STATUS; 133 function-enumerator = <1>; 134 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 135 }; 136 }; 137 138 hdmi-connector { 139 compatible = "hdmi-connector"; 140 label = "X44"; 141 type = "a"; 142 143 port { 144 hdmi_connector_in: endpoint { 145 remote-endpoint = <&hdmi_tx_out>; 146 }; 147 }; 148 }; 149 150 display: display { 151 /* 152 * Display is not fixed, so compatible has to be added from 153 * DT overlay 154 */ 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_lvdsdisplay>; 157 power-supply = <®_vcc_3v3>; 158 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 159 backlight = <&backlight_lvds>; 160 status = "disabled"; 161 }; 162 163 reg_pwm_fan: regulator-pwm-fan { 164 compatible = "regulator-fixed"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_regpwmfan>; 167 regulator-name = "FAN_PWR"; 168 regulator-min-microvolt = <12000000>; 169 regulator-max-microvolt = <12000000>; 170 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 171 enable-active-high; 172 vin-supply = <®_vcc_12v0>; 173 }; 174 175 reg_usdhc2_vmmc: regulator-usdhc2 { 176 compatible = "regulator-fixed"; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 179 regulator-name = "VSD_3V3"; 180 regulator-min-microvolt = <3300000>; 181 regulator-max-microvolt = <3300000>; 182 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 183 enable-active-high; 184 startup-delay-us = <100>; 185 off-on-delay-us = <12000>; 186 }; 187 188 reg_vcc_12v0: regulator-12v0 { 189 compatible = "regulator-fixed"; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_reg12v0>; 192 regulator-name = "VCC_12V0"; 193 regulator-min-microvolt = <12000000>; 194 regulator-max-microvolt = <12000000>; 195 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 196 enable-active-high; 197 }; 198 199 reg_vcc_1v8: regulator-1v8 { 200 compatible = "regulator-fixed"; 201 regulator-name = "VCC_1V8"; 202 regulator-min-microvolt = <1800000>; 203 regulator-max-microvolt = <1800000>; 204 }; 205 206 reg_vcc_3v3: regulator-3v3 { 207 compatible = "regulator-fixed"; 208 regulator-name = "VCC_3V3"; 209 regulator-min-microvolt = <3300000>; 210 regulator-max-microvolt = <3300000>; 211 }; 212 213 reg_vcc_5v0: regulator-5v0 { 214 compatible = "regulator-fixed"; 215 regulator-name = "VCC_5V0"; 216 regulator-min-microvolt = <5000000>; 217 regulator-max-microvolt = <5000000>; 218 }; 219 220 reserved-memory { 221 #address-cells = <2>; 222 #size-cells = <2>; 223 ranges; 224 225 /* global autoconfigured region for contiguous allocations */ 226 linux,cma { 227 compatible = "shared-dma-pool"; 228 reusable; 229 size = <0 0x38000000>; 230 alloc-ranges = <0 0x40000000 0 0xB0000000>; 231 linux,cma-default; 232 }; 233 }; 234 235 sound { 236 compatible = "fsl,imx-audio-tlv320aic32x4"; 237 model = "tq-tlv320aic32x"; 238 audio-cpu = <&sai3>; 239 audio-codec = <&tlv320aic3x04>; 240 }; 241 242 thermal-zones { 243 soc-thermal { 244 trips { 245 soc_active0: trip-active0 { 246 temperature = <40000>; 247 hysteresis = <5000>; 248 type = "active"; 249 }; 250 251 soc_active1: trip-active1 { 252 temperature = <48000>; 253 hysteresis = <3000>; 254 type = "active"; 255 }; 256 257 soc_active2: trip-active2 { 258 temperature = <60000>; 259 hysteresis = <10000>; 260 type = "active"; 261 }; 262 }; 263 264 cooling-maps { 265 map1 { 266 trip = <&soc_active0>; 267 cooling-device = <&fan0 1 1>; 268 }; 269 270 map2 { 271 trip = <&soc_active1>; 272 cooling-device = <&fan0 2 2>; 273 }; 274 275 map3 { 276 trip = <&soc_active2>; 277 cooling-device = <&fan0 3 3>; 278 }; 279 }; 280 }; 281 }; 282}; 283 284&ecspi1 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_ecspi1>; 287 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 288 status = "okay"; 289}; 290 291&ecspi2 { 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_ecspi2>; 294 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 295 status = "okay"; 296}; 297 298&ecspi3 { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_ecspi3>; 301 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 302 status = "okay"; 303 304 adc: adc@0 { 305 reg = <0>; 306 compatible = "microchip,mcp3202"; 307 /* 100 ksps * 18 */ 308 spi-max-frequency = <1800000>; 309 vref-supply = <®_vcc_3v3>; 310 #io-channel-cells = <1>; 311 }; 312}; 313 314&eqos { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 317 phy-mode = "rgmii-id"; 318 phy-handle = <ðphy3>; 319 status = "okay"; 320 321 mdio { 322 compatible = "snps,dwmac-mdio"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 326 ethphy3: ethernet-phy@3 { 327 compatible = "ethernet-phy-ieee802.3-c22"; 328 reg = <3>; 329 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 330 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 331 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 332 ti,dp83867-rxctrl-strap-quirk; 333 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 334 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 335 reset-assert-us = <500000>; 336 reset-deassert-us = <50000>; 337 enet-phy-lane-no-swap; 338 interrupt-parent = <&gpio4>; 339 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 340 }; 341 }; 342}; 343 344&fec { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 347 phy-mode = "rgmii-id"; 348 phy-handle = <ðphy0>; 349 fsl,magic-packet; 350 status = "okay"; 351 352 mdio { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 356 ethphy0: ethernet-phy@0 { 357 compatible = "ethernet-phy-ieee802.3-c22"; 358 reg = <0>; 359 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 360 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 361 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 362 ti,dp83867-rxctrl-strap-quirk; 363 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 364 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 365 reset-assert-us = <500000>; 366 reset-deassert-us = <50000>; 367 enet-phy-lane-no-swap; 368 interrupt-parent = <&gpio4>; 369 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 370 }; 371 }; 372}; 373 374&flexcan1 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_flexcan1>; 377 xceiver-supply = <®_vcc_3v3>; 378 status = "okay"; 379}; 380 381&flexcan2 { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_flexcan2>; 384 xceiver-supply = <®_vcc_3v3>; 385 status = "okay"; 386}; 387 388&gpio1 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_gpio1>; 391 392 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 393 "", "", "GPO2", "GPI0", 394 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 395 "OTG_PWR", "", "GPI2", "GPI3", 396 "", "", "", "", 397 "", "", "", "", 398 "", "", "", "", 399 "", "", "", ""; 400}; 401 402&gpio2 { 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_hoggpio2>; 405 406 gpio-line-names = "", "", "", "", 407 "", "", "VCC12V_EN", "PERST#", 408 "", "", "CLKREQ#", "PEWAKE#", 409 "USDHC2_CD", "", "", "", 410 "", "", "", "V_SD3V3_EN", 411 "", "", "", "", 412 "", "", "", "", 413 "", "", "", ""; 414 415 perst-hog { 416 gpio-hog; 417 gpios = <7 0>; 418 output-high; 419 line-name = "PERST#"; 420 }; 421 422 clkreq-hog { 423 gpio-hog; 424 gpios = <10 0>; 425 input; 426 line-name = "CLKREQ#"; 427 }; 428 429 pewake-hog { 430 gpio-hog; 431 gpios = <11 0>; 432 input; 433 line-name = "PEWAKE#"; 434 }; 435}; 436 437&gpio3 { 438 gpio-line-names = "", "", "", "", 439 "", "", "", "", 440 "", "", "", "", 441 "", "", "LVDS0_RESET#", "", 442 "", "", "", "LVDS0_BLT_EN", 443 "LVDS0_PWR_EN", "", "", "", 444 "", "", "", "", 445 "", "", "", ""; 446}; 447 448&gpio4 { 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_gpio4>; 451 452 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 453 "", "", "", "", 454 "", "", "", "", 455 "", "", "", "", 456 "", "", "DP_IRQ", "DSI_EN", 457 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 458 "", "", "", "FAN_PWR", 459 "RTC_EVENT#", "CODEC_RST#", "", ""; 460 461 pcie-refclkreq-hog { 462 gpio-hog; 463 gpios = <22 0>; 464 output-high; 465 line-name = "PCIE_REFCLK_OE#"; 466 }; 467}; 468 469&gpio5 { 470 gpio-line-names = "", "", "", "LED2", 471 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 472 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 473 "", "ECSPI2_SS0", "", "", 474 "", "", "", "", 475 "", "", "", "", 476 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 477 "", "", "", ""; 478}; 479 480&hdmi_pvi { 481 status = "okay"; 482}; 483 484&hdmi_tx { 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_hdmi>; 487 status = "okay"; 488 489 ports { 490 port@1 { 491 hdmi_tx_out: endpoint { 492 remote-endpoint = <&hdmi_connector_in>; 493 }; 494 }; 495 }; 496}; 497 498&hdmi_tx_phy { 499 status = "okay"; 500}; 501 502&i2c2 { 503 clock-frequency = <384000>; 504 pinctrl-names = "default", "gpio"; 505 pinctrl-0 = <&pinctrl_i2c2>; 506 pinctrl-1 = <&pinctrl_i2c2_gpio>; 507 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 508 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 509 status = "okay"; 510 511 tlv320aic3x04: audio-codec@18 { 512 compatible = "ti,tlv320aic32x4"; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&pinctrl_tlv320aic3x04>; 515 reg = <0x18>; 516 clock-names = "mclk"; 517 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 518 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; 519 iov-supply = <®_vcc_1v8>; 520 ldoin-supply = <®_vcc_3v3>; 521 }; 522 523 se97_1c: temperature-sensor@1c { 524 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 525 reg = <0x1c>; 526 }; 527 528 at24c02_54: eeprom@54 { 529 compatible = "nxp,se97b", "atmel,24c02"; 530 reg = <0x54>; 531 pagesize = <16>; 532 vcc-supply = <®_vcc_3v3>; 533 }; 534 535 pcieclk: clock-generator@6a { 536 compatible = "renesas,9fgv0241"; 537 reg = <0x6a>; 538 clocks = <&clk_xtal25>; 539 #clock-cells = <1>; 540 }; 541}; 542 543&i2c4 { 544 clock-frequency = <384000>; 545 pinctrl-names = "default", "gpio"; 546 pinctrl-0 = <&pinctrl_i2c4>; 547 pinctrl-1 = <&pinctrl_i2c4_gpio>; 548 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 549 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 550 status = "okay"; 551}; 552 553&i2c6 { 554 clock-frequency = <384000>; 555 pinctrl-names = "default", "gpio"; 556 pinctrl-0 = <&pinctrl_i2c6>; 557 pinctrl-1 = <&pinctrl_i2c6_gpio>; 558 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 559 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 560 status = "okay"; 561}; 562 563&lcdif3 { 564 status = "okay"; 565}; 566 567&pcf85063 { 568 /* RTC_EVENT# is connected on MBa8MPxL */ 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_pcf85063>; 571 interrupt-parent = <&gpio4>; 572 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 573}; 574 575&pcie_phy { 576 fsl,clkreq-unsupported; 577 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 578 clocks = <&pcieclk 0>; 579 clock-names = "ref"; 580 status = "okay"; 581}; 582 583&pcie { 584 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 585 <&clk IMX8MP_CLK_HSIO_AXI>, 586 <&clk IMX8MP_CLK_PCIE_ROOT>; 587 clock-names = "pcie", "pcie_bus", "pcie_aux"; 588 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 589 assigned-clock-rates = <10000000>; 590 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 591 status = "okay"; 592}; 593 594&pwm2 { 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_pwm2>; 597 status = "disabled"; 598}; 599 600&pwm3 { 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_pwm3>; 603 status = "okay"; 604}; 605 606&sai3 { 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_sai3>; 609 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 610 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 611 assigned-clock-rates = <12288000>; 612 fsl,sai-mclk-direction-output; 613 status = "okay"; 614}; 615 616&snvs_pwrkey { 617 status = "okay"; 618}; 619 620&uart1 { 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_uart1>; 623 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 624 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 625 status = "okay"; 626}; 627 628&uart2 { 629 pinctrl-names = "default"; 630 pinctrl-0 = <&pinctrl_uart2>; 631 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 632 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 633 status = "okay"; 634}; 635 636&uart3 { 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_uart3>; 639 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 640 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 641 status = "okay"; 642}; 643 644&uart4 { 645 /* console */ 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_uart4>; 648 status = "okay"; 649}; 650 651&usb3_0 { 652 pinctrl-names = "default"; 653 pinctrl-0 = <&pinctrl_usb0>; 654 fsl,over-current-active-low; 655 status = "okay"; 656}; 657 658&usb3_1 { 659 fsl,disable-port-power-control; 660 fsl,permanently-attached; 661 status = "okay"; 662}; 663 664&usb3_phy0 { 665 vbus-supply = <®_vcc_5v0>; 666 status = "okay"; 667}; 668 669&usb3_phy1 { 670 vbus-supply = <®_vcc_5v0>; 671 status = "okay"; 672}; 673 674&usb_dwc3_0 { 675 /* dual role is implemented, but not a full featured OTG */ 676 hnp-disable; 677 srp-disable; 678 adp-disable; 679 dr_mode = "otg"; 680 usb-role-switch; 681 role-switch-default-mode = "peripheral"; 682 status = "okay"; 683 684 port { 685 usb3_dwc: endpoint { 686 remote-endpoint = <&usb_dr_connector>; 687 }; 688 }; 689}; 690 691&usb_dwc3_1 { 692 dr_mode = "host"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_usbhub>; 697 status = "okay"; 698 699 hub_2_0: hub@1 { 700 compatible = "usb451,8142"; 701 reg = <1>; 702 peer-hub = <&hub_3_0>; 703 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 704 vdd-supply = <®_vcc_3v3>; 705 }; 706 707 hub_3_0: hub@2 { 708 compatible = "usb451,8140"; 709 reg = <2>; 710 peer-hub = <&hub_2_0>; 711 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 712 vdd-supply = <®_vcc_3v3>; 713 }; 714}; 715 716&usdhc2 { 717 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 718 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 719 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 720 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 721 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 722 vmmc-supply = <®_usdhc2_vmmc>; 723 no-mmc; 724 no-sdio; 725 disable-wp; 726 bus-width = <4>; 727 status = "okay"; 728}; 729 730&iomuxc { 731 pinctrl_backlight: backlightgrp { 732 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 733 }; 734 735 pinctrl_flexcan1: flexcan1grp { 736 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 737 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 738 }; 739 740 pinctrl_flexcan2: flexcan2grp { 741 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 742 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 743 }; 744 745 /* only on X57, primary used as CSI0 control signals */ 746 pinctrl_ecspi1: ecspi1grp { 747 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 748 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 749 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 750 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 751 }; 752 753 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 754 pinctrl_ecspi2: ecspi2grp { 755 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 756 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 757 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 758 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 759 }; 760 761 pinctrl_ecspi3: ecspi3grp { 762 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 763 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 764 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 765 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 766 }; 767 768 pinctrl_eqos: eqosgrp { 769 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 770 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 771 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 772 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 773 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 774 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 775 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 776 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 777 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 778 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 779 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 780 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 781 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 782 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 783 }; 784 785 pinctrl_eqos_event: eqosevtgrp { 786 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 787 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 788 }; 789 790 pinctrl_eqos_phy: eqosphygrp { 791 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 792 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 793 }; 794 795 pinctrl_fec: fecgrp { 796 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 797 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 798 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 799 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 800 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 801 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 802 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 803 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 804 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 805 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 806 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 807 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 808 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 809 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 810 }; 811 812 pinctrl_fec_event: fecevtgrp { 813 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 814 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 815 }; 816 817 pinctrl_fec_phy: fecphygrp { 818 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 819 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 820 }; 821 822 pinctrl_fec_phyalt: fecphyaltgrp { 823 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 824 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 825 }; 826 827 pinctrl_gpiobutton: gpiobuttongrp { 828 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 829 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 830 }; 831 832 pinctrl_gpioled: gpioledgrp { 833 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 834 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 835 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 836 }; 837 838 pinctrl_gpio1: gpio1grp { 839 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 840 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 841 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 842 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 843 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 844 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 845 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 846 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 847 }; 848 849 pinctrl_gpio4: gpio4grp { 850 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 851 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 852 }; 853 854 pinctrl_hdmi: hdmigrp { 855 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 856 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 857 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 858 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 859 }; 860 861 pinctrl_hoggpio2: hoggpio2grp { 862 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 863 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 864 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 865 }; 866 867 pinctrl_i2c2: i2c2grp { 868 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 869 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 870 }; 871 872 pinctrl_i2c2_gpio: i2c2-gpiogrp { 873 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 874 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 875 }; 876 877 pinctrl_i2c4: i2c4grp { 878 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 879 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 880 }; 881 882 pinctrl_i2c4_gpio: i2c4-gpiogrp { 883 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 884 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 885 }; 886 887 pinctrl_i2c6: i2c6grp { 888 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 889 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 890 }; 891 892 pinctrl_i2c6_gpio: i2c6-gpiogrp { 893 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 894 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 895 }; 896 897 pinctrl_lvdsdisplay: lvdsdisplaygrp { 898 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 899 }; 900 901 pinctrl_pcf85063: pcf85063grp { 902 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 903 }; 904 905 /* LVDS Backlight */ 906 pinctrl_pwm2: pwm2grp { 907 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 908 }; 909 910 /* FAN */ 911 pinctrl_pwm3: pwm3grp { 912 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 913 }; 914 915 pinctrl_pwmfan: pwmfangrp { 916 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ 917 }; 918 919 pinctrl_reg12v0: reg12v0grp { 920 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 921 }; 922 923 pinctrl_regpwmfan: regpwmfangrp { 924 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; 925 }; 926 927 pinctrl_sai3: sai3grp { 928 fsl,pins = < 929 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 930 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 931 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 932 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 933 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94 934 >; 935 }; 936 937 pinctrl_tlv320aic3x04: tlv320aic3x04grp { 938 fsl,pins = < 939 /* CODEC RST# */ 940 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180 941 >; 942 }; 943 944 /* X61 */ 945 pinctrl_uart1: uart1grp { 946 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 947 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 948 }; 949 950 /* X61 */ 951 pinctrl_uart2: uart2grp { 952 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 953 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 954 }; 955 956 pinctrl_uart3: uart3grp { 957 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 958 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 959 }; 960 961 pinctrl_uart4: uart4grp { 962 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 963 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 964 }; 965 966 pinctrl_usb0: usb0grp { 967 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 968 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 969 }; 970 971 pinctrl_usbcon0: usb0congrp { 972 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 973 }; 974 975 pinctrl_usbhub: usbhubgrp { 976 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 977 }; 978 979 pinctrl_usdhc2: usdhc2grp { 980 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 981 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 982 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 983 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 984 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 985 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 986 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 987 }; 988 989 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 990 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 991 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 992 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 993 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 994 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 995 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 996 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 997 }; 998 999 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1000 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1001 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1002 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1003 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1004 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1005 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 1006 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 1007 }; 1008 1009 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1010 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 1011 }; 1012}; 1013