1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 chassis-type = "embedded"; 19 20 chosen { 21 stdout-path = &uart4; 22 }; 23 24 iio-hwmon { 25 compatible = "iio-hwmon"; 26 io-channels = <&adc 0>, <&adc 1>; 27 }; 28 29 aliases { 30 mmc0 = &usdhc3; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc1; 33 rtc0 = &pcf85063; 34 rtc1 = &snvs_rtc; 35 spi0 = &flexspi; 36 spi1 = &ecspi1; 37 spi2 = &ecspi2; 38 spi3 = &ecspi3; 39 }; 40 41 backlight_lvds: backlight { 42 compatible = "pwm-backlight"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_backlight>; 45 pwms = <&pwm2 0 5000000 0>; 46 brightness-levels = <0 4 8 16 32 64 128 255>; 47 default-brightness-level = <7>; 48 power-supply = <®_vcc_12v0>; 49 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 50 status = "disabled"; 51 }; 52 53 clk_xtal25: clk-xtal25 { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <25000000>; 57 }; 58 59 connector { 60 compatible = "gpio-usb-b-connector", "usb-b-connector"; 61 type = "micro"; 62 label = "X29"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_usbcon0>; 65 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 66 67 port { 68 usb_dr_connector: endpoint { 69 remote-endpoint = <&usb3_dwc>; 70 }; 71 }; 72 }; 73 74 fan0: pwm-fan { 75 compatible = "pwm-fan"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_pwmfan>; 78 fan-supply = <®_pwm_fan>; 79 #cooling-cells = <2>; 80 /* typical 25 kHz -> 40.000 nsec */ 81 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; 82 cooling-levels = <0 32 64 128 196 240>; 83 pulses-per-revolution = <2>; 84 interrupt-parent = <&gpio5>; 85 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 86 status = "disabled"; 87 }; 88 89 gpio-keys { 90 compatible = "gpio-keys"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_gpiobutton>; 93 autorepeat; 94 95 switch-1 { 96 label = "S12"; 97 linux,code = <BTN_0>; 98 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 99 wakeup-source; 100 }; 101 102 switch-2 { 103 label = "S13"; 104 linux,code = <BTN_1>; 105 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 106 wakeup-source; 107 }; 108 }; 109 110 gpio-leds { 111 compatible = "gpio-leds"; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_gpioled>; 114 115 led-0 { 116 color = <LED_COLOR_ID_GREEN>; 117 function = LED_FUNCTION_STATUS; 118 function-enumerator = <0>; 119 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 120 linux,default-trigger = "default-on"; 121 }; 122 123 led-1 { 124 color = <LED_COLOR_ID_GREEN>; 125 function = LED_FUNCTION_HEARTBEAT; 126 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 127 linux,default-trigger = "heartbeat"; 128 }; 129 130 led-2 { 131 color = <LED_COLOR_ID_YELLOW>; 132 function = LED_FUNCTION_STATUS; 133 function-enumerator = <1>; 134 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 135 }; 136 }; 137 138 display: display { 139 /* 140 * Display is not fixed, so compatible has to be added from 141 * DT overlay 142 */ 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_lvdsdisplay>; 145 power-supply = <®_vcc_3v3>; 146 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 147 backlight = <&backlight_lvds>; 148 status = "disabled"; 149 }; 150 151 reg_pwm_fan: regulator-pwm-fan { 152 compatible = "regulator-fixed"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_regpwmfan>; 155 regulator-name = "FAN_PWR"; 156 regulator-min-microvolt = <12000000>; 157 regulator-max-microvolt = <12000000>; 158 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 159 enable-active-high; 160 vin-supply = <®_vcc_12v0>; 161 }; 162 163 reg_usdhc2_vmmc: regulator-usdhc2 { 164 compatible = "regulator-fixed"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 167 regulator-name = "VSD_3V3"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 171 enable-active-high; 172 startup-delay-us = <100>; 173 off-on-delay-us = <12000>; 174 }; 175 176 reg_vcc_12v0: regulator-12v0 { 177 compatible = "regulator-fixed"; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_reg12v0>; 180 regulator-name = "VCC_12V0"; 181 regulator-min-microvolt = <12000000>; 182 regulator-max-microvolt = <12000000>; 183 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 184 enable-active-high; 185 }; 186 187 reg_vcc_3v3: regulator-3v3 { 188 compatible = "regulator-fixed"; 189 regulator-name = "VCC_3V3"; 190 regulator-min-microvolt = <3300000>; 191 regulator-max-microvolt = <3300000>; 192 }; 193 194 reg_vcc_5v0: regulator-5v0 { 195 compatible = "regulator-fixed"; 196 regulator-name = "VCC_5V0"; 197 regulator-min-microvolt = <5000000>; 198 regulator-max-microvolt = <5000000>; 199 }; 200 201 reserved-memory { 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 ocram: ocram@900000 { 207 no-map; 208 reg = <0 0x900000 0 0x70000>; 209 }; 210 211 /* global autoconfigured region for contiguous allocations */ 212 linux,cma { 213 compatible = "shared-dma-pool"; 214 reusable; 215 size = <0 0x38000000>; 216 alloc-ranges = <0 0x40000000 0 0xB0000000>; 217 linux,cma-default; 218 }; 219 }; 220 221 sound { 222 compatible = "fsl,imx-audio-tlv320aic32x4"; 223 model = "tq-tlv320aic32x"; 224 audio-cpu = <&sai3>; 225 audio-codec = <&tlv320aic3x04>; 226 }; 227 228 thermal-zones { 229 soc-thermal { 230 trips { 231 soc_active0: trip-active0 { 232 temperature = <40000>; 233 hysteresis = <5000>; 234 type = "active"; 235 }; 236 237 soc_active1: trip-active1 { 238 temperature = <48000>; 239 hysteresis = <3000>; 240 type = "active"; 241 }; 242 243 soc_active2: trip-active2 { 244 temperature = <60000>; 245 hysteresis = <10000>; 246 type = "active"; 247 }; 248 }; 249 250 cooling-maps { 251 map1 { 252 trip = <&soc_active0>; 253 cooling-device = <&fan0 1 1>; 254 }; 255 256 map2 { 257 trip = <&soc_active1>; 258 cooling-device = <&fan0 2 2>; 259 }; 260 261 map3 { 262 trip = <&soc_active2>; 263 cooling-device = <&fan0 3 3>; 264 }; 265 }; 266 }; 267 }; 268}; 269 270&ecspi1 { 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_ecspi1>; 273 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 274 status = "okay"; 275}; 276 277&ecspi2 { 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_ecspi2>; 280 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 281 status = "okay"; 282}; 283 284&ecspi3 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_ecspi3>; 287 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 288 status = "okay"; 289 290 adc: adc@0 { 291 reg = <0>; 292 compatible = "microchip,mcp3202"; 293 /* 100 ksps * 18 */ 294 spi-max-frequency = <1800000>; 295 vref-supply = <®_vcc_3v3>; 296 #io-channel-cells = <1>; 297 }; 298}; 299 300&eqos { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 303 phy-mode = "rgmii-id"; 304 phy-handle = <ðphy3>; 305 status = "okay"; 306 307 mdio { 308 compatible = "snps,dwmac-mdio"; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 ethphy3: ethernet-phy@3 { 313 compatible = "ethernet-phy-ieee802.3-c22"; 314 reg = <3>; 315 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 316 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 317 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 318 ti,dp83867-rxctrl-strap-quirk; 319 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 320 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 321 reset-assert-us = <500000>; 322 reset-deassert-us = <50000>; 323 enet-phy-lane-no-swap; 324 interrupt-parent = <&gpio4>; 325 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 326 }; 327 }; 328}; 329 330&fec { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 333 phy-mode = "rgmii-id"; 334 phy-handle = <ðphy0>; 335 fsl,magic-packet; 336 status = "okay"; 337 338 mdio { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 342 ethphy0: ethernet-phy@0 { 343 compatible = "ethernet-phy-ieee802.3-c22"; 344 reg = <0>; 345 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 346 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 347 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 348 ti,dp83867-rxctrl-strap-quirk; 349 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 350 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 351 reset-assert-us = <500000>; 352 reset-deassert-us = <50000>; 353 enet-phy-lane-no-swap; 354 interrupt-parent = <&gpio4>; 355 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 356 }; 357 }; 358}; 359 360&flexcan1 { 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_flexcan1>; 363 xceiver-supply = <®_vcc_3v3>; 364 status = "okay"; 365}; 366 367&flexcan2 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_flexcan2>; 370 xceiver-supply = <®_vcc_3v3>; 371 status = "okay"; 372}; 373 374&gpio1 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_gpio1>; 377 378 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 379 "", "", "GPO2", "GPI0", 380 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 381 "OTG_PWR", "", "GPI2", "GPI3", 382 "", "", "", "", 383 "", "", "", "", 384 "", "", "", "", 385 "", "", "", ""; 386}; 387 388&gpio2 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_hoggpio2>; 391 392 gpio-line-names = "", "", "", "", 393 "", "", "VCC12V_EN", "PERST#", 394 "", "", "CLKREQ#", "PEWAKE#", 395 "USDHC2_CD", "", "", "", 396 "", "", "", "V_SD3V3_EN", 397 "", "", "", "", 398 "", "", "", "", 399 "", "", "", ""; 400 401 perst-hog { 402 gpio-hog; 403 gpios = <7 0>; 404 output-high; 405 line-name = "PERST#"; 406 }; 407 408 clkreq-hog { 409 gpio-hog; 410 gpios = <10 0>; 411 input; 412 line-name = "CLKREQ#"; 413 }; 414 415 pewake-hog { 416 gpio-hog; 417 gpios = <11 0>; 418 input; 419 line-name = "PEWAKE#"; 420 }; 421}; 422 423&gpio3 { 424 gpio-line-names = "", "", "", "", 425 "", "", "", "", 426 "", "", "", "", 427 "", "", "LVDS0_RESET#", "", 428 "", "", "", "LVDS0_BLT_EN", 429 "LVDS0_PWR_EN", "", "", "", 430 "", "", "", "", 431 "", "", "", ""; 432}; 433 434&gpio4 { 435 pinctrl-names = "default"; 436 pinctrl-0 = <&pinctrl_gpio4>; 437 438 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 439 "", "", "", "", 440 "", "", "", "", 441 "", "", "", "", 442 "", "", "DP_IRQ", "DSI_EN", 443 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 444 "", "", "", "FAN_PWR", 445 "RTC_EVENT#", "CODEC_RST#", "", ""; 446 447 pcie-refclkreq-hog { 448 gpio-hog; 449 gpios = <22 0>; 450 output-high; 451 line-name = "PCIE_REFCLK_OE#"; 452 }; 453}; 454 455&gpio5 { 456 gpio-line-names = "", "", "", "LED2", 457 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 458 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 459 "", "ECSPI2_SS0", "", "", 460 "", "", "", "", 461 "", "", "", "", 462 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 463 "", "", "", ""; 464}; 465 466&i2c2 { 467 clock-frequency = <384000>; 468 pinctrl-names = "default", "gpio"; 469 pinctrl-0 = <&pinctrl_i2c2>; 470 pinctrl-1 = <&pinctrl_i2c2_gpio>; 471 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 472 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 473 status = "okay"; 474 475 tlv320aic3x04: audio-codec@18 { 476 compatible = "ti,tlv320aic32x4"; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pinctrl_tlv320aic3x04>; 479 reg = <0x18>; 480 clock-names = "mclk"; 481 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 482 reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; 483 iov-supply = <®_vcc_3v3>; 484 ldoin-supply = <®_vcc_3v3>; 485 }; 486 487 se97_1c: temperature-sensor@1c { 488 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 489 reg = <0x1c>; 490 }; 491 492 at24c02_54: eeprom@54 { 493 compatible = "nxp,se97b", "atmel,24c02"; 494 reg = <0x54>; 495 pagesize = <16>; 496 vcc-supply = <®_vcc_3v3>; 497 }; 498 499 pcieclk: clock-generator@6a { 500 compatible = "renesas,9fgv0241"; 501 reg = <0x6a>; 502 clocks = <&clk_xtal25>; 503 #clock-cells = <1>; 504 }; 505}; 506 507&i2c4 { 508 clock-frequency = <384000>; 509 pinctrl-names = "default", "gpio"; 510 pinctrl-0 = <&pinctrl_i2c4>; 511 pinctrl-1 = <&pinctrl_i2c4_gpio>; 512 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 513 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 514 status = "okay"; 515}; 516 517&i2c6 { 518 clock-frequency = <384000>; 519 pinctrl-names = "default", "gpio"; 520 pinctrl-0 = <&pinctrl_i2c6>; 521 pinctrl-1 = <&pinctrl_i2c6_gpio>; 522 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 523 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 524 status = "okay"; 525}; 526 527&pcf85063 { 528 /* RTC_EVENT# is connected on MBa8MPxL */ 529 pinctrl-names = "default"; 530 pinctrl-0 = <&pinctrl_pcf85063>; 531 interrupt-parent = <&gpio4>; 532 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 533}; 534 535&pcie_phy { 536 fsl,clkreq-unsupported; 537 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 538 clocks = <&pcieclk 0>; 539 clock-names = "ref"; 540 status = "okay"; 541}; 542 543&pcie { 544 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 545 <&clk IMX8MP_CLK_HSIO_AXI>, 546 <&clk IMX8MP_CLK_PCIE_ROOT>; 547 clock-names = "pcie", "pcie_bus", "pcie_aux"; 548 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 549 assigned-clock-rates = <10000000>; 550 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 551 status = "okay"; 552}; 553 554&pwm2 { 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_pwm2>; 557 status = "disabled"; 558}; 559 560&pwm3 { 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_pwm3>; 563 status = "okay"; 564}; 565 566&sai3 { 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_sai3>; 569 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 570 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 571 assigned-clock-rates = <12288000>; 572 fsl,sai-mclk-direction-output; 573 status = "okay"; 574}; 575 576&snvs_pwrkey { 577 status = "okay"; 578}; 579 580&uart1 { 581 pinctrl-names = "default"; 582 pinctrl-0 = <&pinctrl_uart1>; 583 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 584 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 585 status = "okay"; 586}; 587 588&uart2 { 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pinctrl_uart2>; 591 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 592 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 593 status = "okay"; 594}; 595 596&uart3 { 597 pinctrl-names = "default"; 598 pinctrl-0 = <&pinctrl_uart3>; 599 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 600 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 601 status = "okay"; 602}; 603 604&uart4 { 605 /* console */ 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_uart4>; 608 status = "okay"; 609}; 610 611&usb3_0 { 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pinctrl_usb0>; 614 fsl,over-current-active-low; 615 status = "okay"; 616}; 617 618&usb3_1 { 619 fsl,disable-port-power-control; 620 fsl,permanently-attached; 621 status = "okay"; 622}; 623 624&usb3_phy0 { 625 vbus-supply = <®_vcc_5v0>; 626 status = "okay"; 627}; 628 629&usb3_phy1 { 630 vbus-supply = <®_vcc_5v0>; 631 status = "okay"; 632}; 633 634&usb_dwc3_0 { 635 /* dual role is implemented, but not a full featured OTG */ 636 hnp-disable; 637 srp-disable; 638 adp-disable; 639 dr_mode = "otg"; 640 usb-role-switch; 641 role-switch-default-mode = "peripheral"; 642 status = "okay"; 643 644 port { 645 usb3_dwc: endpoint { 646 remote-endpoint = <&usb_dr_connector>; 647 }; 648 }; 649}; 650 651&usb_dwc3_1 { 652 dr_mode = "host"; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&pinctrl_usbhub>; 657 status = "okay"; 658 659 hub_2_0: hub@1 { 660 compatible = "usb451,8142"; 661 reg = <1>; 662 peer-hub = <&hub_3_0>; 663 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 664 vdd-supply = <®_vcc_3v3>; 665 }; 666 667 hub_3_0: hub@2 { 668 compatible = "usb451,8140"; 669 reg = <2>; 670 peer-hub = <&hub_2_0>; 671 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 672 vdd-supply = <®_vcc_3v3>; 673 }; 674}; 675 676&usdhc2 { 677 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 678 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 679 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 680 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 681 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 682 vmmc-supply = <®_usdhc2_vmmc>; 683 no-mmc; 684 no-sdio; 685 disable-wp; 686 bus-width = <4>; 687 status = "okay"; 688}; 689 690&iomuxc { 691 pinctrl_backlight: backlightgrp { 692 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 693 }; 694 695 pinctrl_flexcan1: flexcan1grp { 696 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 697 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 698 }; 699 700 pinctrl_flexcan2: flexcan2grp { 701 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 702 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 703 }; 704 705 /* only on X57, primary used as CSI0 control signals */ 706 pinctrl_ecspi1: ecspi1grp { 707 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 708 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 709 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 710 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 711 }; 712 713 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 714 pinctrl_ecspi2: ecspi2grp { 715 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 716 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 717 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 718 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 719 }; 720 721 pinctrl_ecspi3: ecspi3grp { 722 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 723 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 724 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 725 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 726 }; 727 728 pinctrl_eqos: eqosgrp { 729 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 730 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 731 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 732 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 733 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 734 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 735 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 736 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 737 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 738 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 739 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 740 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 741 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 742 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 743 }; 744 745 pinctrl_eqos_event: eqosevtgrp { 746 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 747 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 748 }; 749 750 pinctrl_eqos_phy: eqosphygrp { 751 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 752 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 753 }; 754 755 pinctrl_fec: fecgrp { 756 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 757 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 758 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 759 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 760 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 761 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 762 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 763 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 764 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 765 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 766 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 767 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 768 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 769 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 770 }; 771 772 pinctrl_fec_event: fecevtgrp { 773 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 774 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 775 }; 776 777 pinctrl_fec_phy: fecphygrp { 778 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 779 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 780 }; 781 782 pinctrl_fec_phyalt: fecphyaltgrp { 783 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 784 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 785 }; 786 787 pinctrl_gpiobutton: gpiobuttongrp { 788 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 789 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 790 }; 791 792 pinctrl_gpioled: gpioledgrp { 793 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 794 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 795 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 796 }; 797 798 pinctrl_gpio1: gpio1grp { 799 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 800 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 801 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 802 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 803 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 804 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 805 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 806 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 807 }; 808 809 pinctrl_gpio4: gpio4grp { 810 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 811 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 812 }; 813 814 pinctrl_hdmi: hdmigrp { 815 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 816 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 817 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 818 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 819 }; 820 821 pinctrl_hoggpio2: hoggpio2grp { 822 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 823 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 824 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 825 }; 826 827 pinctrl_i2c2: i2c2grp { 828 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 829 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 830 }; 831 832 pinctrl_i2c2_gpio: i2c2-gpiogrp { 833 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 834 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 835 }; 836 837 pinctrl_i2c4: i2c4grp { 838 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 839 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 840 }; 841 842 pinctrl_i2c4_gpio: i2c4-gpiogrp { 843 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 844 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 845 }; 846 847 pinctrl_i2c6: i2c6grp { 848 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 849 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 850 }; 851 852 pinctrl_i2c6_gpio: i2c6-gpiogrp { 853 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 854 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 855 }; 856 857 pinctrl_lvdsdisplay: lvdsdisplaygrp { 858 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 859 }; 860 861 pinctrl_pcf85063: pcf85063grp { 862 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 863 }; 864 865 /* LVDS Backlight */ 866 pinctrl_pwm2: pwm2grp { 867 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 868 }; 869 870 /* FAN */ 871 pinctrl_pwm3: pwm3grp { 872 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 873 }; 874 875 pinctrl_pwmfan: pwmfangrp { 876 fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ 877 }; 878 879 pinctrl_reg12v0: reg12v0grp { 880 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 881 }; 882 883 pinctrl_regpwmfan: regpwmfangrp { 884 fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; 885 }; 886 887 pinctrl_sai3: sai3grp { 888 fsl,pins = < 889 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 890 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 891 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 892 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 893 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x94 894 >; 895 }; 896 897 pinctrl_tlv320aic3x04: tlv320aic3x04grp { 898 fsl,pins = < 899 /* CODEC RST# */ 900 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x180 901 >; 902 }; 903 904 /* X61 */ 905 pinctrl_uart1: uart1grp { 906 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 907 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 908 }; 909 910 /* X61 */ 911 pinctrl_uart2: uart2grp { 912 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 913 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 914 }; 915 916 pinctrl_uart3: uart3grp { 917 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 918 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 919 }; 920 921 pinctrl_uart4: uart4grp { 922 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 923 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 924 }; 925 926 pinctrl_usb0: usb0grp { 927 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 928 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 929 }; 930 931 pinctrl_usbcon0: usb0congrp { 932 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 933 }; 934 935 pinctrl_usbhub: usbhubgrp { 936 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 937 }; 938 939 pinctrl_usdhc2: usdhc2grp { 940 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 941 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 942 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 943 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 944 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 945 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 946 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 947 }; 948 949 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 950 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 951 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 952 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 953 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 954 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 955 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 956 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 957 }; 958 959 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 960 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 961 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 962 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 963 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 964 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 965 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 966 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 967 }; 968 969 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 970 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 971 }; 972}; 973