1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2021-2022 TQ-Systems GmbH 4 * Author: Alexander Stein <alexander.stein@tq-group.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include <dt-bindings/pwm/pwm.h> 13#include "imx8mp-tqma8mpql.dtsi" 14 15/ { 16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; 17 compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart4; 21 }; 22 23 iio-hwmon { 24 compatible = "iio-hwmon"; 25 io-channels = <&adc 0>, <&adc 1>; 26 }; 27 28 aliases { 29 mmc0 = &usdhc3; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc1; 32 rtc0 = &pcf85063; 33 rtc1 = &snvs_rtc; 34 spi0 = &flexspi; 35 spi1 = &ecspi1; 36 spi2 = &ecspi2; 37 spi3 = &ecspi3; 38 }; 39 40 backlight_lvds: backlight { 41 compatible = "pwm-backlight"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_backlight>; 44 pwms = <&pwm2 0 5000000 0>; 45 brightness-levels = <0 4 8 16 32 64 128 255>; 46 default-brightness-level = <7>; 47 power-supply = <®_vcc_12v0>; 48 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 49 status = "disabled"; 50 }; 51 52 clk_xtal25: clk-xtal25 { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 }; 57 58 gpio-keys { 59 compatible = "gpio-keys"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_gpiobutton>; 62 autorepeat; 63 64 switch-1 { 65 label = "S12"; 66 linux,code = <BTN_0>; 67 gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 68 }; 69 70 switch-2 { 71 label = "S13"; 72 linux,code = <BTN_1>; 73 gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 74 }; 75 }; 76 77 gpio-leds { 78 compatible = "gpio-leds"; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_gpioled>; 81 82 led-0 { 83 color = <LED_COLOR_ID_GREEN>; 84 function = LED_FUNCTION_STATUS; 85 function-enumerator = <0>; 86 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 87 linux,default-trigger = "default-on"; 88 }; 89 90 led-1 { 91 color = <LED_COLOR_ID_GREEN>; 92 function = LED_FUNCTION_HEARTBEAT; 93 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 94 linux,default-trigger = "heartbeat"; 95 }; 96 97 led-2 { 98 color = <LED_COLOR_ID_YELLOW>; 99 function = LED_FUNCTION_STATUS; 100 function-enumerator = <1>; 101 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 102 }; 103 }; 104 105 display: display { 106 /* 107 * Display is not fixed, so compatible has to be added from 108 * DT overlay 109 */ 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_lvdsdisplay>; 112 power-supply = <®_vcc_3v3>; 113 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; 114 backlight = <&backlight_lvds>; 115 status = "disabled"; 116 }; 117 118 reg_usdhc2_vmmc: regulator-usdhc2 { 119 compatible = "regulator-fixed"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 122 regulator-name = "VSD_3V3"; 123 regulator-min-microvolt = <3300000>; 124 regulator-max-microvolt = <3300000>; 125 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 126 enable-active-high; 127 startup-delay-us = <100>; 128 off-on-delay-us = <12000>; 129 }; 130 131 reg_vcc_12v0: regulator-12v0 { 132 compatible = "regulator-fixed"; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_reg12v0>; 135 regulator-name = "VCC_12V0"; 136 regulator-min-microvolt = <12000000>; 137 regulator-max-microvolt = <12000000>; 138 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 139 enable-active-high; 140 }; 141 142 reg_vcc_3v3: regulator-3v3 { 143 compatible = "regulator-fixed"; 144 regulator-name = "VCC_3V3"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 }; 148 149 reg_vcc_5v0: regulator-5v0 { 150 compatible = "regulator-fixed"; 151 regulator-name = "VCC_5V0"; 152 regulator-min-microvolt = <5000000>; 153 regulator-max-microvolt = <5000000>; 154 }; 155 156 reserved-memory { 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges; 160 161 ocram: ocram@900000 { 162 no-map; 163 reg = <0 0x900000 0 0x70000>; 164 }; 165 166 /* global autoconfigured region for contiguous allocations */ 167 linux,cma { 168 compatible = "shared-dma-pool"; 169 reusable; 170 size = <0 0x38000000>; 171 alloc-ranges = <0 0x40000000 0 0xB0000000>; 172 linux,cma-default; 173 }; 174 }; 175}; 176 177&ecspi1 { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_ecspi1>; 180 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 181 status = "okay"; 182}; 183 184&ecspi2 { 185 pinctrl-names = "default"; 186 pinctrl-0 = <&pinctrl_ecspi2>; 187 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 188 status = "okay"; 189}; 190 191&ecspi3 { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_ecspi3>; 194 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 195 status = "okay"; 196 197 adc: adc@0 { 198 reg = <0>; 199 compatible = "microchip,mcp3202"; 200 /* 100 ksps * 18 */ 201 spi-max-frequency = <1800000>; 202 vref-supply = <®_vcc_3v3>; 203 #io-channel-cells = <1>; 204 }; 205}; 206 207&eqos { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; 210 phy-mode = "rgmii-id"; 211 phy-handle = <ðphy3>; 212 status = "okay"; 213 214 mdio { 215 compatible = "snps,dwmac-mdio"; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 ethphy3: ethernet-phy@3 { 220 compatible = "ethernet-phy-ieee802.3-c22"; 221 reg = <3>; 222 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 223 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 224 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 225 ti,dp83867-rxctrl-strap-quirk; 226 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 227 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 228 reset-assert-us = <500000>; 229 reset-deassert-us = <50000>; 230 enet-phy-lane-no-swap; 231 interrupt-parent = <&gpio4>; 232 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 233 }; 234 }; 235}; 236 237&fec { 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>; 240 phy-mode = "rgmii-id"; 241 phy-handle = <ðphy0>; 242 fsl,magic-packet; 243 status = "okay"; 244 245 mdio { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 ethphy0: ethernet-phy@0 { 250 compatible = "ethernet-phy-ieee802.3-c22"; 251 reg = <0>; 252 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 253 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 254 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 255 ti,dp83867-rxctrl-strap-quirk; 256 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 257 reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 258 reset-assert-us = <500000>; 259 reset-deassert-us = <50000>; 260 enet-phy-lane-no-swap; 261 interrupt-parent = <&gpio4>; 262 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 263 }; 264 }; 265}; 266 267&flexcan1 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_flexcan1>; 270 xceiver-supply = <®_vcc_3v3>; 271 status = "okay"; 272}; 273 274&flexcan2 { 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_flexcan2>; 277 xceiver-supply = <®_vcc_3v3>; 278 status = "okay"; 279}; 280 281&gpio1 { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_gpio1>; 284 285 gpio-line-names = "GPO1", "GPO0", "", "GPO3", 286 "", "", "GPO2", "GPI0", 287 "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#", 288 "OTG_PWR", "", "GPI2", "GPI3", 289 "", "", "", "", 290 "", "", "", "", 291 "", "", "", "", 292 "", "", "", ""; 293}; 294 295&gpio2 { 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_hoggpio2>; 298 299 gpio-line-names = "", "", "", "", 300 "", "", "VCC12V_EN", "PERST#", 301 "", "", "CLKREQ#", "PEWAKE#", 302 "USDHC2_CD", "", "", "", 303 "", "", "", "V_SD3V3_EN", 304 "", "", "", "", 305 "", "", "", "", 306 "", "", "", ""; 307 308 perst-hog { 309 gpio-hog; 310 gpios = <7 0>; 311 output-high; 312 line-name = "PERST#"; 313 }; 314 315 clkreq-hog { 316 gpio-hog; 317 gpios = <10 0>; 318 input; 319 line-name = "CLKREQ#"; 320 }; 321 322 pewake-hog { 323 gpio-hog; 324 gpios = <11 0>; 325 input; 326 line-name = "PEWAKE#"; 327 }; 328}; 329 330&gpio3 { 331 gpio-line-names = "", "", "", "", 332 "", "", "", "", 333 "", "", "", "", 334 "", "", "LVDS0_RESET#", "", 335 "", "", "", "LVDS0_BLT_EN", 336 "LVDS0_PWR_EN", "", "", "", 337 "", "", "", "", 338 "", "", "", ""; 339}; 340 341&gpio4 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_gpio4>; 344 345 gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#", 346 "", "", "", "", 347 "", "", "", "", 348 "", "", "", "", 349 "", "", "DP_IRQ", "DSI_EN", 350 "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", 351 "", "", "", "FAN_PWR", 352 "RTC_EVENT#", "CODEC_RST#", "", ""; 353 354 pcie-refclkreq-hog { 355 gpio-hog; 356 gpios = <22 0>; 357 output-high; 358 line-name = "PCIE_REFCLK_OE#"; 359 }; 360}; 361 362&gpio5 { 363 gpio-line-names = "", "", "", "LED2", 364 "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC", 365 "CSI0_TRIGGER", "CSI0_ENABLE", "", "", 366 "", "ECSPI2_SS0", "", "", 367 "", "", "", "", 368 "", "", "", "", 369 "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B", 370 "", "", "", ""; 371}; 372 373&i2c2 { 374 clock-frequency = <384000>; 375 pinctrl-names = "default", "gpio"; 376 pinctrl-0 = <&pinctrl_i2c2>; 377 pinctrl-1 = <&pinctrl_i2c2_gpio>; 378 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 379 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 380 status = "okay"; 381 382 /* NXP SE97BTP with temperature sensor + eeprom */ 383 se97_1c: temperature-sensor-eeprom@1c { 384 compatible = "nxp,se97", "jedec,jc-42.4-temp"; 385 reg = <0x1c>; 386 }; 387 388 at24c02_54: eeprom@54 { 389 compatible = "nxp,se97b", "atmel,24c02"; 390 reg = <0x54>; 391 pagesize = <16>; 392 vcc-supply = <®_vcc_3v3>; 393 }; 394 395 pcieclk: clock-generator@6a { 396 compatible = "renesas,9fgv0241"; 397 reg = <0x6a>; 398 clocks = <&clk_xtal25>; 399 #clock-cells = <1>; 400 }; 401}; 402 403&i2c4 { 404 clock-frequency = <384000>; 405 pinctrl-names = "default", "gpio"; 406 pinctrl-0 = <&pinctrl_i2c4>; 407 pinctrl-1 = <&pinctrl_i2c4_gpio>; 408 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 409 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 410 status = "okay"; 411}; 412 413&i2c6 { 414 clock-frequency = <384000>; 415 pinctrl-names = "default", "gpio"; 416 pinctrl-0 = <&pinctrl_i2c6>; 417 pinctrl-1 = <&pinctrl_i2c6_gpio>; 418 scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 419 sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 420 status = "okay"; 421}; 422 423&pcf85063 { 424 /* RTC_EVENT# is connected on MBa8MPxL */ 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pinctrl_pcf85063>; 427 interrupt-parent = <&gpio4>; 428 interrupts = <28 IRQ_TYPE_EDGE_FALLING>; 429}; 430 431&pcie_phy { 432 fsl,clkreq-unsupported; 433 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 434 clocks = <&pcieclk 0>; 435 clock-names = "ref"; 436 status = "okay"; 437}; 438 439&pcie { 440 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 441 <&clk IMX8MP_CLK_HSIO_AXI>, 442 <&clk IMX8MP_CLK_PCIE_ROOT>; 443 clock-names = "pcie", "pcie_bus", "pcie_aux"; 444 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 445 assigned-clock-rates = <10000000>; 446 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 447 status = "okay"; 448}; 449 450&pwm2 { 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pinctrl_pwm2>; 453 status = "disabled"; 454}; 455 456&pwm3 { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_pwm3>; 459 status = "okay"; 460}; 461 462&snvs_pwrkey { 463 status = "okay"; 464}; 465 466&uart1 { 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_uart1>; 469 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 470 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 471 status = "okay"; 472}; 473 474&uart2 { 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_uart2>; 477 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 478 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 479 status = "okay"; 480}; 481 482&uart3 { 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pinctrl_uart3>; 485 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 486 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 487 status = "okay"; 488}; 489 490&uart4 { 491 /* console */ 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pinctrl_uart4>; 494 status = "okay"; 495}; 496 497&usb3_0 { 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_usb0>; 500 fsl,over-current-active-low; 501 status = "okay"; 502}; 503 504&usb3_1 { 505 fsl,disable-port-power-control; 506 fsl,permanently-attached; 507 dr_mode = "host"; 508 status = "okay"; 509}; 510 511&usb3_phy0 { 512 vbus-supply = <®_vcc_5v0>; 513 status = "okay"; 514}; 515 516&usb3_phy1 { 517 vbus-supply = <®_vcc_5v0>; 518 status = "okay"; 519}; 520 521&usb_dwc3_0 { 522 /* dual role is implemented, but not a full featured OTG */ 523 hnp-disable; 524 srp-disable; 525 adp-disable; 526 dr_mode = "otg"; 527 usb-role-switch; 528 role-switch-default-mode = "peripheral"; 529 status = "okay"; 530 531 connector { 532 compatible = "gpio-usb-b-connector", "usb-b-connector"; 533 type = "micro"; 534 label = "X29"; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_usbcon0>; 537 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 538 }; 539}; 540 541&usb_dwc3_1 { 542 dr_mode = "host"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&pinctrl_usbhub>; 547 status = "okay"; 548 549 hub_2_0: hub@1 { 550 compatible = "usb451,8142"; 551 reg = <1>; 552 peer-hub = <&hub_3_0>; 553 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 554 vdd-supply = <®_vcc_3v3>; 555 }; 556 557 hub_3_0: hub@2 { 558 compatible = "usb451,8140"; 559 reg = <2>; 560 peer-hub = <&hub_2_0>; 561 reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 562 vdd-supply = <®_vcc_3v3>; 563 }; 564}; 565 566&usdhc2 { 567 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 568 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 569 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 570 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 571 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 572 vmmc-supply = <®_usdhc2_vmmc>; 573 no-mmc; 574 no-sdio; 575 disable-wp; 576 bus-width = <4>; 577 status = "okay"; 578}; 579 580&iomuxc { 581 pinctrl_backlight: backlightgrp { 582 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x14>; 583 }; 584 585 pinctrl_flexcan1: flexcan1grp { 586 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x150>, 587 <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x150>; 588 }; 589 590 pinctrl_flexcan2: flexcan2grp { 591 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x150>, 592 <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x150>; 593 }; 594 595 /* only on X57, primary used as CSI0 control signals */ 596 pinctrl_ecspi1: ecspi1grp { 597 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c0>, 598 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1c0>, 599 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1c0>, 600 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c0>; 601 }; 602 603 /* on X63 and optionally on X57, can also be used as CSI1 control signals */ 604 pinctrl_ecspi2: ecspi2grp { 605 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c0>, 606 <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1c0>, 607 <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1c0>, 608 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c0>; 609 }; 610 611 pinctrl_ecspi3: ecspi3grp { 612 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x1c0>, 613 <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x1c0>, 614 <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 615 <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0>; 616 }; 617 618 pinctrl_eqos: eqosgrp { 619 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 620 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 621 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 622 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 623 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 624 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 625 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 626 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 627 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 628 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 629 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 630 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 631 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 632 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 633 }; 634 635 pinctrl_eqos_event: eqosevtgrp { 636 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x100>, 637 <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1c0>; 638 }; 639 640 pinctrl_eqos_phy: eqosphygrp { 641 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 642 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 643 }; 644 645 pinctrl_fec: fecgrp { 646 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 647 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 648 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 649 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 650 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 651 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 652 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 653 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 654 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 655 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 656 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 657 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 658 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 659 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 660 }; 661 662 pinctrl_fec_event: fecevtgrp { 663 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x100>, 664 <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1c0>; 665 }; 666 667 pinctrl_fec_phy: fecphygrp { 668 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 669 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 670 }; 671 672 pinctrl_fec_phyalt: fecphyaltgrp { 673 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x180>, 674 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>; 675 }; 676 677 pinctrl_gpiobutton: gpiobuttongrp { 678 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>, 679 <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x10>; 680 }; 681 682 pinctrl_gpioled: gpioledgrp { 683 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x14>, 684 <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x14>, 685 <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x14>; 686 }; 687 688 pinctrl_gpio1: gpio1grp { 689 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x10>, 690 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x10>, 691 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x10>, 692 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10>, 693 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80>, 694 <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x80>, 695 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>, 696 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 697 }; 698 699 pinctrl_gpio4: gpio4grp { 700 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x180>, 701 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x180>; 702 }; 703 704 pinctrl_hdmi: hdmigrp { 705 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 706 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 707 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 708 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010>; 709 }; 710 711 pinctrl_hoggpio2: hoggpio2grp { 712 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x140>, 713 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140>, 714 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140>; 715 }; 716 717 pinctrl_i2c2: i2c2grp { 718 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 719 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 720 }; 721 722 pinctrl_i2c2_gpio: i2c2-gpiogrp { 723 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 724 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 725 }; 726 727 pinctrl_i2c4: i2c4grp { 728 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e2>, 729 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e2>; 730 }; 731 732 pinctrl_i2c4_gpio: i2c4-gpiogrp { 733 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001e2>, 734 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001e2>; 735 }; 736 737 pinctrl_i2c6: i2c6grp { 738 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 739 <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 740 }; 741 742 pinctrl_i2c6_gpio: i2c6-gpiogrp { 743 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 744 <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 745 }; 746 747 pinctrl_lvdsdisplay: lvdsdisplaygrp { 748 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */ 749 }; 750 751 pinctrl_pcf85063: pcf85063grp { 752 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>; 753 }; 754 755 /* LVDS Backlight */ 756 pinctrl_pwm2: pwm2grp { 757 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>; 758 }; 759 760 /* FAN */ 761 pinctrl_pwm3: pwm3grp { 762 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; 763 }; 764 765 pinctrl_reg12v0: reg12v0grp { 766 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ 767 }; 768 769 /* X61 */ 770 pinctrl_uart1: uart1grp { 771 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, 772 <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140>; 773 }; 774 775 /* X61 */ 776 pinctrl_uart2: uart2grp { 777 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x140>, 778 <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x140>; 779 }; 780 781 pinctrl_uart3: uart3grp { 782 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 783 <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 784 }; 785 786 pinctrl_uart4: uart4grp { 787 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>, 788 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>; 789 }; 790 791 pinctrl_usb0: usb0grp { 792 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0>, 793 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x1c0>; 794 }; 795 796 pinctrl_usbcon0: usb0congrp { 797 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; 798 }; 799 800 pinctrl_usbhub: usbhubgrp { 801 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; 802 }; 803 804 pinctrl_usdhc2: usdhc2grp { 805 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 806 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 807 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 808 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 809 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 810 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 811 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 812 }; 813 814 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 815 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 816 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 817 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 818 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 819 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 820 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 821 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 822 }; 823 824 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 825 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 826 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 827 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 828 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 829 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 830 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 831 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 832 }; 833 834 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 835 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 836 }; 837}; 838