xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts (revision da5b2ad1c2f18834cb1ce429e2e5a5cf5cbdf21b) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/leds/leds-pca9532.h>
10#include <dt-bindings/pwm/pwm.h>
11#include "imx8mp-phycore-som.dtsi"
12
13/ {
14	model = "PHYTEC phyBOARD-Pollux i.MX8MP";
15	compatible = "phytec,imx8mp-phyboard-pollux-rdk",
16		     "phytec,imx8mp-phycore-som", "fsl,imx8mp";
17
18	chosen {
19		stdout-path = &uart1;
20	};
21
22	backlight_lvds: backlight {
23		compatible = "pwm-backlight";
24		pinctrl-names = "default";
25		pinctrl-0 = <&pinctrl_lvds1>;
26		brightness-levels = <0 4 8 16 32 64 128 255>;
27		default-brightness-level = <11>;
28		enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
29		num-interpolated-steps = <2>;
30		power-supply = <&reg_lvds1_reg_en>;
31		pwms = <&pwm3 0 50000 0>;
32	};
33
34	panel1_lvds: panel-lvds {
35		compatible = "edt,etml1010g3dra";
36		backlight = <&backlight_lvds>;
37		power-supply = <&reg_vcc_3v3_sw>;
38
39		port {
40			panel1_in: endpoint {
41				remote-endpoint = <&ldb_lvds_ch1>;
42			};
43		};
44	};
45
46	reg_can1_stby: regulator-can1-stby {
47		compatible = "regulator-fixed";
48		pinctrl-names = "default";
49		pinctrl-0 = <&pinctrl_flexcan1_reg>;
50		gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
51		regulator-max-microvolt = <3300000>;
52		regulator-min-microvolt = <3300000>;
53		regulator-name = "can1-stby";
54	};
55
56	reg_can2_stby: regulator-can2-stby {
57		compatible = "regulator-fixed";
58		pinctrl-names = "default";
59		pinctrl-0 = <&pinctrl_flexcan2_reg>;
60		gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
61		regulator-max-microvolt = <3300000>;
62		regulator-min-microvolt = <3300000>;
63		regulator-name = "can2-stby";
64	};
65
66	reg_lvds1_reg_en: regulator-lvds1 {
67		compatible = "regulator-fixed";
68		enable-active-high;
69		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
70		regulator-max-microvolt = <1200000>;
71		regulator-min-microvolt = <1200000>;
72		regulator-name = "lvds1_reg_en";
73	};
74
75	reg_usb1_vbus: regulator-usb1-vbus {
76		compatible = "regulator-fixed";
77		pinctrl-names = "default";
78		pinctrl-0 = <&pinctrl_usb1_vbus>;
79		gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
80		regulator-max-microvolt = <5000000>;
81		regulator-min-microvolt = <5000000>;
82		regulator-name = "usb1_host_vbus";
83	};
84
85	reg_usdhc2_vmmc: regulator-usdhc2 {
86		compatible = "regulator-fixed";
87		pinctrl-names = "default";
88		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
89		regulator-name = "VSD_3V3";
90		regulator-min-microvolt = <3300000>;
91		regulator-max-microvolt = <3300000>;
92		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
93		enable-active-high;
94		startup-delay-us = <100>;
95		off-on-delay-us = <12000>;
96	};
97
98	reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
99		compatible = "regulator-fixed";
100		regulator-name = "VCC_3V3_SW";
101		regulator-min-microvolt = <3300000>;
102		regulator-max-microvolt = <3300000>;
103	};
104};
105
106&eqos {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_eqos>;
109	phy-mode = "rgmii-id";
110	phy-handle = <&ethphy0>;
111	status = "okay";
112
113	mdio {
114		compatible = "snps,dwmac-mdio";
115		#address-cells = <1>;
116		#size-cells = <0>;
117
118		ethphy0: ethernet-phy@1 {
119			compatible = "ethernet-phy-ieee802.3-c22";
120			reg = <0x1>;
121			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
122			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
123			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
124			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
125			enet-phy-lane-no-swap;
126		};
127	};
128};
129
130/* CAN FD */
131&flexcan1 {
132	pinctrl-names = "default";
133	pinctrl-0 = <&pinctrl_flexcan1>;
134	xceiver-supply = <&reg_can1_stby>;
135	status = "okay";
136};
137
138&flexcan2 {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_flexcan2>;
141	xceiver-supply = <&reg_can2_stby>;
142	status = "okay";
143};
144
145&i2c2 {
146	clock-frequency = <400000>;
147	pinctrl-names = "default", "gpio";
148	pinctrl-0 = <&pinctrl_i2c2>;
149	pinctrl-1 = <&pinctrl_i2c2_gpio>;
150	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
151	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
152	status = "okay";
153
154	eeprom@51 {
155		compatible = "atmel,24c02";
156		reg = <0x51>;
157		pagesize = <16>;
158	};
159
160	leds@62 {
161		compatible = "nxp,pca9533";
162		reg = <0x62>;
163
164		led-1 {
165			type = <PCA9532_TYPE_LED>;
166		};
167
168		led-2 {
169			type = <PCA9532_TYPE_LED>;
170		};
171
172		led-3 {
173			type = <PCA9532_TYPE_LED>;
174		};
175	};
176};
177
178&lcdif2 {
179	status = "okay";
180};
181
182&lvds_bridge {
183	status = "okay";
184
185	ports {
186		port@2 {
187			ldb_lvds_ch1: endpoint {
188				remote-endpoint = <&panel1_in>;
189			};
190		};
191	};
192};
193
194&snvs_pwrkey {
195	status = "okay";
196};
197
198&pwm3 {
199	status = "okay";
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_pwm3>;
202};
203
204&rv3028 {
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_rtc>;
207	interrupt-parent = <&gpio4>;
208	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
209	wakeup-source;
210	trickle-resistor-ohms = <3000>;
211};
212
213/* debug console */
214&uart1 {
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_uart1>;
217	status = "okay";
218};
219
220/* USB1 Host mode Type-A */
221&usb3_phy0 {
222	vbus-supply = <&reg_usb1_vbus>;
223	status = "okay";
224};
225
226&usb3_0 {
227	status = "okay";
228};
229
230&usb_dwc3_0 {
231	dr_mode = "host";
232	status = "okay";
233};
234
235/* USB2 4-port USB3.0 HUB */
236&usb3_phy1 {
237	status = "okay";
238};
239
240&usb3_1 {
241	fsl,permanently-attached;
242	fsl,disable-port-power-control;
243	status = "okay";
244};
245
246&usb_dwc3_1 {
247	dr_mode = "host";
248	status = "okay";
249};
250
251/* RS232/RS485 */
252&uart2 {
253	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
254	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
255	pinctrl-names = "default";
256	pinctrl-0 = <&pinctrl_uart2>;
257	uart-has-rtscts;
258	status = "okay";
259};
260
261/* SD-Card */
262&usdhc2 {
263	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
264	assigned-clock-rates = <200000000>;
265	pinctrl-names = "default", "state_100mhz", "state_200mhz";
266	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
267	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
268	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
269	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
270	vmmc-supply = <&reg_usdhc2_vmmc>;
271	bus-width = <4>;
272	status = "okay";
273};
274
275&gpio1 {
276	gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
277		"PMIC_SD_VSEL", "", "", "", "", "",
278		"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
279};
280
281&gpio2 {
282	gpio-line-names = "", "", "", "",
283		"", "", "", "", "", "",
284		"", "", "X_SD2_CD_B", "", "", "",
285		"", "", "", "SD2_RESET_B";
286};
287
288&gpio3 {
289	gpio-line-names = "", "", "", "",
290		"", "", "", "", "", "",
291		"", "", "", "", "", "",
292		"", "", "", "", "nCAN1_EN", "nCAN2_EN";
293};
294
295&gpio4 {
296	gpio-line-names = "", "", "", "",
297		"", "", "", "", "", "",
298		"", "", "", "", "", "",
299		"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
300};
301
302&iomuxc {
303	pinctrl_eqos: eqosgrp {
304		fsl,pins = <
305			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
306			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
307			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
308			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
309			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
310			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
311			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
312			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
313			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x12
314			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x12
315			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x12
316			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x12
317			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12
318			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x12
319			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10
320		>;
321	};
322
323	pinctrl_flexcan1: flexcan1grp {
324		fsl,pins = <
325			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154
326			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154
327		>;
328	};
329
330	pinctrl_flexcan2: flexcan2grp {
331		fsl,pins = <
332			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
333			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
334		>;
335	};
336
337	pinctrl_flexcan1_reg: flexcan1reggrp {
338		fsl,pins = <
339			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x154
340		>;
341	};
342
343	pinctrl_flexcan2_reg: flexcan2reggrp {
344		fsl,pins = <
345			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x154
346		>;
347	};
348
349	pinctrl_i2c2: i2c2grp {
350		fsl,pins = <
351			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
352			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
353		>;
354	};
355
356	pinctrl_i2c2_gpio: i2c2gpiogrp {
357		fsl,pins = <
358			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2
359			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2
360		>;
361	};
362
363	pinctrl_lvds1: lvds1grp {
364		fsl,pins = <
365			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x12
366		>;
367	};
368
369	pinctrl_pwm3: pwm3grp {
370		fsl,pins = <
371			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT		0x12
372		>;
373	};
374
375	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
376		fsl,pins = <
377			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
378		>;
379	};
380
381	pinctrl_rtc: rtcgrp {
382		fsl,pins = <
383			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1C0
384		>;
385	};
386
387	pinctrl_uart1: uart1grp {
388		fsl,pins = <
389			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
390			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
391		>;
392	};
393
394	pinctrl_usb1_vbus: usb1vbusgrp {
395		fsl,pins = <
396			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x10
397		>;
398	};
399
400	pinctrl_uart2: uart2grp {
401		fsl,pins = <
402			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
403			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
404			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS	0x140
405			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS	0x140
406		>;
407	};
408
409	pinctrl_usdhc2_pins: usdhc2-gpiogrp {
410		fsl,pins = <
411			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40
412		>;
413	};
414
415	pinctrl_usdhc2: usdhc2grp {
416		fsl,pins = <
417			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
418			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
419			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
420			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
421			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
422			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
423			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
424		>;
425	};
426
427	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
428		fsl,pins = <
429			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
430			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
431			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
432			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
433			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
434			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
435			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
436		>;
437	};
438
439	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
440		fsl,pins = <
441			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
442			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
443			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
444			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
445			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
446			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
447			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
448		>;
449	};
450};
451