1*edfdb7bcSYannic Moog// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*edfdb7bcSYannic Moog/* 3*edfdb7bcSYannic Moog * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4*edfdb7bcSYannic Moog */ 5*edfdb7bcSYannic Moog 6*edfdb7bcSYannic Moog#include <dt-bindings/gpio/gpio.h> 7*edfdb7bcSYannic Moog#include <dt-bindings/clock/imx8mp-clock.h> 8*edfdb7bcSYannic Moog 9*edfdb7bcSYannic Moog/dts-v1/; 10*edfdb7bcSYannic Moog/plugin/; 11*edfdb7bcSYannic Moog 12*edfdb7bcSYannic Moog&backlight_lvds1 { 13*edfdb7bcSYannic Moog brightness-levels = <0 8 16 32 64 128 255>; 14*edfdb7bcSYannic Moog default-brightness-level = <8>; 15*edfdb7bcSYannic Moog enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; 16*edfdb7bcSYannic Moog num-interpolated-steps = <2>; 17*edfdb7bcSYannic Moog pwms = <&pwm3 0 50000 0>; 18*edfdb7bcSYannic Moog status = "okay"; 19*edfdb7bcSYannic Moog}; 20*edfdb7bcSYannic Moog 21*edfdb7bcSYannic Moog&lcdif2 { 22*edfdb7bcSYannic Moog status = "okay"; 23*edfdb7bcSYannic Moog}; 24*edfdb7bcSYannic Moog 25*edfdb7bcSYannic Moog&lvds_bridge { 26*edfdb7bcSYannic Moog assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; 27*edfdb7bcSYannic Moog assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 28*edfdb7bcSYannic Moog /* 29*edfdb7bcSYannic Moog * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to 30*edfdb7bcSYannic Moog * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout 31*edfdb7bcSYannic Moog * engine can reach accurate pixel clock of exactly 72.4 MHz. 32*edfdb7bcSYannic Moog */ 33*edfdb7bcSYannic Moog assigned-clock-rates = <0>, <506800000>; 34*edfdb7bcSYannic Moog status = "okay"; 35*edfdb7bcSYannic Moog}; 36*edfdb7bcSYannic Moog 37*edfdb7bcSYannic Moog&panel_lvds1 { 38*edfdb7bcSYannic Moog compatible = "edt,etml1010g3dra"; 39*edfdb7bcSYannic Moog status = "okay"; 40*edfdb7bcSYannic Moog}; 41*edfdb7bcSYannic Moog 42*edfdb7bcSYannic Moog&pwm3 { 43*edfdb7bcSYannic Moog status = "okay"; 44*edfdb7bcSYannic Moog}; 45