1*ab4d874cSMartyn Welch// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*ab4d874cSMartyn Welch/* 3*ab4d874cSMartyn Welch * Copyright 2020 Boundary Devices 4*ab4d874cSMartyn Welch * Copyright 2025 Collabora Ltd. 5*ab4d874cSMartyn Welch */ 6*ab4d874cSMartyn Welch 7*ab4d874cSMartyn Welch#include "imx8mp.dtsi" 8*ab4d874cSMartyn Welch 9*ab4d874cSMartyn Welch/ { 10*ab4d874cSMartyn Welch model = "Boundary Devices Nitrogen8M Plus Som"; 11*ab4d874cSMartyn Welch compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp"; 12*ab4d874cSMartyn Welch 13*ab4d874cSMartyn Welch rfkill-bt { 14*ab4d874cSMartyn Welch compatible = "rfkill-gpio"; 15*ab4d874cSMartyn Welch label = "rfkill-bluetooth"; 16*ab4d874cSMartyn Welch pinctrl-names = "default"; 17*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_rfkill_bt>; 18*ab4d874cSMartyn Welch radio-type = "bluetooth"; 19*ab4d874cSMartyn Welch shutdown-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; 20*ab4d874cSMartyn Welch }; 21*ab4d874cSMartyn Welch 22*ab4d874cSMartyn Welch rfkill-wlan { 23*ab4d874cSMartyn Welch compatible = "rfkill-gpio"; 24*ab4d874cSMartyn Welch label = "rfkill-wlan"; 25*ab4d874cSMartyn Welch pinctrl-names = "default"; 26*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_rfkill_wlan>; 27*ab4d874cSMartyn Welch radio-type = "wlan"; 28*ab4d874cSMartyn Welch shutdown-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; 29*ab4d874cSMartyn Welch }; 30*ab4d874cSMartyn Welch}; 31*ab4d874cSMartyn Welch 32*ab4d874cSMartyn Welch&A53_0 { 33*ab4d874cSMartyn Welch cpu-supply = <&buck2>; 34*ab4d874cSMartyn Welch}; 35*ab4d874cSMartyn Welch 36*ab4d874cSMartyn Welch&A53_1 { 37*ab4d874cSMartyn Welch cpu-supply = <&buck2>; 38*ab4d874cSMartyn Welch}; 39*ab4d874cSMartyn Welch 40*ab4d874cSMartyn Welch&A53_2 { 41*ab4d874cSMartyn Welch cpu-supply = <&buck2>; 42*ab4d874cSMartyn Welch}; 43*ab4d874cSMartyn Welch 44*ab4d874cSMartyn Welch&A53_3 { 45*ab4d874cSMartyn Welch cpu-supply = <&buck2>; 46*ab4d874cSMartyn Welch}; 47*ab4d874cSMartyn Welch 48*ab4d874cSMartyn Welch&eqos { 49*ab4d874cSMartyn Welch phy-handle = <ðphy0>; 50*ab4d874cSMartyn Welch phy-mode = "rgmii-id"; 51*ab4d874cSMartyn Welch pinctrl-names = "default"; 52*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_eqos>; 53*ab4d874cSMartyn Welch status = "okay"; 54*ab4d874cSMartyn Welch 55*ab4d874cSMartyn Welch mdio { 56*ab4d874cSMartyn Welch compatible = "snps,dwmac-mdio"; 57*ab4d874cSMartyn Welch #address-cells = <1>; 58*ab4d874cSMartyn Welch #size-cells = <0>; 59*ab4d874cSMartyn Welch 60*ab4d874cSMartyn Welch ethphy0: ethernet-phy@4 { 61*ab4d874cSMartyn Welch compatible = "ethernet-phy-ieee802.3-c22"; 62*ab4d874cSMartyn Welch reg = <4>; 63*ab4d874cSMartyn Welch eee-broken-1000t; 64*ab4d874cSMartyn Welch }; 65*ab4d874cSMartyn Welch }; 66*ab4d874cSMartyn Welch}; 67*ab4d874cSMartyn Welch 68*ab4d874cSMartyn Welch&i2c1 { 69*ab4d874cSMartyn Welch clock-frequency = <400000>; 70*ab4d874cSMartyn Welch pinctrl-names = "default", "gpio"; 71*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_i2c1>; 72*ab4d874cSMartyn Welch pinctrl-1 = <&pinctrl_i2c1_gpio>; 73*ab4d874cSMartyn Welch scl-gpios = <&gpio5 14 GPIO_OPEN_DRAIN>; 74*ab4d874cSMartyn Welch sda-gpios = <&gpio5 15 GPIO_OPEN_DRAIN>; 75*ab4d874cSMartyn Welch status = "okay"; 76*ab4d874cSMartyn Welch 77*ab4d874cSMartyn Welch pmic: pmic@25 { 78*ab4d874cSMartyn Welch compatible = "nxp,pca9450c"; 79*ab4d874cSMartyn Welch reg = <0x25>; 80*ab4d874cSMartyn Welch interrupt-parent = <&gpio3>; 81*ab4d874cSMartyn Welch interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 82*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_pmic>; 83*ab4d874cSMartyn Welch 84*ab4d874cSMartyn Welch regulators { 85*ab4d874cSMartyn Welch 86*ab4d874cSMartyn Welch buck1: BUCK1 { 87*ab4d874cSMartyn Welch regulator-name = "VDD_SOC (BUCK1)"; 88*ab4d874cSMartyn Welch regulator-always-on; 89*ab4d874cSMartyn Welch regulator-boot-on; 90*ab4d874cSMartyn Welch regulator-max-microvolt = <2187500>; 91*ab4d874cSMartyn Welch regulator-min-microvolt = <600000>; 92*ab4d874cSMartyn Welch regulator-ramp-delay = <3125>; 93*ab4d874cSMartyn Welch }; 94*ab4d874cSMartyn Welch 95*ab4d874cSMartyn Welch buck2: BUCK2 { 96*ab4d874cSMartyn Welch regulator-name = "VDD_ARM (BUCK2)"; 97*ab4d874cSMartyn Welch regulator-always-on; 98*ab4d874cSMartyn Welch regulator-boot-on; 99*ab4d874cSMartyn Welch regulator-max-microvolt = <2187500>; 100*ab4d874cSMartyn Welch regulator-min-microvolt = <600000>; 101*ab4d874cSMartyn Welch regulator-ramp-delay = <3125>; 102*ab4d874cSMartyn Welch }; 103*ab4d874cSMartyn Welch 104*ab4d874cSMartyn Welch buck4: BUCK4 { 105*ab4d874cSMartyn Welch regulator-name = "VDD_3P3V (BUCK4)"; 106*ab4d874cSMartyn Welch regulator-always-on; 107*ab4d874cSMartyn Welch regulator-boot-on; 108*ab4d874cSMartyn Welch regulator-max-microvolt = <3400000>; 109*ab4d874cSMartyn Welch regulator-min-microvolt = <600000>; 110*ab4d874cSMartyn Welch }; 111*ab4d874cSMartyn Welch 112*ab4d874cSMartyn Welch buck5: BUCK5 { 113*ab4d874cSMartyn Welch regulator-name = "VDD_1P8V (BUCK5)"; 114*ab4d874cSMartyn Welch regulator-always-on; 115*ab4d874cSMartyn Welch regulator-boot-on; 116*ab4d874cSMartyn Welch regulator-max-microvolt = <3400000>; 117*ab4d874cSMartyn Welch regulator-min-microvolt = <600000>; 118*ab4d874cSMartyn Welch }; 119*ab4d874cSMartyn Welch 120*ab4d874cSMartyn Welch buck6: BUCK6 { 121*ab4d874cSMartyn Welch regulator-name = "NVCC_DRAM_1P1V (BUCK6)"; 122*ab4d874cSMartyn Welch regulator-always-on; 123*ab4d874cSMartyn Welch regulator-boot-on; 124*ab4d874cSMartyn Welch regulator-max-microvolt = <3400000>; 125*ab4d874cSMartyn Welch regulator-min-microvolt = <600000>; 126*ab4d874cSMartyn Welch }; 127*ab4d874cSMartyn Welch 128*ab4d874cSMartyn Welch ldo1: LDO1 { 129*ab4d874cSMartyn Welch regulator-name = "NVCC_SNVS_1V8 (LDO1)"; 130*ab4d874cSMartyn Welch regulator-always-on; 131*ab4d874cSMartyn Welch regulator-boot-on; 132*ab4d874cSMartyn Welch regulator-max-microvolt = <3300000>; 133*ab4d874cSMartyn Welch regulator-min-microvolt = <1600000>; 134*ab4d874cSMartyn Welch }; 135*ab4d874cSMartyn Welch 136*ab4d874cSMartyn Welch ldo3: LDO3 { 137*ab4d874cSMartyn Welch regulator-name = "VDDA_1V8 (LDO3)"; 138*ab4d874cSMartyn Welch regulator-always-on; 139*ab4d874cSMartyn Welch regulator-boot-on; 140*ab4d874cSMartyn Welch regulator-max-microvolt = <3300000>; 141*ab4d874cSMartyn Welch regulator-min-microvolt = <800000>; 142*ab4d874cSMartyn Welch }; 143*ab4d874cSMartyn Welch 144*ab4d874cSMartyn Welch ldo5: LDO5 { 145*ab4d874cSMartyn Welch regulator-name = "NVCC_SD1 (LDO5)"; 146*ab4d874cSMartyn Welch regulator-max-microvolt = <3300000>; 147*ab4d874cSMartyn Welch regulator-min-microvolt = <1800000>; 148*ab4d874cSMartyn Welch }; 149*ab4d874cSMartyn Welch }; 150*ab4d874cSMartyn Welch }; 151*ab4d874cSMartyn Welch}; 152*ab4d874cSMartyn Welch 153*ab4d874cSMartyn Welch&i2c2 { 154*ab4d874cSMartyn Welch clock-frequency = <100000>; 155*ab4d874cSMartyn Welch pinctrl-names = "default", "gpio"; 156*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_i2c2>; 157*ab4d874cSMartyn Welch pinctrl-1 = <&pinctrl_i2c2_gpio>; 158*ab4d874cSMartyn Welch scl-gpios = <&gpio5 16 GPIO_OPEN_DRAIN>; 159*ab4d874cSMartyn Welch sda-gpios = <&gpio5 17 GPIO_OPEN_DRAIN>; 160*ab4d874cSMartyn Welch status = "okay"; 161*ab4d874cSMartyn Welch}; 162*ab4d874cSMartyn Welch 163*ab4d874cSMartyn Welch&i2c3 { 164*ab4d874cSMartyn Welch clock-frequency = <100000>; 165*ab4d874cSMartyn Welch pinctrl-names = "default", "gpio"; 166*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_i2c3>; 167*ab4d874cSMartyn Welch pinctrl-1 = <&pinctrl_i2c3_gpio>; 168*ab4d874cSMartyn Welch scl-gpios = <&gpio5 18 GPIO_OPEN_DRAIN>; 169*ab4d874cSMartyn Welch sda-gpios = <&gpio5 19 GPIO_OPEN_DRAIN>; 170*ab4d874cSMartyn Welch status = "okay"; 171*ab4d874cSMartyn Welch}; 172*ab4d874cSMartyn Welch 173*ab4d874cSMartyn Welch&i2c4 { 174*ab4d874cSMartyn Welch clock-frequency = <100000>; 175*ab4d874cSMartyn Welch pinctrl-names = "default", "gpio"; 176*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_i2c4>; 177*ab4d874cSMartyn Welch pinctrl-1 = <&pinctrl_i2c4_gpio>; 178*ab4d874cSMartyn Welch scl-gpios = <&gpio5 20 GPIO_OPEN_DRAIN>; 179*ab4d874cSMartyn Welch sda-gpios = <&gpio5 21 GPIO_OPEN_DRAIN>; 180*ab4d874cSMartyn Welch status = "okay"; 181*ab4d874cSMartyn Welch}; 182*ab4d874cSMartyn Welch 183*ab4d874cSMartyn Welch&uart1 { 184*ab4d874cSMartyn Welch pinctrl-names = "default"; 185*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_uart1>; 186*ab4d874cSMartyn Welch status = "okay"; 187*ab4d874cSMartyn Welch}; 188*ab4d874cSMartyn Welch 189*ab4d874cSMartyn Welch&usdhc2 { 190*ab4d874cSMartyn Welch bus-width = <4>; 191*ab4d874cSMartyn Welch keep-power-in-suspend; 192*ab4d874cSMartyn Welch non-removable; 193*ab4d874cSMartyn Welch pinctrl-names = "default", "state_100mhz", "state_200mhz"; 194*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_usdhc2>; 195*ab4d874cSMartyn Welch pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 196*ab4d874cSMartyn Welch pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 197*ab4d874cSMartyn Welch status = "okay"; 198*ab4d874cSMartyn Welch}; 199*ab4d874cSMartyn Welch 200*ab4d874cSMartyn Welch&usdhc3 { 201*ab4d874cSMartyn Welch bus-width = <8>; 202*ab4d874cSMartyn Welch non-removable; 203*ab4d874cSMartyn Welch no-mmc-hs400; 204*ab4d874cSMartyn Welch pinctrl-names = "default", "state_100mhz", "state_200mhz"; 205*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_usdhc3>; 206*ab4d874cSMartyn Welch pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 207*ab4d874cSMartyn Welch pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 208*ab4d874cSMartyn Welch status = "okay"; 209*ab4d874cSMartyn Welch}; 210*ab4d874cSMartyn Welch 211*ab4d874cSMartyn Welch&wdog1 { 212*ab4d874cSMartyn Welch pinctrl-names = "default"; 213*ab4d874cSMartyn Welch pinctrl-0 = <&pinctrl_wdog>; 214*ab4d874cSMartyn Welch fsl,ext-reset-output; 215*ab4d874cSMartyn Welch status = "okay"; 216*ab4d874cSMartyn Welch}; 217*ab4d874cSMartyn Welch 218*ab4d874cSMartyn Welch&iomuxc { 219*ab4d874cSMartyn Welch pinctrl_eqos: eqosgrp { 220*ab4d874cSMartyn Welch fsl,pins = < 221*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20 222*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0 223*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 224*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 225*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 226*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 227*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 228*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 229*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 230*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 231*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 232*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 233*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 234*ab4d874cSMartyn Welch MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 235*ab4d874cSMartyn Welch 236*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10 237*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100 238*ab4d874cSMartyn Welch >; 239*ab4d874cSMartyn Welch }; 240*ab4d874cSMartyn Welch 241*ab4d874cSMartyn Welch pinctrl_i2c1_gpio: i2c1gpiogrp { 242*ab4d874cSMartyn Welch fsl,pins = < 243*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 244*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 245*ab4d874cSMartyn Welch >; 246*ab4d874cSMartyn Welch }; 247*ab4d874cSMartyn Welch 248*ab4d874cSMartyn Welch pinctrl_i2c1: i2c1grp { 249*ab4d874cSMartyn Welch fsl,pins = < 250*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 251*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 252*ab4d874cSMartyn Welch >; 253*ab4d874cSMartyn Welch }; 254*ab4d874cSMartyn Welch 255*ab4d874cSMartyn Welch pinctrl_i2c2_gpio: i2c2gpiogrp { 256*ab4d874cSMartyn Welch fsl,pins = < 257*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 258*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 259*ab4d874cSMartyn Welch >; 260*ab4d874cSMartyn Welch }; 261*ab4d874cSMartyn Welch 262*ab4d874cSMartyn Welch pinctrl_i2c2: i2c2grp { 263*ab4d874cSMartyn Welch fsl,pins = < 264*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 265*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 266*ab4d874cSMartyn Welch >; 267*ab4d874cSMartyn Welch }; 268*ab4d874cSMartyn Welch 269*ab4d874cSMartyn Welch pinctrl_i2c3_gpio: i2c3gpiogrp { 270*ab4d874cSMartyn Welch fsl,pins = < 271*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 272*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 273*ab4d874cSMartyn Welch >; 274*ab4d874cSMartyn Welch }; 275*ab4d874cSMartyn Welch 276*ab4d874cSMartyn Welch pinctrl_i2c3: i2c3grp { 277*ab4d874cSMartyn Welch fsl,pins = < 278*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 279*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 280*ab4d874cSMartyn Welch >; 281*ab4d874cSMartyn Welch }; 282*ab4d874cSMartyn Welch 283*ab4d874cSMartyn Welch pinctrl_i2c4_gpio: i2c4gpiogrp { 284*ab4d874cSMartyn Welch fsl,pins = < 285*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3 286*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3 287*ab4d874cSMartyn Welch >; 288*ab4d874cSMartyn Welch }; 289*ab4d874cSMartyn Welch 290*ab4d874cSMartyn Welch pinctrl_i2c4: i2c4grp { 291*ab4d874cSMartyn Welch fsl,pins = < 292*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 293*ab4d874cSMartyn Welch MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 294*ab4d874cSMartyn Welch >; 295*ab4d874cSMartyn Welch }; 296*ab4d874cSMartyn Welch 297*ab4d874cSMartyn Welch pinctrl_pmic: pmicirqgrp { 298*ab4d874cSMartyn Welch fsl,pins = < 299*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 300*ab4d874cSMartyn Welch >; 301*ab4d874cSMartyn Welch }; 302*ab4d874cSMartyn Welch 303*ab4d874cSMartyn Welch pinctrl_rfkill_bt: rfkill-btgrp { 304*ab4d874cSMartyn Welch fsl,pins = < 305*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 306*ab4d874cSMartyn Welch >; 307*ab4d874cSMartyn Welch }; 308*ab4d874cSMartyn Welch 309*ab4d874cSMartyn Welch pinctrl_rfkill_wlan: rfkill-wlangrp { 310*ab4d874cSMartyn Welch fsl,pins = < 311*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16 312*ab4d874cSMartyn Welch >; 313*ab4d874cSMartyn Welch }; 314*ab4d874cSMartyn Welch 315*ab4d874cSMartyn Welch pinctrl_uart1: uart1grp { 316*ab4d874cSMartyn Welch fsl,pins = < 317*ab4d874cSMartyn Welch MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 318*ab4d874cSMartyn Welch MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 319*ab4d874cSMartyn Welch MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 320*ab4d874cSMartyn Welch MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 321*ab4d874cSMartyn Welch >; 322*ab4d874cSMartyn Welch }; 323*ab4d874cSMartyn Welch 324*ab4d874cSMartyn Welch pinctrl_usdhc2: usdhc2grp { 325*ab4d874cSMartyn Welch fsl,pins = < 326*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 327*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 328*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 329*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 330*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 331*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 332*ab4d874cSMartyn Welch >; 333*ab4d874cSMartyn Welch }; 334*ab4d874cSMartyn Welch 335*ab4d874cSMartyn Welch pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 336*ab4d874cSMartyn Welch fsl,pins = < 337*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 338*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 339*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 340*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 341*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 342*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 343*ab4d874cSMartyn Welch >; 344*ab4d874cSMartyn Welch }; 345*ab4d874cSMartyn Welch 346*ab4d874cSMartyn Welch pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 347*ab4d874cSMartyn Welch fsl,pins = < 348*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 349*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 350*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 351*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 352*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 353*ab4d874cSMartyn Welch MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 354*ab4d874cSMartyn Welch >; 355*ab4d874cSMartyn Welch }; 356*ab4d874cSMartyn Welch 357*ab4d874cSMartyn Welch pinctrl_usdhc3: usdhc3grp { 358*ab4d874cSMartyn Welch fsl,pins = < 359*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x10 360*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x150 361*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x150 362*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x150 363*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x150 364*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x150 365*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x150 366*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x150 367*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x150 368*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x150 369*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140 370*ab4d874cSMartyn Welch 371*ab4d874cSMartyn Welch >; 372*ab4d874cSMartyn Welch }; 373*ab4d874cSMartyn Welch 374*ab4d874cSMartyn Welch pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 375*ab4d874cSMartyn Welch fsl,pins = < 376*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x14 377*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x154 378*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x154 379*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x154 380*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x154 381*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x154 382*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x154 383*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x154 384*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x154 385*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x154 386*ab4d874cSMartyn Welch >; 387*ab4d874cSMartyn Welch }; 388*ab4d874cSMartyn Welch 389*ab4d874cSMartyn Welch pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 390*ab4d874cSMartyn Welch fsl,pins = < 391*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x12 392*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x152 393*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x152 394*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x152 395*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x152 396*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x152 397*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x152 398*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x152 399*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x152 400*ab4d874cSMartyn Welch MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x152 401*ab4d874cSMartyn Welch >; 402*ab4d874cSMartyn Welch }; 403*ab4d874cSMartyn Welch 404*ab4d874cSMartyn Welch pinctrl_wdog: wdoggrp { 405*ab4d874cSMartyn Welch fsl,pins = < 406*ab4d874cSMartyn Welch MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 407*ab4d874cSMartyn Welch >; 408*ab4d874cSMartyn Welch }; 409*ab4d874cSMartyn Welch}; 410