1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Emcraft Systems 4 * Copyright 2024 Gilles Talis <gilles.talis@gmail.com> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/leds/common.h> 11#include "imx8mp.dtsi" 12 13/ { 14 model = "Emcraft Systems i.MX8MPlus NavQ+ Kit"; 15 compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp"; 16 17 chosen { 18 stdout-path = &uart2; 19 }; 20 21 leds { 22 compatible = "gpio-leds"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_gpio_led>; 25 26 led-0 { 27 color = <LED_COLOR_ID_GREEN>; 28 function = LED_FUNCTION_STATUS; 29 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 30 default-state = "on"; 31 }; 32 }; 33 34 reg_usdhc2_vmmc: regulator-usdhc2 { 35 compatible = "regulator-fixed"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 38 regulator-name = "VSD_3V3"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 42 enable-active-high; 43 startup-delay-us = <100>; 44 off-on-delay-us = <12000>; 45 }; 46}; 47 48&A53_0 { 49 cpu-supply = <&buck2>; 50}; 51 52&A53_1 { 53 cpu-supply = <&buck2>; 54}; 55 56&A53_2 { 57 cpu-supply = <&buck2>; 58}; 59 60&A53_3 { 61 cpu-supply = <&buck2>; 62}; 63 64&eqos { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_eqos>; 67 phy-mode = "rgmii-id"; 68 phy-handle = <ðphy0>; 69 status = "okay"; 70 71 mdio { 72 compatible = "snps,dwmac-mdio"; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 ethphy0: ethernet-phy@0 { 77 compatible = "ethernet-phy-ieee802.3-c22"; 78 reg = <0>; 79 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 80 reset-assert-us = <1000>; 81 reset-deassert-us = <10000>; 82 qca,disable-smarteee; 83 qca,disable-hibernation-mode; 84 }; 85 }; 86}; 87 88&i2c1 { 89 clock-frequency = <400000>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_i2c1>; 92 status = "okay"; 93 94 pmic@25 { 95 compatible = "nxp,pca9450c"; 96 reg = <0x25>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_pmic>; 99 interrupt-parent = <&gpio1>; 100 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 101 102 regulators { 103 BUCK1 { 104 regulator-name = "BUCK1"; 105 regulator-min-microvolt = <600000>; 106 regulator-max-microvolt = <2187500>; 107 regulator-boot-on; 108 regulator-always-on; 109 regulator-ramp-delay = <3125>; 110 }; 111 112 buck2: BUCK2 { 113 regulator-name = "BUCK2"; 114 regulator-min-microvolt = <600000>; 115 regulator-max-microvolt = <2187500>; 116 regulator-boot-on; 117 regulator-always-on; 118 regulator-ramp-delay = <3125>; 119 nxp,dvs-run-voltage = <950000>; 120 nxp,dvs-standby-voltage = <850000>; 121 }; 122 123 BUCK4 { 124 regulator-name = "BUCK4"; 125 regulator-min-microvolt = <600000>; 126 regulator-max-microvolt = <3400000>; 127 regulator-boot-on; 128 regulator-always-on; 129 }; 130 131 BUCK5 { 132 regulator-name = "BUCK5"; 133 regulator-min-microvolt = <600000>; 134 regulator-max-microvolt = <3400000>; 135 regulator-boot-on; 136 regulator-always-on; 137 }; 138 139 BUCK6 { 140 regulator-name = "BUCK6"; 141 regulator-min-microvolt = <600000>; 142 regulator-max-microvolt = <3400000>; 143 regulator-boot-on; 144 regulator-always-on; 145 }; 146 147 LDO1 { 148 regulator-name = "LDO1"; 149 regulator-min-microvolt = <1600000>; 150 regulator-max-microvolt = <3300000>; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 LDO2 { 156 regulator-name = "LDO2"; 157 regulator-min-microvolt = <800000>; 158 regulator-max-microvolt = <1150000>; 159 regulator-boot-on; 160 regulator-always-on; 161 }; 162 163 LDO3 { 164 regulator-name = "LDO3"; 165 regulator-min-microvolt = <800000>; 166 regulator-max-microvolt = <3300000>; 167 regulator-boot-on; 168 regulator-always-on; 169 }; 170 171 LDO4 { 172 regulator-name = "LDO4"; 173 regulator-min-microvolt = <800000>; 174 regulator-max-microvolt = <3300000>; 175 regulator-boot-on; 176 regulator-always-on; 177 }; 178 179 LDO5 { 180 regulator-name = "LDO5"; 181 regulator-min-microvolt = <1800000>; 182 regulator-max-microvolt = <3300000>; 183 regulator-boot-on; 184 regulator-always-on; 185 }; 186 }; 187 }; 188}; 189 190&i2c2 { 191 clock-frequency = <400000>; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_i2c2>; 194 status = "okay"; 195}; 196 197&i2c3 { 198 clock-frequency = <400000>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_i2c3>; 201 status = "okay"; 202}; 203 204&i2c4 { 205 clock-frequency = <400000>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_i2c4>; 208 status = "okay"; 209 210 rtc@53 { 211 compatible = "nxp,pcf2131"; 212 reg = <0x53>; 213 }; 214}; 215 216&uart2 { 217 /* console */ 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_uart2>; 220 status = "okay"; 221}; 222 223/* SD Card */ 224&usdhc2 { 225 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 226 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 227 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 228 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 229 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 230 vmmc-supply = <®_usdhc2_vmmc>; 231 bus-width = <4>; 232 status = "okay"; 233}; 234 235/* eMMC */ 236&usdhc3 { 237 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 238 assigned-clock-rates = <400000000>; 239 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 240 pinctrl-0 = <&pinctrl_usdhc3>; 241 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 242 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 243 bus-width = <8>; 244 non-removable; 245 status = "okay"; 246}; 247 248&wdog1 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_wdog>; 251 fsl,ext-reset-output; 252 status = "okay"; 253}; 254 255&iomuxc { 256 pinctrl_eqos: eqosgrp { 257 fsl,pins = < 258 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 259 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 260 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 261 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 262 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 263 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 264 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 265 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 266 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 267 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 268 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 269 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 270 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 271 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 272 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110 273 >; 274 }; 275 276 pinctrl_gpio_led: gpioledgrp { 277 fsl,pins = < 278 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 279 >; 280 }; 281 282 pinctrl_i2c1: i2c1grp { 283 fsl,pins = < 284 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 285 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 286 >; 287 }; 288 289 pinctrl_i2c2: i2c2grp { 290 fsl,pins = < 291 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 292 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 293 >; 294 }; 295 296 pinctrl_i2c3: i2c3grp { 297 fsl,pins = < 298 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 299 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 300 >; 301 }; 302 303 pinctrl_i2c4: i2c4grp { 304 fsl,pins = < 305 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 306 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 307 >; 308 }; 309 310 pinctrl_pmic: pmicgrp { 311 fsl,pins = < 312 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 313 >; 314 }; 315 316 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 317 fsl,pins = < 318 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 319 >; 320 }; 321 322 pinctrl_uart2: uart2grp { 323 fsl,pins = < 324 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 325 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 326 >; 327 }; 328 329 pinctrl_usdhc2: usdhc2grp { 330 fsl,pins = < 331 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 332 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 333 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 334 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 335 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 336 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 337 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 338 >; 339 }; 340 341 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 342 fsl,pins = < 343 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 344 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 345 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 346 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 347 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 348 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 349 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 350 >; 351 }; 352 353 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 354 fsl,pins = < 355 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 356 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 357 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 358 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 359 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 360 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 361 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 362 >; 363 }; 364 365 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 366 fsl,pins = < 367 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 368 >; 369 }; 370 371 pinctrl_usdhc3: usdhc3grp { 372 fsl,pins = < 373 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 374 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 375 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 376 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 377 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 378 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 379 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 380 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 381 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 382 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 383 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 384 >; 385 }; 386 387 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 388 fsl,pins = < 389 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 390 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 391 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 392 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 393 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 394 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 395 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 396 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 397 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 398 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 399 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 400 >; 401 }; 402 403 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 404 fsl,pins = < 405 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 406 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 407 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 408 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 409 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 410 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 411 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 412 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 413 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 414 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 415 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 416 >; 417 }; 418 419 pinctrl_wdog: wdoggrp { 420 fsl,pins = < 421 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 422 >; 423 }; 424}; 425