xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts (revision be3216d626774412d15fed1ab0d3ef916c0e5acb)
1f703b602SMartyn Welch// SPDX-License-Identifier: GPL-2.0
2f703b602SMartyn Welch/*
3f703b602SMartyn Welch * Copyright (C) 2022 Avnet Embedded GmbH
4f703b602SMartyn Welch */
5f703b602SMartyn Welch
6f703b602SMartyn Welch/dts-v1/;
7f703b602SMartyn Welch
8f703b602SMartyn Welch#include "imx8mp-msc-sm2s-14N0600E.dtsi"
9f703b602SMartyn Welch#include <dt-bindings/clock/imx8mp-clock.h>
10f703b602SMartyn Welch#include <dt-bindings/gpio/gpio.h>
11f703b602SMartyn Welch
12f703b602SMartyn Welch/ {
13f703b602SMartyn Welch	model = "MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM";
14f703b602SMartyn Welch	compatible = "avnet,sm2s-imx8mp-14N0600E-ep1",
15f703b602SMartyn Welch		     "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp",
16f703b602SMartyn Welch		     "fsl,imx8mp";
17d874b9f7SLuca Ceresoli
18d874b9f7SLuca Ceresoli	reg_vcc_3v3_audio: 3v3-audio-regulator {
19d874b9f7SLuca Ceresoli		compatible = "regulator-fixed";
20d874b9f7SLuca Ceresoli		regulator-name = "VCC_3V3_AUD";
21d874b9f7SLuca Ceresoli		regulator-min-microvolt = <3300000>;
22d874b9f7SLuca Ceresoli		regulator-max-microvolt = <3300000>;
23d874b9f7SLuca Ceresoli	};
24d874b9f7SLuca Ceresoli
25d874b9f7SLuca Ceresoli	reg_vcc_1v8_audio: 1v8-audio-regulator {
26d874b9f7SLuca Ceresoli		compatible = "regulator-fixed";
27d874b9f7SLuca Ceresoli		regulator-name = "VCC_1V8_AUD";
28d874b9f7SLuca Ceresoli		regulator-min-microvolt = <1800000>;
29d874b9f7SLuca Ceresoli		regulator-max-microvolt = <1800000>;
30d874b9f7SLuca Ceresoli	};
31d874b9f7SLuca Ceresoli
32d874b9f7SLuca Ceresoli	sound {
33d874b9f7SLuca Ceresoli		compatible = "simple-audio-card";
34d874b9f7SLuca Ceresoli		simple-audio-card,name = "sgtl5000-audio";
35d874b9f7SLuca Ceresoli		simple-audio-card,format = "i2s";
36d874b9f7SLuca Ceresoli		simple-audio-card,frame-master = <&codec_dai>;
37d874b9f7SLuca Ceresoli		simple-audio-card,bitclock-master = <&codec_dai>;
38d874b9f7SLuca Ceresoli
39d874b9f7SLuca Ceresoli		simple-audio-card,cpu {
40d874b9f7SLuca Ceresoli			sound-dai = <&sai2>;
41d874b9f7SLuca Ceresoli		};
42d874b9f7SLuca Ceresoli
43d874b9f7SLuca Ceresoli		codec_dai: simple-audio-card,codec {
44d874b9f7SLuca Ceresoli			sound-dai = <&sgtl5000>;
45d874b9f7SLuca Ceresoli		};
46d874b9f7SLuca Ceresoli	};
47d874b9f7SLuca Ceresoli};
48d874b9f7SLuca Ceresoli
49*be3216d6SLuca Ceresoli&hdmi_pvi {
50*be3216d6SLuca Ceresoli	status = "okay";
51*be3216d6SLuca Ceresoli};
52*be3216d6SLuca Ceresoli
53*be3216d6SLuca Ceresoli&hdmi_tx {
54*be3216d6SLuca Ceresoli	pinctrl-names = "default";
55*be3216d6SLuca Ceresoli	pinctrl-0 = <&pinctrl_hdmi>;
56*be3216d6SLuca Ceresoli	status = "okay";
57*be3216d6SLuca Ceresoli};
58*be3216d6SLuca Ceresoli
59*be3216d6SLuca Ceresoli&hdmi_tx_phy {
60*be3216d6SLuca Ceresoli	status = "okay";
61*be3216d6SLuca Ceresoli};
62*be3216d6SLuca Ceresoli
63*be3216d6SLuca Ceresoli&lcdif3 {
64*be3216d6SLuca Ceresoli	status = "okay";
65*be3216d6SLuca Ceresoli};
66*be3216d6SLuca Ceresoli
67d874b9f7SLuca Ceresoli&i2c1 {
68d874b9f7SLuca Ceresoli	sgtl5000: audio-codec@a {
69d874b9f7SLuca Ceresoli		compatible = "fsl,sgtl5000";
70d874b9f7SLuca Ceresoli		reg = <0x0a>;
71d874b9f7SLuca Ceresoli
72d874b9f7SLuca Ceresoli		assigned-clocks = <&clk IMX8MP_CLK_CLKOUT1_SEL>;
73d874b9f7SLuca Ceresoli		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
74d874b9f7SLuca Ceresoli		assigned-clock-rates = <24000000>;
75d874b9f7SLuca Ceresoli		clocks = <&clk IMX8MP_CLK_CLKOUT1>;
76d874b9f7SLuca Ceresoli		#sound-dai-cells = <0>;
77d874b9f7SLuca Ceresoli
78d874b9f7SLuca Ceresoli		VDDA-supply = <&reg_vcc_3v3_audio>;
79d874b9f7SLuca Ceresoli		VDDD-supply = <&reg_vcc_1v8_audio>;
80d874b9f7SLuca Ceresoli		VDDIO-supply = <&reg_vcc_1v8_audio>;
81d874b9f7SLuca Ceresoli	};
82d874b9f7SLuca Ceresoli};
83d874b9f7SLuca Ceresoli
84d874b9f7SLuca Ceresoli/* I2S-0 = sai2 */
85d874b9f7SLuca Ceresoli&sai2 {
86d874b9f7SLuca Ceresoli	pinctrl-names = "default";
87d874b9f7SLuca Ceresoli	pinctrl-0 = <&pinctrl_sai2>;
88d874b9f7SLuca Ceresoli
89d874b9f7SLuca Ceresoli	assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
90d874b9f7SLuca Ceresoli	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
91d874b9f7SLuca Ceresoli	assigned-clock-rates = <12288000>;
92d874b9f7SLuca Ceresoli
93d874b9f7SLuca Ceresoli	fsl,sai-mclk-direction-output;
94d874b9f7SLuca Ceresoli	status = "okay";
95f703b602SMartyn Welch};
96f703b602SMartyn Welch
97f703b602SMartyn Welch&flexcan1 {
98f703b602SMartyn Welch	status = "okay";
99f703b602SMartyn Welch};
100f703b602SMartyn Welch
101f703b602SMartyn Welch&flexcan2 {
102f703b602SMartyn Welch	status = "okay";
103f703b602SMartyn Welch};
104f703b602SMartyn Welch
105f703b602SMartyn Welch&usdhc2 {
106f703b602SMartyn Welch	no-1-8-v;
107f703b602SMartyn Welch};
108f703b602SMartyn Welch
109f703b602SMartyn Welch&iomuxc {
110f703b602SMartyn Welch	pinctrl-names = "default";
111f703b602SMartyn Welch	pinctrl-0 = <&pinctrl_smarc_gpio>;
112f703b602SMartyn Welch
113*be3216d6SLuca Ceresoli	pinctrl_hdmi: hdmigrp {
114*be3216d6SLuca Ceresoli		fsl,pins = <
115*be3216d6SLuca Ceresoli			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c2
116*be3216d6SLuca Ceresoli			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c2
117*be3216d6SLuca Ceresoli			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x10
118*be3216d6SLuca Ceresoli			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x10
119*be3216d6SLuca Ceresoli		>;
120*be3216d6SLuca Ceresoli	};
121*be3216d6SLuca Ceresoli
122d874b9f7SLuca Ceresoli	pinctrl_sai2: sai2grp {
123d874b9f7SLuca Ceresoli		fsl,pins = <
124d874b9f7SLuca Ceresoli			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC   0xd6
125d874b9f7SLuca Ceresoli			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK    0xd6
126d874b9f7SLuca Ceresoli			MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
127d874b9f7SLuca Ceresoli			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
128d874b9f7SLuca Ceresoli		>;
129d874b9f7SLuca Ceresoli	};
130d874b9f7SLuca Ceresoli
131f703b602SMartyn Welch	pinctrl_smarc_gpio: smarcgpiosgrp {
132f703b602SMartyn Welch		fsl,pins =
133f703b602SMartyn Welch			<MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x19>, /* GPIO0 */
134f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01	0x19>, /* GPIO1 */
135f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02	0x19>, /* GPIO2 */
136f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03	0x19>, /* GPIO3 */
137f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x19>, /* GPIO4 */
138f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x19>, /* GPIO5 */
139f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x19>, /* GPIO6 */
140f703b602SMartyn Welch			<MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10	0x19>, /* GPIO7 */
141f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x19>, /* GPIO8 */
142f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21	0x19>, /* GPIO9 */
143f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22	0x19>, /* GPIO10 */
144f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28	0x19>, /* GPIO11 */
145f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x19>, /* GPIO12 */
146f703b602SMartyn Welch			<MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00	0x19>; /* GPIO13 */
147f703b602SMartyn Welch	};
148f703b602SMartyn Welch};
149