1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright (C) 2024 Kontron Electronics GmbH 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include "imx8mp-kontron-osm-s.dtsi" 8 9/ { 10 model = "Kontron SMARC i.MX8MP"; 11 compatible = "kontron,imx8mp-smarc", "kontron,imx8mp-osm-s", "fsl,imx8mp"; 12 13 leds { 14 compatible = "gpio-leds"; 15 16 led1 { 17 label = "led1"; 18 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 19 linux,default-trigger = "heartbeat"; 20 }; 21 }; 22}; 23 24&ecspi1 { 25 status = "okay"; 26 27 tpm@0 { 28 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 29 reg = <0>; 30 spi-max-frequency = <18500000>; 31 }; 32}; 33 34&eqos { /* Second ethernet (OSM-S ETH_B) */ 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_eqos_rgmii>; 37 phy-mode = "rgmii-id"; 38 phy-handle = <ðphy1>; 39 40 mdio { 41 compatible = "snps,dwmac-mdio"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 ethphy1: ethernet-phy@1 { 46 compatible = "ethernet-phy-id4f51.e91b"; 47 reg = <1>; 48 pinctrl-0 = <&pinctrl_ethphy1>; 49 pinctrl-names = "default"; 50 reset-assert-us = <10000>; 51 reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 52 }; 53 }; 54}; 55 56&fec { /* First ethernet (OSM-S ETH_A) */ 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_enet_rgmii>; 59 phy-connection-type = "rgmii-id"; 60 phy-handle = <ðphy0>; 61 62 mdio { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 ethphy0: ethernet-phy@1 { 67 compatible = "ethernet-phy-id4f51.e91b"; 68 reg = <1>; 69 pinctrl-0 = <&pinctrl_ethphy0>; 70 pinctrl-names = "default"; 71 reset-assert-us = <10000>; 72 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 73 }; 74 }; 75}; 76 77/* 78 * Rename SoM signals according to SMARC module usage: 79 * GPIO_A_2 -> GPIO0 80 * GPIO_A_3 -> GPIO1 81 * GPIO_A_4 -> GPIO2 82 * GPIO_A_5 -> GPIO3 83 * USB_B_EN -> n.a. 84 * USB_B_ID -> n.a. 85 * USB_B_OC -> n.a. 86 */ 87&gpio1 { 88 gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "", 89 "", "GPIO0", "GPIO1", "GPIO2", 90 "GPIO3", "", "USB_A_ID", "", 91 "USB_A_EN", "USB_A_OC","CAM_MCK", "", 92 "ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2", 93 "ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK", 94 "ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1", 95 "ETH_B_RXD2", "ETH_B_RXD3"; 96}; 97 98/* 99 * Rename SoM signals according to SMARC module usage: 100 * SDIO_A_CD -> SDIO_CD 101 * SDIO_A_CLK -> SDIO_CK 102 * SDIO_A_CMD -> SDIO_CMD 103 * SDIO_A_D0 -> SDIO_D0 104 * SDIO_A_D1 -> SDIO_D1 105 * SDIO_A_D2 -> SDIO_D2 106 * SDIO_A_D3 -> SDIO_D3 107 * SDIO_A_PWR_EN -> SDIO_PWR_EN 108 * SDIO_A_WP -> SDIO_WP 109 */ 110&gpio2 { 111 gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", 112 "SDIO_CD", "SDIO_CK", "SDIO_CMD", "SDIO_D0", 113 "SDIO_D1", "SDIO_D2", "SDIO_D3", "SDIO_PWR_EN", 114 "SDIO_WP"; 115}; 116 117/* 118 * Rename SoM signals according to SMARC module usage: 119 * PCIE_CLKREQ -> PCIE_A_CKREQ 120 * PCIE_A_PERST -> PCIE_A_RST 121 * SDIO_B_D5 -> n.a. 122 * SDIO_B_D6 -> n.a. 123 * SDIO_B_D7 -> n.a. 124 * SPI_A_WP -> n.a. 125 * SPI_A_HOLD -> n.a. 126 * UART_B_RTS -> SER2_RTS 127 * UART_B_CTS -> SER2_CTS 128 * SDIO_B_D0 -> GPIO8 129 * SDIO_B_D1 -> GPIO9 130 * SDIO_B_D2 -> GPIO10 131 * SDIO_B_D3 -> GPIO11 132 * SDIO_B_WP -> n.a. 133 * SDIO_B_D4 -> n.a. 134 * PCIE_SM_ALERT -> SMB_ALERT 135 * SDIO_B_CLK -> GPIO6 136 * SDIO_B_CMD -> GPIO7 137 * GPIO_B_0 -> LCD0_BKLT_EN 138 * GPIO_B_1 -> LCD1_BKLT_EN 139 * BOOT_SEL0 -> BOOT_SEL2 140 * SDIO_B_CD -> n.a. 141 * SDIO_B_PWR_EN -> n.a. 142 * HDMI_CEC -> n.a. 143 * SDIO_B_PWR_EN -> n.a. 144 */ 145&gpio3 { 146 pinctrl-0 = <&pinctrl_gpio3>, <&pinctrl_gpio3_smarc>; 147 gpio-line-names = "PCIE_WAKE", "PCIE_A_CKREQ", "PCIE_A_RST", "", 148 "", "", "", "", 149 "SER2_RTS", "SER2_CTS", "GPIO8", "GPIO9", 150 "GPIO10", "GPIO11", "", "", 151 "SMB_ALERT", "GPIO6", "GPIO7", "LCD0_BKLT_EN", 152 "LCD1_BKLT_EN", "", "BOOT_SEL2", "BOOT_SEL1", 153 "", "", "", "", 154 "", "HDMI_HPD"; 155}; 156 157/* 158 * Rename SoM signals according to SMARC module usage: 159 * GPIO_B_5 -> n.a. 160 * GPIO_B_6 -> n.a. 161 * GPIO_B_7 -> n.a. 162 * GPIO_C_0 -> LED 163 * GPIO_B_3 -> ETH2_INT 164 * GPIO_B_4 -> USB_HUB_RST 165 * GPIO_B_2 -> ETH1_INT 166 * GPIO_A_6 -> GPIO4 167 * CAN_A_TX -> CAN0_TX 168 * UART_A_CTS -> SER0_CTS 169 * UART_A_RTS -> SER0_RTS 170 * CAN_A_RX -> CAN0_RX 171 * CAN_B_TX -> CAN1_TX 172 * CAN_B_RX -> CAN1_RX 173 * GPIO_A_7 -> TEST 174 * I2S_A_DATA_IN -> I2S0_SDIN 175 * I2S_LRCLK -> I2S0_LRCK 176 */ 177&gpio4 { 178 gpio-line-names = "", "", "", "LED", 179 "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", 180 "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", 181 "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", 182 "ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH2_INT", "USB_HUB_RST", 183 "ETH1_INT", "GPIO4", "CAN0_TX", "SER0_CTS", 184 "SER0_RTS", "CAN0_RX", "CAN1_TX", "CAN1_RX", 185 "TEST", "CARRIER_PWR_EN", "I2S0_SDIN", "I2S0_LRCK"; 186}; 187 188/* 189 * Rename SoM signals according to SMARC module usage: 190 * I2S_BITCLK -> I2S0_CK 191 * I2S_A_DATA_OUT -> I2S0_SDOUT 192 * I2S_MCLK -> AUDIO_MCK 193 * PWM_2 -> GPIO5 194 * PWM_1 -> LCD1_BKLT_PWM 195 * PWM_0 -> LCD0_BKLT_PWM 196 * SPI_A_SCK -> SPI0_CK 197 * SPI_A_SDO -> SPI0_DO 198 * SPI_A_SDI -> SPI0_DIN 199 * SPI_A_CS0 -> SPI0_CS0 200 * SPI_B_SCK -> ESPI_CK 201 * SPI_B_SDO -> ESPI_IO_0 202 * SPI_B_SDI -> ESPI_IO_1 203 * SPI_B_CS0 -> ESPI_CS0 204 * I2C_A_SCL -> I2C_PM_CK 205 * I2C_A_SDA -> I2C_PM_DAT 206 * I2C_B_SCL -> I2C_GP_CK 207 * I2C_B_SDA -> I2C_GP_DAT 208 * PCIE_SMCLK -> HDMI_CTRL_CK 209 * PCIE_SMDAT -> HDMI_CTRL_DAT 210 * I2C_CAM_SCL -> I2C_CAM1_CK 211 * I2C_CAM_SDA -> I2C_CAM1_DAT 212 * UART_A_RX -> SER0_RX 213 * UART_A_TX -> SER0_TX 214 * UART_C_RX -> SER3_RX 215 * UART_C_TX -> SER3_TX 216 * UART_CON_RX -> SER1_RX 217 * UART_CON_TX -> SER1_TX 218 * UART_B_RX -> SER2_RX 219 * UART_B_TX -> SER2_TX 220 */ 221&gpio5 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_gpio5_smarc>; 224 gpio-line-names = "I2S0_CK", "I2S0_SDOUT", "AUDIO_MCK", "GPIO5", 225 "LCD1_BKLT_PWM", "LCD0_BKLT_PWM", "SPI0_CK", "SPI0_DO", 226 "SPI0_DIN", "SPI0_CS0", "ESPI_CK", "ESPI_IO_0", 227 "ESPI_IO_1", "ESPI_CS0", "I2C_PM_CK", "I2C_PM_DAT", 228 "I2C_GP_CK", "I2C_GP_DAT", "HDMI_CTRL_CK", "HDMI_CTRL_DAT", 229 "I2C_CAM1_CK", "I2C_CAM1_DAT", "SER0_RX", "SER0_TX", 230 "SER3_RX", "SER3_TX", "SER1_RX", "SER1_TX", 231 "SER2_RX", "SER2_TX"; 232}; 233 234&usb_dwc3_1 { 235 dr_mode = "host"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 239 usb-hub@1 { 240 compatible = "usb424,2514"; 241 reg = <1>; 242 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 243 }; 244}; 245 246&usb3_1 { 247 fsl,disable-port-power-control; 248 fsl,permanently-attached; 249}; 250 251&iomuxc { 252 pinctrl_ethphy0: ethphy0grp { 253 fsl,pins = < 254 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46 255 >; 256 }; 257 258 pinctrl_ethphy1: ethphy1grp { 259 fsl,pins = < 260 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46 261 >; 262 }; 263 264 pinctrl_gpio3_smarc: gpio3smarcgrp { 265 fsl,pins = < 266 MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x1d0 /* SMARC GPIO8 */ 267 MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x1d0 /* SMARC GPIO9 */ 268 MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x1d0 /* SMARC GPIO10 */ 269 MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x1d0 /* SMARC GPIO11 */ 270 MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x190 /* SMARC GPIO6 */ 271 MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x1d0 /* SMARC GPIO7 */ 272 >; 273 }; 274 275 pinctrl_gpio5_smarc: gpio5smarcgrp { 276 fsl,pins = < 277 MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1d0 /* SMARC GPIO5 */ 278 >; 279 }; 280}; 281