xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mp-kontron-osm-s.dtsi"
9
10/ {
11	model = "Kontron BL i.MX8MP OSM-S";
12	compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";
13
14	aliases {
15		ethernet0 = &fec;
16		ethernet1 = &eqos;
17	};
18
19	extcon_usbc: usbc {
20		compatible = "linux,extcon-usb-gpio";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_usb1_id>;
23		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
24	};
25
26	leds {
27		compatible = "gpio-leds";
28
29		led1 {
30			label = "led1";
31			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
32			linux,default-trigger = "heartbeat";
33		};
34	};
35
36	pwm-beeper {
37		compatible = "pwm-beeper";
38		pwms = <&pwm2 0 5000 0>;
39	};
40
41	reg_vcc_panel: regulator-vcc-panel {
42		compatible = "regulator-fixed";
43		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
44		enable-active-high;
45		regulator-max-microvolt = <3300000>;
46		regulator-min-microvolt = <3300000>;
47		regulator-name = "VCC_PANEL";
48	};
49};
50
51&ecspi2 {
52	status = "okay";
53
54	eeram@0 {
55		compatible = "microchip,48l640";
56		reg = <0>;
57		spi-max-frequency = <20000000>;
58	};
59};
60
61&eqos {	/* Second ethernet (OSM-S ETH_B) */
62	pinctrl-names = "default";
63	pinctrl-0 = <&pinctrl_eqos_rgmii>;
64	phy-mode = "rgmii-id";
65	phy-handle = <&ethphy1>;
66	status = "okay";
67
68	mdio {
69		compatible = "snps,dwmac-mdio";
70		#address-cells = <1>;
71		#size-cells = <0>;
72
73		ethphy1: ethernet-phy@1 {
74			compatible = "ethernet-phy-id4f51.e91b";
75			reg = <1>;
76			pinctrl-0 = <&pinctrl_ethphy1>;
77			pinctrl-names = "default";
78			reset-assert-us = <10000>;
79			reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
80		};
81	};
82};
83
84&fec { /* First ethernet (OSM-S ETH_A) */
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_enet_rgmii>;
87	phy-connection-type = "rgmii-id";
88	phy-handle = <&ethphy0>;
89	status = "okay";
90
91	mdio {
92		#address-cells = <1>;
93		#size-cells = <0>;
94
95		ethphy0: ethernet-phy@1 {
96			compatible = "ethernet-phy-id4f51.e91b";
97			reg = <1>;
98			pinctrl-0 = <&pinctrl_ethphy0>;
99			pinctrl-names = "default";
100			reset-assert-us = <10000>;
101			reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
102		};
103	};
104};
105
106&flexcan1 {
107	status = "okay";
108};
109
110/*
111 * Rename SoM signals according to board usage:
112 *   SDIO_A_PWR_EN -> CAN_ADDR2
113 *   SDIO_A_WP     -> CAN_ADDR3
114 */
115&gpio2 {
116	pinctrl-names = "default";
117	pinctrl-0 = <&pinctrl_gpio2>;
118	gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
119			  "SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
120			  "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",
121			  "CAN_ADDR3";
122};
123
124/*
125 * Rename SoM signals according to board usage:
126 *   GPIO_B_0      -> IO_EXP_INT
127 *   GPIO_B_1      -> IO_EXP_RST
128 */
129&gpio3 {
130	gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
131			  "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
132			  "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
133			  "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
134			  "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",
135			  "IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",
136			  "", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
137			  "HDMI_CEC", "HDMI_HPD";
138};
139
140/*
141 * Rename SoM signals according to board usage and remove labels for unsed pins:
142 *   GPIO_A_6      -> TFT_RESET
143 *   GPIO_A_7      -> TFT_STBY
144 *   GPIO_B_3      -> CSI_ENABLE
145 *   GPIO_B_2      -> USB_HUB_RST
146 */
147&gpio4 {
148	gpio-line-names = "", "", "", "",
149			  "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
150			  "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
151			  "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
152			  "ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",
153			  "USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",
154			  "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
155			  "TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
156};
157
158/*
159 * Rename SoM signals according to board usage:
160 *   SPI_A_SDI	-> CAN_ADDR0
161 *   SPI_A_SDO	-> CAN_ADDR1
162 */
163&gpio5 {
164	pinctrl-names = "default";
165	pinctrl-0 = <&pinctrl_gpio5>;
166	gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
167			  "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
168			  "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
169			  "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
170			  "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
171			  "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
172			  "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
173			  "UART_B_RX", "UART_B_TX";
174};
175
176&hdmi_pvi {
177	status = "okay";
178};
179
180&hdmi_tx {
181	pinctrl-names = "default";
182	pinctrl-0 = <&pinctrl_hdmi>;
183	ddc-i2c-bus = <&i2c2>;
184	status = "okay";
185};
186
187&hdmi_tx_phy {
188	status = "okay";
189};
190
191&i2c1 {
192	status = "okay";
193
194	gpio_expander_dio: io-expander@20 {
195		compatible = "ti,tca6408";
196		reg = <0x20>;
197		gpio-controller;
198		#gpio-cells = <2>;
199		gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",
200				  "DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";
201		interrupt-parent = <&gpio3>;
202		interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
203		reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
204	};
205};
206
207&i2c2 {
208	status = "okay";
209};
210
211&i2c4 {
212	status = "okay";
213};
214
215&lcdif3 {
216	status = "okay";
217};
218
219&pwm2 {
220	status = "okay";
221};
222
223&reg_usdhc2_vcc {
224	status = "disabled";
225};
226
227&snvs_pwrkey {
228	status = "okay";
229};
230
231&uart1 {
232	uart-has-rtscts;
233	status = "okay";
234};
235
236&uart4 {
237	linux,rs485-enabled-at-boot-time;
238	uart-has-rtscts;
239	status = "okay";
240};
241
242&usb_dwc3_0 {
243	adp-disable;
244	hnp-disable;
245	srp-disable;
246	dr_mode = "otg";
247	extcon = <&extcon_usbc>;
248	usb-role-switch;
249	status = "okay";
250};
251
252&usb_dwc3_1 {
253	#address-cells = <1>;
254	#size-cells = <0>;
255	dr_mode = "host";
256	status = "okay";
257
258	usb-hub@1 {
259		compatible = "usb424,2514";
260		reg = <1>;
261		reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
262	};
263};
264
265&usb3_0 {
266	status = "okay";
267};
268
269&usb3_1 {
270	fsl,disable-port-power-control;
271	fsl,permanently-attached;
272	status = "okay";
273};
274
275&usb3_phy0 {
276	vbus-supply = <&reg_usb1_vbus>;
277	status = "okay";
278};
279
280&usb3_phy1 {
281	status = "okay";
282};
283
284&usdhc2 {
285	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
286	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
287	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
288	vmmc-supply = <&reg_vdd_3v3>;
289	status = "okay";
290};
291
292&iomuxc {
293	pinctrl_ethphy0: ethphy0grp {
294		fsl,pins = <
295			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x46
296		>;
297	};
298
299	pinctrl_ethphy1: ethphy1grp {
300		fsl,pins = <
301			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x46
302		>;
303	};
304
305	pinctrl_gpio2: gpio2grp {
306		fsl,pins = <
307			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x46
308			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x46
309		>;
310	};
311
312	pinctrl_gpio5: gpio5grp {
313		fsl,pins = <
314			MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07		0x46 /* CAN_ADR0 */
315			MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08		0x46 /* CAN_ADR1 */
316		>;
317	};
318};
319