1*2a222aa2SJosua Mayer// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*2a222aa2SJosua Mayer/* 3*2a222aa2SJosua Mayer * Copyright 2025 Josua Mayer <josua@solid-run.com> 4*2a222aa2SJosua Mayer */ 5*2a222aa2SJosua Mayer 6*2a222aa2SJosua Mayer/dts-v1/; 7*2a222aa2SJosua Mayer 8*2a222aa2SJosua Mayer#include <dt-bindings/phy/phy-imx8-pcie.h> 9*2a222aa2SJosua Mayer 10*2a222aa2SJosua Mayer#include "imx8mp-sr-som.dtsi" 11*2a222aa2SJosua Mayer#include "imx8mp-hummingboard-pulse-codec.dtsi" 12*2a222aa2SJosua Mayer#include "imx8mp-hummingboard-pulse-common.dtsi" 13*2a222aa2SJosua Mayer#include "imx8mp-hummingboard-pulse-hdmi.dtsi" 14*2a222aa2SJosua Mayer#include "imx8mp-hummingboard-pulse-m2con.dtsi" 15*2a222aa2SJosua Mayer#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" 16*2a222aa2SJosua Mayer 17*2a222aa2SJosua Mayer/ { 18*2a222aa2SJosua Mayer model = "SolidRun i.MX8MP HummingBoard Pulse"; 19*2a222aa2SJosua Mayer compatible = "solidrun,imx8mp-hummingboard-pulse", 20*2a222aa2SJosua Mayer "solidrun,imx8mp-sr-som", "fsl,imx8mp"; 21*2a222aa2SJosua Mayer 22*2a222aa2SJosua Mayer aliases { 23*2a222aa2SJosua Mayer ethernet0 = &eqos; 24*2a222aa2SJosua Mayer ethernet1 = &pcie_eth; 25*2a222aa2SJosua Mayer }; 26*2a222aa2SJosua Mayer}; 27*2a222aa2SJosua Mayer 28*2a222aa2SJosua Mayer&fec { 29*2a222aa2SJosua Mayer /* this board does not use second phy / ethernet on SoM */ 30*2a222aa2SJosua Mayer status = "disabled"; 31*2a222aa2SJosua Mayer}; 32*2a222aa2SJosua Mayer 33*2a222aa2SJosua Mayer&gpio1 { 34*2a222aa2SJosua Mayer pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>; 35*2a222aa2SJosua Mayer pinctrl-names = "default"; 36*2a222aa2SJosua Mayer 37*2a222aa2SJosua Mayer m2-reset-hog { 38*2a222aa2SJosua Mayer gpio-hog; 39*2a222aa2SJosua Mayer gpios = <6 GPIO_ACTIVE_LOW>; 40*2a222aa2SJosua Mayer output-low; 41*2a222aa2SJosua Mayer line-name = "m2-reset"; 42*2a222aa2SJosua Mayer }; 43*2a222aa2SJosua Mayer}; 44*2a222aa2SJosua Mayer 45*2a222aa2SJosua Mayer&iomuxc { 46*2a222aa2SJosua Mayer pinctrl-names = "default"; 47*2a222aa2SJosua Mayer pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>, 48*2a222aa2SJosua Mayer <&m2_wwan_wake_pins>; 49*2a222aa2SJosua Mayer 50*2a222aa2SJosua Mayer pcie_eth_pins: pinctrl-pcie-eth-grp { 51*2a222aa2SJosua Mayer fsl,pins = < 52*2a222aa2SJosua Mayer MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 53*2a222aa2SJosua Mayer >; 54*2a222aa2SJosua Mayer }; 55*2a222aa2SJosua Mayer}; 56*2a222aa2SJosua Mayer 57*2a222aa2SJosua Mayer&pcie { 58*2a222aa2SJosua Mayer pinctrl-0 = <&pcie_eth_pins>; 59*2a222aa2SJosua Mayer pinctrl-names = "default"; 60*2a222aa2SJosua Mayer reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; 61*2a222aa2SJosua Mayer status = "okay"; 62*2a222aa2SJosua Mayer 63*2a222aa2SJosua Mayer root@0,0 { 64*2a222aa2SJosua Mayer compatible = "pci16c3,abcd"; 65*2a222aa2SJosua Mayer reg = <0x00000000 0 0 0 0>; 66*2a222aa2SJosua Mayer #address-cells = <3>; 67*2a222aa2SJosua Mayer #size-cells = <2>; 68*2a222aa2SJosua Mayer 69*2a222aa2SJosua Mayer /* Intel i210 */ 70*2a222aa2SJosua Mayer pcie_eth: ethernet@1,0 { 71*2a222aa2SJosua Mayer compatible = "pci8086,157b"; 72*2a222aa2SJosua Mayer reg = <0x00010000 0 0 0 0>; 73*2a222aa2SJosua Mayer }; 74*2a222aa2SJosua Mayer }; 75*2a222aa2SJosua Mayer}; 76*2a222aa2SJosua Mayer 77*2a222aa2SJosua Mayer&pcie_phy { 78*2a222aa2SJosua Mayer clocks = <&hsio_blk_ctrl>; 79*2a222aa2SJosua Mayer clock-names = "ref"; 80*2a222aa2SJosua Mayer fsl,clkreq-unsupported; 81*2a222aa2SJosua Mayer fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 82*2a222aa2SJosua Mayer status = "okay"; 83*2a222aa2SJosua Mayer}; 84