1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 hdmi-connector { 20 compatible = "hdmi-connector"; 21 label = "hdmi"; 22 type = "a"; 23 24 port { 25 hdmi_connector_in: endpoint { 26 remote-endpoint = <&adv7535_out>; 27 }; 28 }; 29 }; 30 31 gpio-leds { 32 compatible = "gpio-leds"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_led>; 35 36 status { 37 label = "yellow:status"; 38 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 39 default-state = "on"; 40 }; 41 }; 42 43 memory@40000000 { 44 device_type = "memory"; 45 reg = <0x0 0x40000000 0 0xc0000000>, 46 <0x1 0x00000000 0 0xc0000000>; 47 }; 48 49 pcie0_refclk: pcie0-refclk { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <100000000>; 53 }; 54 55 reg_audio_pwr: regulator-audio-pwr { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 59 regulator-name = "audio-pwr"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 reg_can1_stby: regulator-can1-stby { 67 compatible = "regulator-fixed"; 68 regulator-name = "can1-stby"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_flexcan1_reg>; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 74 enable-active-high; 75 }; 76 77 reg_can2_stby: regulator-can2-stby { 78 compatible = "regulator-fixed"; 79 regulator-name = "can2-stby"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_flexcan2_reg>; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 }; 87 88 reg_pcie0: regulator-pcie { 89 compatible = "regulator-fixed"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_pcie0_reg>; 92 regulator-name = "MPCIE_3V3"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 }; 98 99 reg_usdhc2_vmmc: regulator-usdhc2 { 100 compatible = "regulator-fixed"; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 103 regulator-name = "VSD_3V3"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 reg_vext_3v3: regulator-vext-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "VEXT_3V3"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 }; 116 117 sound { 118 compatible = "simple-audio-card"; 119 simple-audio-card,name = "wm8960-audio"; 120 simple-audio-card,format = "i2s"; 121 simple-audio-card,frame-master = <&cpudai>; 122 simple-audio-card,bitclock-master = <&cpudai>; 123 simple-audio-card,widgets = 124 "Headphone", "Headphone Jack", 125 "Speaker", "External Speaker", 126 "Microphone", "Mic Jack"; 127 simple-audio-card,routing = 128 "Headphone Jack", "HP_L", 129 "Headphone Jack", "HP_R", 130 "External Speaker", "SPK_LP", 131 "External Speaker", "SPK_LN", 132 "External Speaker", "SPK_RP", 133 "External Speaker", "SPK_RN", 134 "LINPUT1", "Mic Jack", 135 "LINPUT3", "Mic Jack", 136 "Mic Jack", "MICB"; 137 138 cpudai: simple-audio-card,cpu { 139 sound-dai = <&sai3>; 140 }; 141 142 simple-audio-card,codec { 143 sound-dai = <&wm8960>; 144 }; 145 146 }; 147 148 reserved-memory { 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 dsp_vdev0vring0: vdev0vring0@942f0000 { 154 reg = <0 0x942f0000 0 0x8000>; 155 no-map; 156 }; 157 158 dsp_vdev0vring1: vdev0vring1@942f8000 { 159 reg = <0 0x942f8000 0 0x8000>; 160 no-map; 161 }; 162 163 dsp_vdev0buffer: vdev0buffer@94300000 { 164 compatible = "shared-dma-pool"; 165 reg = <0 0x94300000 0 0x100000>; 166 no-map; 167 }; 168 }; 169}; 170 171&flexspi { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_flexspi0>; 174 status = "okay"; 175 176 flash@0 { 177 compatible = "jedec,spi-nor"; 178 reg = <0>; 179 spi-max-frequency = <80000000>; 180 spi-tx-bus-width = <1>; 181 spi-rx-bus-width = <4>; 182 }; 183}; 184 185&A53_0 { 186 cpu-supply = <®_arm>; 187}; 188 189&A53_1 { 190 cpu-supply = <®_arm>; 191}; 192 193&A53_2 { 194 cpu-supply = <®_arm>; 195}; 196 197&A53_3 { 198 cpu-supply = <®_arm>; 199}; 200 201&eqos { 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_eqos>; 204 phy-mode = "rgmii-id"; 205 phy-handle = <ðphy0>; 206 snps,force_thresh_dma_mode; 207 snps,mtl-tx-config = <&mtl_tx_setup>; 208 snps,mtl-rx-config = <&mtl_rx_setup>; 209 status = "okay"; 210 211 mdio { 212 compatible = "snps,dwmac-mdio"; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 216 ethphy0: ethernet-phy@1 { 217 compatible = "ethernet-phy-ieee802.3-c22"; 218 reg = <1>; 219 eee-broken-1000t; 220 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 221 reset-assert-us = <10000>; 222 reset-deassert-us = <80000>; 223 realtek,clkout-disable; 224 }; 225 }; 226 227 mtl_tx_setup: tx-queues-config { 228 snps,tx-queues-to-use = <5>; 229 snps,tx-sched-sp; 230 231 queue0 { 232 snps,dcb-algorithm; 233 snps,priority = <0x1>; 234 }; 235 236 queue1 { 237 snps,dcb-algorithm; 238 snps,priority = <0x2>; 239 }; 240 241 queue2 { 242 snps,dcb-algorithm; 243 snps,priority = <0x4>; 244 }; 245 246 queue3 { 247 snps,dcb-algorithm; 248 snps,priority = <0x8>; 249 }; 250 251 queue4 { 252 snps,dcb-algorithm; 253 snps,priority = <0xf0>; 254 }; 255 }; 256 257 mtl_rx_setup: rx-queues-config { 258 snps,rx-queues-to-use = <5>; 259 snps,rx-sched-sp; 260 261 queue0 { 262 snps,dcb-algorithm; 263 snps,priority = <0x1>; 264 snps,map-to-dma-channel = <0>; 265 }; 266 267 queue1 { 268 snps,dcb-algorithm; 269 snps,priority = <0x2>; 270 snps,map-to-dma-channel = <1>; 271 }; 272 273 queue2 { 274 snps,dcb-algorithm; 275 snps,priority = <0x4>; 276 snps,map-to-dma-channel = <2>; 277 }; 278 279 queue3 { 280 snps,dcb-algorithm; 281 snps,priority = <0x8>; 282 snps,map-to-dma-channel = <3>; 283 }; 284 285 queue4 { 286 snps,dcb-algorithm; 287 snps,priority = <0xf0>; 288 snps,map-to-dma-channel = <4>; 289 }; 290 }; 291}; 292 293&fec { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_fec>; 296 phy-mode = "rgmii-id"; 297 phy-handle = <ðphy1>; 298 fsl,magic-packet; 299 status = "okay"; 300 301 mdio { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 ethphy1: ethernet-phy@1 { 306 compatible = "ethernet-phy-ieee802.3-c22"; 307 reg = <1>; 308 eee-broken-1000t; 309 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 310 reset-assert-us = <10000>; 311 reset-deassert-us = <80000>; 312 realtek,clkout-disable; 313 }; 314 }; 315}; 316 317&flexcan1 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_flexcan1>; 320 xceiver-supply = <®_can1_stby>; 321 status = "okay"; 322}; 323 324&flexcan2 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_flexcan2>; 327 xceiver-supply = <®_can2_stby>; 328 status = "disabled";/* can2 pin conflict with pdm */ 329}; 330 331&i2c1 { 332 clock-frequency = <400000>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_i2c1>; 335 status = "okay"; 336 337 pmic@25 { 338 compatible = "nxp,pca9450c"; 339 reg = <0x25>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_pmic>; 342 interrupt-parent = <&gpio1>; 343 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 344 345 regulators { 346 BUCK1 { 347 regulator-name = "BUCK1"; 348 regulator-min-microvolt = <720000>; 349 regulator-max-microvolt = <1000000>; 350 regulator-boot-on; 351 regulator-always-on; 352 regulator-ramp-delay = <3125>; 353 }; 354 355 reg_arm: BUCK2 { 356 regulator-name = "BUCK2"; 357 regulator-min-microvolt = <720000>; 358 regulator-max-microvolt = <1025000>; 359 regulator-boot-on; 360 regulator-always-on; 361 regulator-ramp-delay = <3125>; 362 nxp,dvs-run-voltage = <950000>; 363 nxp,dvs-standby-voltage = <850000>; 364 }; 365 366 BUCK4 { 367 regulator-name = "BUCK4"; 368 regulator-min-microvolt = <3000000>; 369 regulator-max-microvolt = <3600000>; 370 regulator-boot-on; 371 regulator-always-on; 372 }; 373 374 reg_buck5: BUCK5 { 375 regulator-name = "BUCK5"; 376 regulator-min-microvolt = <1650000>; 377 regulator-max-microvolt = <1950000>; 378 regulator-boot-on; 379 regulator-always-on; 380 }; 381 382 BUCK6 { 383 regulator-name = "BUCK6"; 384 regulator-min-microvolt = <1045000>; 385 regulator-max-microvolt = <1155000>; 386 regulator-boot-on; 387 regulator-always-on; 388 }; 389 390 LDO1 { 391 regulator-name = "LDO1"; 392 regulator-min-microvolt = <1650000>; 393 regulator-max-microvolt = <1950000>; 394 regulator-boot-on; 395 regulator-always-on; 396 }; 397 398 LDO3 { 399 regulator-name = "LDO3"; 400 regulator-min-microvolt = <1710000>; 401 regulator-max-microvolt = <1890000>; 402 regulator-boot-on; 403 regulator-always-on; 404 }; 405 406 LDO5 { 407 regulator-name = "LDO5"; 408 regulator-min-microvolt = <1800000>; 409 regulator-max-microvolt = <3300000>; 410 regulator-boot-on; 411 regulator-always-on; 412 }; 413 }; 414 }; 415}; 416 417&i2c2 { 418 clock-frequency = <400000>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pinctrl_i2c2>; 421 status = "okay"; 422 423 hdmi@3d { 424 compatible = "adi,adv7535"; 425 reg = <0x3d>; 426 interrupt-parent = <&gpio1>; 427 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 428 adi,dsi-lanes = <4>; 429 avdd-supply = <®_buck5>; 430 dvdd-supply = <®_buck5>; 431 pvdd-supply = <®_buck5>; 432 a2vdd-supply = <®_buck5>; 433 v3p3-supply = <®_vext_3v3>; 434 v1p2-supply = <®_buck5>; 435 436 ports { 437 #address-cells = <1>; 438 #size-cells = <0>; 439 440 port@0 { 441 reg = <0>; 442 443 adv7535_in: endpoint { 444 remote-endpoint = <&dsi_out>; 445 }; 446 }; 447 448 port@1 { 449 reg = <1>; 450 451 adv7535_out: endpoint { 452 remote-endpoint = <&hdmi_connector_in>; 453 }; 454 }; 455 456 }; 457 }; 458}; 459 460&i2c3 { 461 clock-frequency = <400000>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_i2c3>; 464 status = "okay"; 465 466 wm8960: codec@1a { 467 compatible = "wlf,wm8960"; 468 reg = <0x1a>; 469 #sound-dai-cells = <0>; 470 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 471 clock-names = "mclk"; 472 wlf,shared-lrclk; 473 wlf,hp-cfg = <3 2 3>; 474 wlf,gpio-cfg = <1 3>; 475 SPKVDD1-supply = <®_audio_pwr>; 476 }; 477 478 pca6416: gpio@20 { 479 compatible = "ti,tca6416"; 480 reg = <0x20>; 481 gpio-controller; 482 #gpio-cells = <2>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pinctrl_pca6416_int>; 487 interrupt-parent = <&gpio1>; 488 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 489 gpio-line-names = "EXT_PWREN1", 490 "EXT_PWREN2", 491 "CAN1/I2C5_SEL", 492 "PDM/CAN2_SEL", 493 "FAN_EN", 494 "PWR_MEAS_IO1", 495 "PWR_MEAS_IO2", 496 "EXP_P0_7", 497 "EXP_P1_0", 498 "EXP_P1_1", 499 "EXP_P1_2", 500 "EXP_P1_3", 501 "EXP_P1_4", 502 "EXP_P1_5", 503 "EXP_P1_6", 504 "EXP_P1_7"; 505 }; 506}; 507 508/* I2C on expansion connector J22. */ 509&i2c5 { 510 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 511 pinctrl-names = "default"; 512 pinctrl-0 = <&pinctrl_i2c5>; 513 status = "disabled"; /* can1 pins conflict with i2c5 */ 514 515 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 516 * LOW: CAN1 (default, pull-down) 517 * HIGH: I2C5 518 * You need to set it to high to enable I2C5 (for example, add gpio-hog 519 * in pca6416 node). 520 */ 521}; 522 523&lcdif1 { 524 status = "okay"; 525}; 526 527&mipi_dsi { 528 samsung,esc-clock-frequency = <10000000>; 529 status = "okay"; 530 531 ports { 532 port@1 { 533 reg = <1>; 534 535 dsi_out: endpoint { 536 remote-endpoint = <&adv7535_in>; 537 data-lanes = <1 2 3 4>; 538 }; 539 }; 540 }; 541}; 542 543&pcie_phy { 544 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 545 clocks = <&pcie0_refclk>; 546 clock-names = "ref"; 547 status = "okay"; 548}; 549 550&pcie { 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_pcie0>; 553 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 554 vpcie-supply = <®_pcie0>; 555 status = "okay"; 556}; 557 558&pwm1 { 559 pinctrl-names = "default"; 560 pinctrl-0 = <&pinctrl_pwm1>; 561 status = "okay"; 562}; 563 564&pwm2 { 565 pinctrl-names = "default"; 566 pinctrl-0 = <&pinctrl_pwm2>; 567 status = "okay"; 568}; 569 570&pwm4 { 571 pinctrl-names = "default"; 572 pinctrl-0 = <&pinctrl_pwm4>; 573 status = "okay"; 574}; 575 576&sai3 { 577 pinctrl-names = "default"; 578 pinctrl-0 = <&pinctrl_sai3>; 579 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 580 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 581 assigned-clock-rates = <12288000>; 582 fsl,sai-mclk-direction-output; 583 status = "okay"; 584}; 585 586&snvs_pwrkey { 587 status = "okay"; 588}; 589 590&uart1 { /* BT */ 591 pinctrl-names = "default"; 592 pinctrl-0 = <&pinctrl_uart1>; 593 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 594 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 595 uart-has-rtscts; 596 status = "okay"; 597}; 598 599&uart2 { 600 /* console */ 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_uart2>; 603 status = "okay"; 604}; 605 606&usb3_phy1 { 607 status = "okay"; 608}; 609 610&usb3_1 { 611 status = "okay"; 612}; 613 614&usb_dwc3_1 { 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pinctrl_usb1_vbus>; 617 dr_mode = "host"; 618 status = "okay"; 619}; 620 621&uart3 { 622 pinctrl-names = "default"; 623 pinctrl-0 = <&pinctrl_uart3>; 624 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 625 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 626 uart-has-rtscts; 627 status = "okay"; 628}; 629 630&usdhc2 { 631 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 632 assigned-clock-rates = <400000000>; 633 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 634 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 635 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 636 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 637 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 638 vmmc-supply = <®_usdhc2_vmmc>; 639 bus-width = <4>; 640 status = "okay"; 641}; 642 643&usdhc3 { 644 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 645 assigned-clock-rates = <400000000>; 646 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 647 pinctrl-0 = <&pinctrl_usdhc3>; 648 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 649 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 650 bus-width = <8>; 651 non-removable; 652 status = "okay"; 653}; 654 655&wdog1 { 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_wdog>; 658 fsl,ext-reset-output; 659 status = "okay"; 660}; 661 662&iomuxc { 663 pinctrl_audio_pwr_reg: audiopwrreggrp { 664 fsl,pins = < 665 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 666 >; 667 }; 668 669 pinctrl_eqos: eqosgrp { 670 fsl,pins = < 671 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 672 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 673 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 674 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 675 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 676 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 677 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 678 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 679 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 680 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 681 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 682 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 683 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 684 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 685 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 686 >; 687 }; 688 689 pinctrl_fec: fecgrp { 690 fsl,pins = < 691 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 692 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 693 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 694 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 695 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 696 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 697 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 698 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 699 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 700 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 701 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 702 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 703 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 704 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 705 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 706 >; 707 }; 708 709 pinctrl_flexcan1: flexcan1grp { 710 fsl,pins = < 711 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 712 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 713 >; 714 }; 715 716 pinctrl_flexcan2: flexcan2grp { 717 fsl,pins = < 718 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 719 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 720 >; 721 }; 722 723 pinctrl_flexcan1_reg: flexcan1reggrp { 724 fsl,pins = < 725 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 726 >; 727 }; 728 729 pinctrl_flexcan2_reg: flexcan2reggrp { 730 fsl,pins = < 731 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 732 >; 733 }; 734 735 pinctrl_flexspi0: flexspi0grp { 736 fsl,pins = < 737 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 738 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 739 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 740 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 741 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 742 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 743 >; 744 }; 745 746 pinctrl_gpio_led: gpioledgrp { 747 fsl,pins = < 748 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 749 >; 750 }; 751 752 pinctrl_i2c1: i2c1grp { 753 fsl,pins = < 754 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 755 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 756 >; 757 }; 758 759 pinctrl_i2c2: i2c2grp { 760 fsl,pins = < 761 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 762 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 763 >; 764 }; 765 766 pinctrl_i2c3: i2c3grp { 767 fsl,pins = < 768 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 769 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 770 >; 771 }; 772 773 pinctrl_i2c5: i2c5grp { 774 fsl,pins = < 775 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 776 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 777 >; 778 }; 779 780 pinctrl_pcie0: pcie0grp { 781 fsl,pins = < 782 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 783 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 784 >; 785 }; 786 787 pinctrl_pcie0_reg: pcie0reggrp { 788 fsl,pins = < 789 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 790 >; 791 }; 792 793 pinctrl_pmic: pmicgrp { 794 fsl,pins = < 795 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 796 >; 797 }; 798 799 pinctrl_pca6416_int: pca6416_int_grp { 800 fsl,pins = < 801 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 802 >; 803 }; 804 805 pinctrl_pwm1: pwm1grp { 806 fsl,pins = < 807 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 808 >; 809 }; 810 811 pinctrl_pwm2: pwm2grp { 812 fsl,pins = < 813 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 814 >; 815 }; 816 817 pinctrl_pwm4: pwm4grp { 818 fsl,pins = < 819 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 820 >; 821 }; 822 823 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 824 fsl,pins = < 825 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 826 >; 827 }; 828 829 pinctrl_uart1: uart1grp { 830 fsl,pins = < 831 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 832 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 833 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 834 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 835 >; 836 }; 837 838 pinctrl_sai3: sai3grp { 839 fsl,pins = < 840 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 841 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 842 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 843 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 844 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 845 >; 846 }; 847 848 pinctrl_uart2: uart2grp { 849 fsl,pins = < 850 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 851 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 852 >; 853 }; 854 855 pinctrl_usb1_vbus: usb1grp { 856 fsl,pins = < 857 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 858 >; 859 }; 860 861 pinctrl_uart3: uart3grp { 862 fsl,pins = < 863 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 864 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 865 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 866 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 867 >; 868 }; 869 870 pinctrl_usdhc2: usdhc2grp { 871 fsl,pins = < 872 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 873 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 874 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 875 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 876 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 877 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 878 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 879 >; 880 }; 881 882 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 883 fsl,pins = < 884 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 885 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 886 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 887 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 888 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 889 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 890 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 891 >; 892 }; 893 894 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 895 fsl,pins = < 896 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 897 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 898 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 899 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 900 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 901 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 902 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 903 >; 904 }; 905 906 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 907 fsl,pins = < 908 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 909 >; 910 }; 911 912 pinctrl_usdhc3: usdhc3grp { 913 fsl,pins = < 914 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 915 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 916 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 917 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 918 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 919 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 920 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 921 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 922 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 923 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 924 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 925 >; 926 }; 927 928 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 929 fsl,pins = < 930 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 931 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 932 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 933 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 934 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 935 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 936 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 937 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 938 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 939 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 940 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 941 >; 942 }; 943 944 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 945 fsl,pins = < 946 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 947 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 948 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 949 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 950 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 951 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 952 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 953 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 954 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 955 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 956 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 957 >; 958 }; 959 960 pinctrl_wdog: wdoggrp { 961 fsl,pins = < 962 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 963 >; 964 }; 965}; 966