1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 hdmi-connector { 20 compatible = "hdmi-connector"; 21 label = "hdmi"; 22 type = "a"; 23 24 port { 25 hdmi_connector_in: endpoint { 26 remote-endpoint = <&adv7535_out>; 27 }; 28 }; 29 }; 30 31 gpio-leds { 32 compatible = "gpio-leds"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_led>; 35 36 status { 37 label = "yellow:status"; 38 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 39 default-state = "on"; 40 }; 41 }; 42 43 memory@40000000 { 44 device_type = "memory"; 45 reg = <0x0 0x40000000 0 0xc0000000>, 46 <0x1 0x00000000 0 0xc0000000>; 47 }; 48 49 pcie0_refclk: pcie0-refclk { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <100000000>; 53 }; 54 55 reg_audio_pwr: regulator-audio-pwr { 56 compatible = "regulator-fixed"; 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 59 regulator-name = "audio-pwr"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 63 enable-active-high; 64 }; 65 66 reg_can1_stby: regulator-can1-stby { 67 compatible = "regulator-fixed"; 68 regulator-name = "can1-stby"; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_flexcan1_reg>; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 74 enable-active-high; 75 }; 76 77 reg_can2_stby: regulator-can2-stby { 78 compatible = "regulator-fixed"; 79 regulator-name = "can2-stby"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_flexcan2_reg>; 82 regulator-min-microvolt = <3300000>; 83 regulator-max-microvolt = <3300000>; 84 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 }; 87 88 reg_pcie0: regulator-pcie { 89 compatible = "regulator-fixed"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_pcie0_reg>; 92 regulator-name = "MPCIE_3V3"; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 96 enable-active-high; 97 }; 98 99 reg_usdhc2_vmmc: regulator-usdhc2 { 100 compatible = "regulator-fixed"; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 103 regulator-name = "VSD_3V3"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 }; 109 110 reg_vext_3v3: regulator-vext-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "VEXT_3V3"; 113 regulator-min-microvolt = <3300000>; 114 regulator-max-microvolt = <3300000>; 115 }; 116 117 sound { 118 compatible = "simple-audio-card"; 119 simple-audio-card,name = "wm8960-audio"; 120 simple-audio-card,format = "i2s"; 121 simple-audio-card,frame-master = <&cpudai>; 122 simple-audio-card,bitclock-master = <&cpudai>; 123 simple-audio-card,widgets = 124 "Headphone", "Headphone Jack", 125 "Speaker", "External Speaker", 126 "Microphone", "Mic Jack"; 127 simple-audio-card,routing = 128 "Headphone Jack", "HP_L", 129 "Headphone Jack", "HP_R", 130 "External Speaker", "SPK_LP", 131 "External Speaker", "SPK_LN", 132 "External Speaker", "SPK_RP", 133 "External Speaker", "SPK_RN", 134 "LINPUT1", "Mic Jack", 135 "LINPUT3", "Mic Jack", 136 "Mic Jack", "MICB"; 137 138 cpudai: simple-audio-card,cpu { 139 sound-dai = <&sai3>; 140 }; 141 142 simple-audio-card,codec { 143 sound-dai = <&wm8960>; 144 }; 145 146 }; 147 148 sound-hdmi { 149 compatible = "fsl,imx-audio-hdmi"; 150 model = "audio-hdmi"; 151 audio-cpu = <&aud2htx>; 152 hdmi-out; 153 }; 154 155 sound-micfil { 156 compatible = "fsl,imx-audio-card"; 157 model = "micfil-audio"; 158 159 pri-dai-link { 160 link-name = "micfil hifi"; 161 format = "i2s"; 162 163 cpu { 164 sound-dai = <&micfil>; 165 }; 166 }; 167 }; 168 169 reserved-memory { 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 dsp_vdev0vring0: vdev0vring0@942f0000 { 175 reg = <0 0x942f0000 0 0x8000>; 176 no-map; 177 }; 178 179 dsp_vdev0vring1: vdev0vring1@942f8000 { 180 reg = <0 0x942f8000 0 0x8000>; 181 no-map; 182 }; 183 184 dsp_vdev0buffer: vdev0buffer@94300000 { 185 compatible = "shared-dma-pool"; 186 reg = <0 0x94300000 0 0x100000>; 187 no-map; 188 }; 189 }; 190}; 191 192&flexspi { 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_flexspi0>; 195 status = "okay"; 196 197 flash@0 { 198 compatible = "jedec,spi-nor"; 199 reg = <0>; 200 spi-max-frequency = <80000000>; 201 spi-tx-bus-width = <1>; 202 spi-rx-bus-width = <4>; 203 }; 204}; 205 206&A53_0 { 207 cpu-supply = <®_arm>; 208}; 209 210&A53_1 { 211 cpu-supply = <®_arm>; 212}; 213 214&A53_2 { 215 cpu-supply = <®_arm>; 216}; 217 218&A53_3 { 219 cpu-supply = <®_arm>; 220}; 221 222&aud2htx { 223 status = "okay"; 224}; 225 226&eqos { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_eqos>; 229 phy-mode = "rgmii-id"; 230 phy-handle = <ðphy0>; 231 snps,force_thresh_dma_mode; 232 snps,mtl-tx-config = <&mtl_tx_setup>; 233 snps,mtl-rx-config = <&mtl_rx_setup>; 234 status = "okay"; 235 236 mdio { 237 compatible = "snps,dwmac-mdio"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 ethphy0: ethernet-phy@1 { 242 compatible = "ethernet-phy-ieee802.3-c22"; 243 reg = <1>; 244 eee-broken-1000t; 245 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 246 reset-assert-us = <10000>; 247 reset-deassert-us = <80000>; 248 realtek,clkout-disable; 249 }; 250 }; 251 252 mtl_tx_setup: tx-queues-config { 253 snps,tx-queues-to-use = <5>; 254 snps,tx-sched-sp; 255 256 queue0 { 257 snps,dcb-algorithm; 258 snps,priority = <0x1>; 259 }; 260 261 queue1 { 262 snps,dcb-algorithm; 263 snps,priority = <0x2>; 264 }; 265 266 queue2 { 267 snps,dcb-algorithm; 268 snps,priority = <0x4>; 269 }; 270 271 queue3 { 272 snps,dcb-algorithm; 273 snps,priority = <0x8>; 274 }; 275 276 queue4 { 277 snps,dcb-algorithm; 278 snps,priority = <0xf0>; 279 }; 280 }; 281 282 mtl_rx_setup: rx-queues-config { 283 snps,rx-queues-to-use = <5>; 284 snps,rx-sched-sp; 285 286 queue0 { 287 snps,dcb-algorithm; 288 snps,priority = <0x1>; 289 snps,map-to-dma-channel = <0>; 290 }; 291 292 queue1 { 293 snps,dcb-algorithm; 294 snps,priority = <0x2>; 295 snps,map-to-dma-channel = <1>; 296 }; 297 298 queue2 { 299 snps,dcb-algorithm; 300 snps,priority = <0x4>; 301 snps,map-to-dma-channel = <2>; 302 }; 303 304 queue3 { 305 snps,dcb-algorithm; 306 snps,priority = <0x8>; 307 snps,map-to-dma-channel = <3>; 308 }; 309 310 queue4 { 311 snps,dcb-algorithm; 312 snps,priority = <0xf0>; 313 snps,map-to-dma-channel = <4>; 314 }; 315 }; 316}; 317 318&fec { 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_fec>; 321 phy-mode = "rgmii-id"; 322 phy-handle = <ðphy1>; 323 fsl,magic-packet; 324 status = "okay"; 325 326 mdio { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 330 ethphy1: ethernet-phy@1 { 331 compatible = "ethernet-phy-ieee802.3-c22"; 332 reg = <1>; 333 eee-broken-1000t; 334 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 335 reset-assert-us = <10000>; 336 reset-deassert-us = <80000>; 337 realtek,clkout-disable; 338 }; 339 }; 340}; 341 342&flexcan1 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_flexcan1>; 345 xceiver-supply = <®_can1_stby>; 346 status = "okay"; 347}; 348 349&flexcan2 { 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_flexcan2>; 352 xceiver-supply = <®_can2_stby>; 353 status = "disabled";/* can2 pin conflict with pdm */ 354}; 355 356&i2c1 { 357 clock-frequency = <400000>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_i2c1>; 360 status = "okay"; 361 362 pmic@25 { 363 compatible = "nxp,pca9450c"; 364 reg = <0x25>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_pmic>; 367 interrupt-parent = <&gpio1>; 368 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 369 370 regulators { 371 BUCK1 { 372 regulator-name = "BUCK1"; 373 regulator-min-microvolt = <720000>; 374 regulator-max-microvolt = <1000000>; 375 regulator-boot-on; 376 regulator-always-on; 377 regulator-ramp-delay = <3125>; 378 }; 379 380 reg_arm: BUCK2 { 381 regulator-name = "BUCK2"; 382 regulator-min-microvolt = <720000>; 383 regulator-max-microvolt = <1025000>; 384 regulator-boot-on; 385 regulator-always-on; 386 regulator-ramp-delay = <3125>; 387 nxp,dvs-run-voltage = <950000>; 388 nxp,dvs-standby-voltage = <850000>; 389 }; 390 391 BUCK4 { 392 regulator-name = "BUCK4"; 393 regulator-min-microvolt = <3000000>; 394 regulator-max-microvolt = <3600000>; 395 regulator-boot-on; 396 regulator-always-on; 397 }; 398 399 reg_buck5: BUCK5 { 400 regulator-name = "BUCK5"; 401 regulator-min-microvolt = <1650000>; 402 regulator-max-microvolt = <1950000>; 403 regulator-boot-on; 404 regulator-always-on; 405 }; 406 407 BUCK6 { 408 regulator-name = "BUCK6"; 409 regulator-min-microvolt = <1045000>; 410 regulator-max-microvolt = <1155000>; 411 regulator-boot-on; 412 regulator-always-on; 413 }; 414 415 LDO1 { 416 regulator-name = "LDO1"; 417 regulator-min-microvolt = <1650000>; 418 regulator-max-microvolt = <1950000>; 419 regulator-boot-on; 420 regulator-always-on; 421 }; 422 423 LDO3 { 424 regulator-name = "LDO3"; 425 regulator-min-microvolt = <1710000>; 426 regulator-max-microvolt = <1890000>; 427 regulator-boot-on; 428 regulator-always-on; 429 }; 430 431 LDO5 { 432 regulator-name = "LDO5"; 433 regulator-min-microvolt = <1800000>; 434 regulator-max-microvolt = <3300000>; 435 regulator-boot-on; 436 regulator-always-on; 437 }; 438 }; 439 }; 440}; 441 442&i2c2 { 443 clock-frequency = <400000>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_i2c2>; 446 status = "okay"; 447 448 hdmi@3d { 449 compatible = "adi,adv7535"; 450 reg = <0x3d>; 451 interrupt-parent = <&gpio1>; 452 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 453 adi,dsi-lanes = <4>; 454 avdd-supply = <®_buck5>; 455 dvdd-supply = <®_buck5>; 456 pvdd-supply = <®_buck5>; 457 a2vdd-supply = <®_buck5>; 458 v3p3-supply = <®_vext_3v3>; 459 v1p2-supply = <®_buck5>; 460 461 ports { 462 #address-cells = <1>; 463 #size-cells = <0>; 464 465 port@0 { 466 reg = <0>; 467 468 adv7535_in: endpoint { 469 remote-endpoint = <&dsi_out>; 470 }; 471 }; 472 473 port@1 { 474 reg = <1>; 475 476 adv7535_out: endpoint { 477 remote-endpoint = <&hdmi_connector_in>; 478 }; 479 }; 480 481 }; 482 }; 483}; 484 485&i2c3 { 486 clock-frequency = <400000>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_i2c3>; 489 status = "okay"; 490 491 wm8960: codec@1a { 492 compatible = "wlf,wm8960"; 493 reg = <0x1a>; 494 #sound-dai-cells = <0>; 495 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 496 clock-names = "mclk"; 497 wlf,shared-lrclk; 498 wlf,hp-cfg = <3 2 3>; 499 wlf,gpio-cfg = <1 3>; 500 SPKVDD1-supply = <®_audio_pwr>; 501 }; 502 503 pca6416: gpio@20 { 504 compatible = "ti,tca6416"; 505 reg = <0x20>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pinctrl_pca6416_int>; 512 interrupt-parent = <&gpio1>; 513 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 514 gpio-line-names = "EXT_PWREN1", 515 "EXT_PWREN2", 516 "CAN1/I2C5_SEL", 517 "PDM/CAN2_SEL", 518 "FAN_EN", 519 "PWR_MEAS_IO1", 520 "PWR_MEAS_IO2", 521 "EXP_P0_7", 522 "EXP_P1_0", 523 "EXP_P1_1", 524 "EXP_P1_2", 525 "EXP_P1_3", 526 "EXP_P1_4", 527 "EXP_P1_5", 528 "EXP_P1_6", 529 "EXP_P1_7"; 530 }; 531}; 532 533/* I2C on expansion connector J22. */ 534&i2c5 { 535 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_i2c5>; 538 status = "disabled"; /* can1 pins conflict with i2c5 */ 539 540 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 541 * LOW: CAN1 (default, pull-down) 542 * HIGH: I2C5 543 * You need to set it to high to enable I2C5 (for example, add gpio-hog 544 * in pca6416 node). 545 */ 546}; 547 548&lcdif1 { 549 status = "okay"; 550}; 551 552&micfil { 553 #sound-dai-cells = <0>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_pdm>; 556 assigned-clocks = <&clk IMX8MP_CLK_PDM>; 557 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 558 assigned-clock-rates = <196608000>; 559 status = "okay"; 560}; 561 562&mipi_dsi { 563 samsung,esc-clock-frequency = <10000000>; 564 status = "okay"; 565 566 ports { 567 port@1 { 568 reg = <1>; 569 570 dsi_out: endpoint { 571 remote-endpoint = <&adv7535_in>; 572 data-lanes = <1 2 3 4>; 573 }; 574 }; 575 }; 576}; 577 578&pcie_phy { 579 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 580 clocks = <&pcie0_refclk>; 581 clock-names = "ref"; 582 status = "okay"; 583}; 584 585&pcie { 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_pcie0>; 588 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 589 vpcie-supply = <®_pcie0>; 590 status = "okay"; 591}; 592 593&pwm1 { 594 pinctrl-names = "default"; 595 pinctrl-0 = <&pinctrl_pwm1>; 596 status = "okay"; 597}; 598 599&pwm2 { 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_pwm2>; 602 status = "okay"; 603}; 604 605&pwm4 { 606 pinctrl-names = "default"; 607 pinctrl-0 = <&pinctrl_pwm4>; 608 status = "okay"; 609}; 610 611&sai3 { 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pinctrl_sai3>; 614 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 615 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 616 assigned-clock-rates = <12288000>; 617 fsl,sai-mclk-direction-output; 618 status = "okay"; 619}; 620 621&snvs_pwrkey { 622 status = "okay"; 623}; 624 625&uart1 { /* BT */ 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_uart1>; 628 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 629 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 630 uart-has-rtscts; 631 status = "okay"; 632}; 633 634&uart2 { 635 /* console */ 636 pinctrl-names = "default"; 637 pinctrl-0 = <&pinctrl_uart2>; 638 status = "okay"; 639}; 640 641&usb3_phy1 { 642 status = "okay"; 643}; 644 645&usb3_1 { 646 status = "okay"; 647}; 648 649&usb_dwc3_1 { 650 pinctrl-names = "default"; 651 pinctrl-0 = <&pinctrl_usb1_vbus>; 652 dr_mode = "host"; 653 status = "okay"; 654}; 655 656&uart3 { 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pinctrl_uart3>; 659 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 660 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 661 uart-has-rtscts; 662 status = "okay"; 663}; 664 665&usdhc2 { 666 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 667 assigned-clock-rates = <400000000>; 668 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 669 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 670 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 671 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 672 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 673 vmmc-supply = <®_usdhc2_vmmc>; 674 bus-width = <4>; 675 status = "okay"; 676}; 677 678&usdhc3 { 679 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 680 assigned-clock-rates = <400000000>; 681 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 682 pinctrl-0 = <&pinctrl_usdhc3>; 683 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 684 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 685 bus-width = <8>; 686 non-removable; 687 status = "okay"; 688}; 689 690&wdog1 { 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_wdog>; 693 fsl,ext-reset-output; 694 status = "okay"; 695}; 696 697&iomuxc { 698 pinctrl_audio_pwr_reg: audiopwrreggrp { 699 fsl,pins = < 700 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 701 >; 702 }; 703 704 pinctrl_eqos: eqosgrp { 705 fsl,pins = < 706 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 707 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 708 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 709 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 710 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 711 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 712 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 713 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 714 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 715 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 716 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 717 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 718 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 719 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 720 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 721 >; 722 }; 723 724 pinctrl_fec: fecgrp { 725 fsl,pins = < 726 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 727 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 728 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 729 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 730 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 731 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 732 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 733 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 734 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 735 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 736 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 737 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 738 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 739 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 740 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 741 >; 742 }; 743 744 pinctrl_flexcan1: flexcan1grp { 745 fsl,pins = < 746 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 747 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 748 >; 749 }; 750 751 pinctrl_flexcan2: flexcan2grp { 752 fsl,pins = < 753 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 754 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 755 >; 756 }; 757 758 pinctrl_flexcan1_reg: flexcan1reggrp { 759 fsl,pins = < 760 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 761 >; 762 }; 763 764 pinctrl_flexcan2_reg: flexcan2reggrp { 765 fsl,pins = < 766 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 767 >; 768 }; 769 770 pinctrl_flexspi0: flexspi0grp { 771 fsl,pins = < 772 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 773 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 774 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 775 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 776 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 777 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 778 >; 779 }; 780 781 pinctrl_gpio_led: gpioledgrp { 782 fsl,pins = < 783 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 784 >; 785 }; 786 787 pinctrl_i2c1: i2c1grp { 788 fsl,pins = < 789 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 790 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 791 >; 792 }; 793 794 pinctrl_i2c2: i2c2grp { 795 fsl,pins = < 796 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 797 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 798 >; 799 }; 800 801 pinctrl_i2c3: i2c3grp { 802 fsl,pins = < 803 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 804 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 805 >; 806 }; 807 808 pinctrl_i2c5: i2c5grp { 809 fsl,pins = < 810 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 811 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 812 >; 813 }; 814 815 pinctrl_pcie0: pcie0grp { 816 fsl,pins = < 817 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 818 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 819 >; 820 }; 821 822 pinctrl_pcie0_reg: pcie0reggrp { 823 fsl,pins = < 824 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 825 >; 826 }; 827 828 pinctrl_pdm: pdmgrp { 829 fsl,pins = < 830 MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 831 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 832 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 833 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 834 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 835 >; 836 }; 837 838 pinctrl_pmic: pmicgrp { 839 fsl,pins = < 840 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 841 >; 842 }; 843 844 pinctrl_pca6416_int: pca6416_int_grp { 845 fsl,pins = < 846 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 847 >; 848 }; 849 850 pinctrl_pwm1: pwm1grp { 851 fsl,pins = < 852 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 853 >; 854 }; 855 856 pinctrl_pwm2: pwm2grp { 857 fsl,pins = < 858 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 859 >; 860 }; 861 862 pinctrl_pwm4: pwm4grp { 863 fsl,pins = < 864 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 865 >; 866 }; 867 868 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 869 fsl,pins = < 870 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 871 >; 872 }; 873 874 pinctrl_uart1: uart1grp { 875 fsl,pins = < 876 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 877 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 878 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 879 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 880 >; 881 }; 882 883 pinctrl_sai3: sai3grp { 884 fsl,pins = < 885 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 886 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 887 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 888 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 889 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 890 >; 891 }; 892 893 pinctrl_uart2: uart2grp { 894 fsl,pins = < 895 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 896 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 897 >; 898 }; 899 900 pinctrl_usb1_vbus: usb1grp { 901 fsl,pins = < 902 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 903 >; 904 }; 905 906 pinctrl_uart3: uart3grp { 907 fsl,pins = < 908 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 909 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 910 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 911 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 912 >; 913 }; 914 915 pinctrl_usdhc2: usdhc2grp { 916 fsl,pins = < 917 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 918 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 919 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 920 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 921 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 922 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 923 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 924 >; 925 }; 926 927 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 928 fsl,pins = < 929 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 930 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 931 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 932 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 933 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 934 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 935 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 936 >; 937 }; 938 939 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 940 fsl,pins = < 941 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 942 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 943 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 944 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 945 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 946 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 947 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 948 >; 949 }; 950 951 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 952 fsl,pins = < 953 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 954 >; 955 }; 956 957 pinctrl_usdhc3: usdhc3grp { 958 fsl,pins = < 959 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 960 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 961 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 962 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 963 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 964 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 965 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 966 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 967 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 968 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 969 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 970 >; 971 }; 972 973 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 974 fsl,pins = < 975 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 976 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 977 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 978 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 979 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 980 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 981 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 982 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 983 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 984 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 985 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 986 >; 987 }; 988 989 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 990 fsl,pins = < 991 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 992 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 993 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 994 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 995 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 996 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 997 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 998 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 999 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1000 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1001 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1002 >; 1003 }; 1004 1005 pinctrl_wdog: wdoggrp { 1006 fsl,pins = < 1007 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 1008 >; 1009 }; 1010}; 1011