1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 backlight_lvds: backlight-lvds { 20 compatible = "pwm-backlight"; 21 pwms = <&pwm2 0 100000 0>; 22 brightness-levels = <0 100>; 23 num-interpolated-steps = <100>; 24 default-brightness-level = <100>; 25 power-supply = <®_per_12v>; 26 status = "disabled"; 27 }; 28 29 hdmi-connector { 30 compatible = "hdmi-connector"; 31 label = "hdmi"; 32 type = "a"; 33 34 port { 35 hdmi_connector_in: endpoint { 36 remote-endpoint = <&adv7535_out>; 37 }; 38 }; 39 }; 40 41 gpio-leds { 42 compatible = "gpio-leds"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_led>; 45 46 status { 47 label = "yellow:status"; 48 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 49 default-state = "on"; 50 }; 51 }; 52 53 memory@40000000 { 54 device_type = "memory"; 55 reg = <0x0 0x40000000 0 0xc0000000>, 56 <0x1 0x00000000 0 0xc0000000>; 57 }; 58 59 native-hdmi-connector { 60 compatible = "hdmi-connector"; 61 label = "HDMI OUT"; 62 type = "a"; 63 64 port { 65 hdmi_in: endpoint { 66 remote-endpoint = <&hdmi_tx_out>; 67 }; 68 }; 69 }; 70 71 pcie0_refclk: pcie0-refclk { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <100000000>; 75 }; 76 77 reg_audio_3v3: regulator-audio-3v3 { 78 compatible = "regulator-fixed"; 79 regulator-name = "audio-3v3"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 regulator-always-on; 83 regulator-boot-on; 84 }; 85 86 reg_audio_1v8: regulator-audio-1v8 { 87 compatible = "regulator-fixed"; 88 regulator-name = "audio-1v8"; 89 regulator-min-microvolt = <1800000>; 90 regulator-max-microvolt = <1800000>; 91 regulator-always-on; 92 regulator-boot-on; 93 }; 94 95 reg_audio_pwr: regulator-audio-pwr { 96 compatible = "regulator-fixed"; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 99 regulator-name = "audio-pwr"; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 103 enable-active-high; 104 }; 105 106 reg_can1_stby: regulator-can1-stby { 107 compatible = "regulator-fixed"; 108 regulator-name = "can1-stby"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_flexcan1_reg>; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 114 enable-active-high; 115 }; 116 117 reg_can2_stby: regulator-can2-stby { 118 compatible = "regulator-fixed"; 119 regulator-name = "can2-stby"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_flexcan2_reg>; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 125 enable-active-high; 126 }; 127 128 reg_pcie0: regulator-pcie { 129 compatible = "regulator-fixed"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_pcie0_reg>; 132 regulator-name = "MPCIE_3V3"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 136 enable-active-high; 137 }; 138 139 reg_per_12v: regulator-per-12v { 140 compatible = "regulator-fixed"; 141 regulator-name = "PER_12V"; 142 regulator-min-microvolt = <12000000>; 143 regulator-max-microvolt = <12000000>; 144 gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; 145 enable-active-high; 146 }; 147 148 reg_usdhc2_vmmc: regulator-usdhc2 { 149 compatible = "regulator-fixed"; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 152 regulator-name = "VSD_3V3"; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 156 enable-active-high; 157 }; 158 159 reg_vext_3v3: regulator-vext-3v3 { 160 compatible = "regulator-fixed"; 161 regulator-name = "VEXT_3V3"; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 }; 165 166 audio_codec_bt_sco: audio-codec-bt-sco { 167 compatible = "linux,bt-sco"; 168 #sound-dai-cells = <1>; 169 }; 170 171 sound { 172 compatible = "simple-audio-card"; 173 simple-audio-card,name = "wm8960-audio"; 174 simple-audio-card,format = "i2s"; 175 simple-audio-card,frame-master = <&cpudai>; 176 simple-audio-card,bitclock-master = <&cpudai>; 177 simple-audio-card,widgets = 178 "Headphone", "Headphone Jack", 179 "Speaker", "External Speaker", 180 "Microphone", "Mic Jack"; 181 simple-audio-card,routing = 182 "Headphone Jack", "HP_L", 183 "Headphone Jack", "HP_R", 184 "External Speaker", "SPK_LP", 185 "External Speaker", "SPK_LN", 186 "External Speaker", "SPK_RP", 187 "External Speaker", "SPK_RN", 188 "LINPUT1", "Mic Jack", 189 "LINPUT3", "Mic Jack", 190 "Mic Jack", "MICB"; 191 192 cpudai: simple-audio-card,cpu { 193 sound-dai = <&sai3>; 194 }; 195 196 simple-audio-card,codec { 197 sound-dai = <&wm8960>; 198 }; 199 200 }; 201 202 sound-bt-sco { 203 compatible = "simple-audio-card"; 204 simple-audio-card,name = "bt-sco-audio"; 205 simple-audio-card,format = "dsp_a"; 206 simple-audio-card,bitclock-inversion; 207 simple-audio-card,frame-master = <&btcpu>; 208 simple-audio-card,bitclock-master = <&btcpu>; 209 210 btcpu: simple-audio-card,cpu { 211 sound-dai = <&sai2>; 212 dai-tdm-slot-num = <2>; 213 dai-tdm-slot-width = <16>; 214 }; 215 216 simple-audio-card,codec { 217 sound-dai = <&audio_codec_bt_sco 1>; 218 }; 219 }; 220 221 sound-hdmi { 222 compatible = "fsl,imx-audio-hdmi"; 223 model = "audio-hdmi"; 224 audio-cpu = <&aud2htx>; 225 hdmi-out; 226 }; 227 228 sound-micfil { 229 compatible = "fsl,imx-audio-card"; 230 model = "micfil-audio"; 231 232 pri-dai-link { 233 link-name = "micfil hifi"; 234 format = "i2s"; 235 236 cpu { 237 sound-dai = <&micfil>; 238 }; 239 }; 240 }; 241 242 sound-xcvr { 243 compatible = "fsl,imx-audio-card"; 244 model = "imx-audio-xcvr"; 245 246 pri-dai-link { 247 link-name = "XCVR PCM"; 248 249 cpu { 250 sound-dai = <&xcvr>; 251 }; 252 }; 253 }; 254 255 reserved-memory { 256 #address-cells = <2>; 257 #size-cells = <2>; 258 ranges; 259 260 dsp_vdev0vring0: vdev0vring0@942f0000 { 261 reg = <0 0x942f0000 0 0x8000>; 262 no-map; 263 }; 264 265 dsp_vdev0vring1: vdev0vring1@942f8000 { 266 reg = <0 0x942f8000 0 0x8000>; 267 no-map; 268 }; 269 270 dsp_vdev0buffer: vdev0buffer@94300000 { 271 compatible = "shared-dma-pool"; 272 reg = <0 0x94300000 0 0x100000>; 273 no-map; 274 }; 275 }; 276}; 277 278&flexspi { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_flexspi0>; 281 status = "okay"; 282 283 flash@0 { 284 compatible = "jedec,spi-nor"; 285 reg = <0>; 286 spi-max-frequency = <80000000>; 287 spi-tx-bus-width = <1>; 288 spi-rx-bus-width = <4>; 289 }; 290}; 291 292&A53_0 { 293 cpu-supply = <®_arm>; 294}; 295 296&A53_1 { 297 cpu-supply = <®_arm>; 298}; 299 300&A53_2 { 301 cpu-supply = <®_arm>; 302}; 303 304&A53_3 { 305 cpu-supply = <®_arm>; 306}; 307 308&aud2htx { 309 status = "okay"; 310}; 311 312&dsp_reserved { 313 status = "okay"; 314}; 315 316&dsp { 317 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 318 <&dsp_vdev0vring1>, <&dsp_reserved>; 319 status = "okay"; 320}; 321 322&eqos { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_eqos>; 325 phy-mode = "rgmii-id"; 326 phy-handle = <ðphy0>; 327 snps,force_thresh_dma_mode; 328 snps,mtl-tx-config = <&mtl_tx_setup>; 329 snps,mtl-rx-config = <&mtl_rx_setup>; 330 status = "okay"; 331 332 mdio { 333 compatible = "snps,dwmac-mdio"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 ethphy0: ethernet-phy@1 { 338 compatible = "ethernet-phy-ieee802.3-c22"; 339 reg = <1>; 340 eee-broken-1000t; 341 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 342 reset-assert-us = <10000>; 343 reset-deassert-us = <80000>; 344 realtek,clkout-disable; 345 }; 346 }; 347 348 mtl_tx_setup: tx-queues-config { 349 snps,tx-queues-to-use = <5>; 350 351 queue0 { 352 snps,dcb-algorithm; 353 snps,priority = <0x1>; 354 }; 355 356 queue1 { 357 snps,dcb-algorithm; 358 snps,priority = <0x2>; 359 }; 360 361 queue2 { 362 snps,dcb-algorithm; 363 snps,priority = <0x4>; 364 }; 365 366 queue3 { 367 snps,dcb-algorithm; 368 snps,priority = <0x8>; 369 }; 370 371 queue4 { 372 snps,dcb-algorithm; 373 snps,priority = <0xf0>; 374 }; 375 }; 376 377 mtl_rx_setup: rx-queues-config { 378 snps,rx-queues-to-use = <5>; 379 snps,rx-sched-sp; 380 381 queue0 { 382 snps,dcb-algorithm; 383 snps,priority = <0x1>; 384 snps,map-to-dma-channel = <0>; 385 }; 386 387 queue1 { 388 snps,dcb-algorithm; 389 snps,priority = <0x2>; 390 snps,map-to-dma-channel = <1>; 391 }; 392 393 queue2 { 394 snps,dcb-algorithm; 395 snps,priority = <0x4>; 396 snps,map-to-dma-channel = <2>; 397 }; 398 399 queue3 { 400 snps,dcb-algorithm; 401 snps,priority = <0x8>; 402 snps,map-to-dma-channel = <3>; 403 }; 404 405 queue4 { 406 snps,dcb-algorithm; 407 snps,priority = <0xf0>; 408 snps,map-to-dma-channel = <4>; 409 }; 410 }; 411}; 412 413&fec { 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_fec>; 416 phy-mode = "rgmii-id"; 417 phy-handle = <ðphy1>; 418 fsl,magic-packet; 419 status = "okay"; 420 421 mdio { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 425 ethphy1: ethernet-phy@1 { 426 compatible = "ethernet-phy-ieee802.3-c22"; 427 reg = <1>; 428 eee-broken-1000t; 429 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 430 reset-assert-us = <10000>; 431 reset-deassert-us = <80000>; 432 realtek,clkout-disable; 433 }; 434 }; 435}; 436 437&flexcan1 { 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pinctrl_flexcan1>; 440 xceiver-supply = <®_can1_stby>; 441 status = "okay"; 442}; 443 444&flexcan2 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_flexcan2>; 447 xceiver-supply = <®_can2_stby>; 448 status = "disabled";/* can2 pin conflict with pdm */ 449}; 450 451&hdmi_pvi { 452 status = "okay"; 453}; 454 455&hdmi_tx { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_hdmi>; 458 status = "okay"; 459 460 ports { 461 port@1 { 462 hdmi_tx_out: endpoint { 463 remote-endpoint = <&hdmi_in>; 464 }; 465 }; 466 }; 467}; 468 469&hdmi_tx_phy { 470 status = "okay"; 471}; 472 473&i2c1 { 474 clock-frequency = <400000>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_i2c1>; 477 status = "okay"; 478 479 pmic@25 { 480 compatible = "nxp,pca9450c"; 481 reg = <0x25>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pinctrl_pmic>; 484 interrupt-parent = <&gpio1>; 485 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 486 487 regulators { 488 BUCK1 { 489 regulator-name = "BUCK1"; 490 regulator-min-microvolt = <720000>; 491 regulator-max-microvolt = <1000000>; 492 regulator-boot-on; 493 regulator-always-on; 494 regulator-ramp-delay = <3125>; 495 }; 496 497 reg_arm: BUCK2 { 498 regulator-name = "BUCK2"; 499 regulator-min-microvolt = <720000>; 500 regulator-max-microvolt = <1025000>; 501 regulator-boot-on; 502 regulator-always-on; 503 regulator-ramp-delay = <3125>; 504 nxp,dvs-run-voltage = <950000>; 505 nxp,dvs-standby-voltage = <850000>; 506 }; 507 508 BUCK4 { 509 regulator-name = "BUCK4"; 510 regulator-min-microvolt = <3000000>; 511 regulator-max-microvolt = <3600000>; 512 regulator-boot-on; 513 regulator-always-on; 514 }; 515 516 reg_buck5: BUCK5 { 517 regulator-name = "BUCK5"; 518 regulator-min-microvolt = <1650000>; 519 regulator-max-microvolt = <1950000>; 520 regulator-boot-on; 521 regulator-always-on; 522 }; 523 524 BUCK6 { 525 regulator-name = "BUCK6"; 526 regulator-min-microvolt = <1045000>; 527 regulator-max-microvolt = <1155000>; 528 regulator-boot-on; 529 regulator-always-on; 530 }; 531 532 LDO1 { 533 regulator-name = "LDO1"; 534 regulator-min-microvolt = <1650000>; 535 regulator-max-microvolt = <1950000>; 536 regulator-boot-on; 537 regulator-always-on; 538 }; 539 540 LDO3 { 541 regulator-name = "LDO3"; 542 regulator-min-microvolt = <1710000>; 543 regulator-max-microvolt = <1890000>; 544 regulator-boot-on; 545 regulator-always-on; 546 }; 547 548 LDO5 { 549 regulator-name = "LDO5"; 550 regulator-min-microvolt = <1800000>; 551 regulator-max-microvolt = <3300000>; 552 regulator-boot-on; 553 regulator-always-on; 554 }; 555 }; 556 }; 557}; 558 559&i2c2 { 560 clock-frequency = <400000>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&pinctrl_i2c2>; 563 status = "okay"; 564 565 hdmi@3d { 566 compatible = "adi,adv7535"; 567 reg = <0x3d>; 568 interrupt-parent = <&gpio1>; 569 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 570 adi,dsi-lanes = <4>; 571 avdd-supply = <®_buck5>; 572 dvdd-supply = <®_buck5>; 573 pvdd-supply = <®_buck5>; 574 a2vdd-supply = <®_buck5>; 575 v3p3-supply = <®_vext_3v3>; 576 v1p2-supply = <®_buck5>; 577 578 ports { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 582 port@0 { 583 reg = <0>; 584 585 adv7535_in: endpoint { 586 remote-endpoint = <&dsi_out>; 587 }; 588 }; 589 590 port@1 { 591 reg = <1>; 592 593 adv7535_out: endpoint { 594 remote-endpoint = <&hdmi_connector_in>; 595 }; 596 }; 597 598 }; 599 }; 600}; 601 602&i2c3 { 603 clock-frequency = <400000>; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&pinctrl_i2c3>; 606 status = "okay"; 607 608 wm8960: codec@1a { 609 compatible = "wlf,wm8960"; 610 reg = <0x1a>; 611 #sound-dai-cells = <0>; 612 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 613 clock-names = "mclk"; 614 wlf,shared-lrclk; 615 wlf,hp-cfg = <3 2 3>; 616 wlf,gpio-cfg = <1 3>; 617 AVDD-supply = <®_audio_3v3>; 618 DBVDD-supply = <®_audio_1v8>; 619 DCVDD-supply = <®_audio_1v8>; 620 SPKVDD1-supply = <®_audio_pwr>; 621 SPKVDD2-supply = <®_audio_pwr>; 622 }; 623 624 pca6416: gpio@20 { 625 compatible = "ti,tca6416"; 626 reg = <0x20>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_pca6416_int>; 633 interrupt-parent = <&gpio1>; 634 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 635 gpio-line-names = "EXT_PWREN1", 636 "EXT_PWREN2", 637 "CAN1/I2C5_SEL", 638 "PDM/CAN2_SEL", 639 "FAN_EN", 640 "PWR_MEAS_IO1", 641 "PWR_MEAS_IO2", 642 "EXP_P0_7", 643 "EXP_P1_0", 644 "EXP_P1_1", 645 "EXP_P1_2", 646 "EXP_P1_3", 647 "EXP_P1_4", 648 "EXP_P1_5", 649 "EXP_P1_6", 650 "EXP_P1_7"; 651 }; 652}; 653 654/* I2C on expansion connector J22. */ 655&i2c5 { 656 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 657 pinctrl-names = "default"; 658 pinctrl-0 = <&pinctrl_i2c5>; 659 status = "disabled"; /* can1 pins conflict with i2c5 */ 660 661 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 662 * LOW: CAN1 (default, pull-down) 663 * HIGH: I2C5 664 * You need to set it to high to enable I2C5 (for example, add gpio-hog 665 * in pca6416 node). 666 */ 667}; 668 669&lcdif1 { 670 status = "okay"; 671}; 672 673&lcdif3 { 674 status = "okay"; 675}; 676 677&micfil { 678 #sound-dai-cells = <0>; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pinctrl_pdm>; 681 assigned-clocks = <&clk IMX8MP_CLK_PDM>; 682 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 683 assigned-clock-rates = <196608000>; 684 status = "okay"; 685}; 686 687&mipi_dsi { 688 samsung,esc-clock-frequency = <10000000>; 689 status = "okay"; 690 691 ports { 692 port@1 { 693 reg = <1>; 694 695 dsi_out: endpoint { 696 remote-endpoint = <&adv7535_in>; 697 data-lanes = <1 2 3 4>; 698 }; 699 }; 700 }; 701}; 702 703&mu2 { 704 status = "okay"; 705}; 706 707&pcie_phy { 708 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 709 clocks = <&pcie0_refclk>; 710 clock-names = "ref"; 711 status = "okay"; 712}; 713 714&pcie0 { 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_pcie0>; 717 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 718 vpcie-supply = <®_pcie0>; 719 status = "okay"; 720}; 721 722&pcie0_ep { 723 pinctrl-0 = <&pinctrl_pcie0>; 724 pinctrl-names = "default"; 725 status = "disabled"; 726}; 727 728&pwm1 { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_pwm1>; 731 status = "okay"; 732}; 733 734&pwm2 { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&pinctrl_pwm2>; 737 status = "okay"; 738}; 739 740&pwm4 { 741 pinctrl-names = "default"; 742 pinctrl-0 = <&pinctrl_pwm4>; 743 status = "okay"; 744}; 745 746&sai2 { 747 #sound-dai-cells = <0>; 748 pinctrl-names = "default"; 749 pinctrl-0 = <&pinctrl_sai2>; 750 assigned-clocks = <&clk IMX8MP_CLK_SAI2>; 751 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 752 assigned-clock-rates = <12288000>; 753 fsl,sai-mclk-direction-output; 754 status = "okay"; 755}; 756 757&sai3 { 758 pinctrl-names = "default"; 759 pinctrl-0 = <&pinctrl_sai3>; 760 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 761 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 762 assigned-clock-rates = <12288000>; 763 fsl,sai-mclk-direction-output; 764 status = "okay"; 765}; 766 767&snvs_pwrkey { 768 status = "okay"; 769}; 770 771&uart1 { /* BT */ 772 pinctrl-names = "default"; 773 pinctrl-0 = <&pinctrl_uart1>; 774 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 775 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 776 uart-has-rtscts; 777 status = "okay"; 778}; 779 780&uart2 { 781 /* console */ 782 pinctrl-names = "default"; 783 pinctrl-0 = <&pinctrl_uart2>; 784 status = "okay"; 785}; 786 787&usb3_phy1 { 788 status = "okay"; 789}; 790 791&usb3_1 { 792 status = "okay"; 793}; 794 795&usb_dwc3_1 { 796 pinctrl-names = "default"; 797 pinctrl-0 = <&pinctrl_usb1_vbus>; 798 dr_mode = "host"; 799 status = "okay"; 800}; 801 802&uart3 { 803 pinctrl-names = "default"; 804 pinctrl-0 = <&pinctrl_uart3>; 805 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 806 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 807 uart-has-rtscts; 808 status = "okay"; 809}; 810 811&usdhc2 { 812 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 813 assigned-clock-rates = <400000000>; 814 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 815 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 816 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 817 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 818 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 819 vmmc-supply = <®_usdhc2_vmmc>; 820 bus-width = <4>; 821 status = "okay"; 822}; 823 824&usdhc3 { 825 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 826 assigned-clock-rates = <400000000>; 827 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 828 pinctrl-0 = <&pinctrl_usdhc3>; 829 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 830 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 831 bus-width = <8>; 832 non-removable; 833 status = "okay"; 834}; 835 836&wdog1 { 837 pinctrl-names = "default"; 838 pinctrl-0 = <&pinctrl_wdog>; 839 fsl,ext-reset-output; 840 status = "okay"; 841}; 842 843&xcvr { 844 #sound-dai-cells = <0>; 845 status = "okay"; 846}; 847 848&iomuxc { 849 pinctrl-names = "default"; 850 pinctrl-0 = <&pinctrl_hog>; 851 852 pinctrl_audio_pwr_reg: audiopwrreggrp { 853 fsl,pins = < 854 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 855 >; 856 }; 857 858 pinctrl_eqos: eqosgrp { 859 fsl,pins = < 860 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 861 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 862 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 863 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 864 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 865 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 866 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 867 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 868 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 869 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 870 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 871 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 872 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 873 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 874 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 875 >; 876 }; 877 878 pinctrl_fec: fecgrp { 879 fsl,pins = < 880 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 881 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 882 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 883 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 884 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 885 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 886 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 887 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 888 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 889 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 890 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 891 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 892 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 893 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 894 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 895 >; 896 }; 897 898 pinctrl_flexcan1: flexcan1grp { 899 fsl,pins = < 900 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 901 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 902 >; 903 }; 904 905 pinctrl_flexcan2: flexcan2grp { 906 fsl,pins = < 907 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 908 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 909 >; 910 }; 911 912 pinctrl_flexcan1_reg: flexcan1reggrp { 913 fsl,pins = < 914 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 915 >; 916 }; 917 918 pinctrl_flexcan2_reg: flexcan2reggrp { 919 fsl,pins = < 920 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 921 >; 922 }; 923 924 pinctrl_flexspi0: flexspi0grp { 925 fsl,pins = < 926 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 927 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 928 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 929 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 930 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 931 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 932 >; 933 }; 934 935 pinctrl_gpio_led: gpioledgrp { 936 fsl,pins = < 937 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 938 >; 939 }; 940 941 pinctrl_hdmi: hdmigrp { 942 fsl,pins = < 943 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 944 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 945 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 946 >; 947 }; 948 949 pinctrl_hog: hoggrp { 950 fsl,pins = < 951 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 952 >; 953 }; 954 955 pinctrl_i2c1: i2c1grp { 956 fsl,pins = < 957 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 958 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 959 >; 960 }; 961 962 pinctrl_i2c2: i2c2grp { 963 fsl,pins = < 964 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 965 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 966 >; 967 }; 968 969 pinctrl_i2c3: i2c3grp { 970 fsl,pins = < 971 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 972 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 973 >; 974 }; 975 976 pinctrl_i2c5: i2c5grp { 977 fsl,pins = < 978 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 979 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 980 >; 981 }; 982 983 pinctrl_lvds_en: lvdsengrp { 984 fsl,pins = < 985 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0 986 >; 987 }; 988 989 pinctrl_pcie0: pcie0grp { 990 fsl,pins = < 991 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 992 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 993 >; 994 }; 995 996 pinctrl_pcie0_reg: pcie0reggrp { 997 fsl,pins = < 998 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 999 >; 1000 }; 1001 1002 pinctrl_pdm: pdmgrp { 1003 fsl,pins = < 1004 MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 1005 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 1006 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 1007 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 1008 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 1009 >; 1010 }; 1011 1012 pinctrl_pmic: pmicgrp { 1013 fsl,pins = < 1014 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 1015 >; 1016 }; 1017 1018 pinctrl_pca6416_int: pca6416_int_grp { 1019 fsl,pins = < 1020 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 1021 >; 1022 }; 1023 1024 pinctrl_pwm1: pwm1grp { 1025 fsl,pins = < 1026 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 1027 >; 1028 }; 1029 1030 pinctrl_pwm2: pwm2grp { 1031 fsl,pins = < 1032 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 1033 >; 1034 }; 1035 1036 pinctrl_pwm4: pwm4grp { 1037 fsl,pins = < 1038 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 1039 >; 1040 }; 1041 1042 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 1043 fsl,pins = < 1044 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 1045 >; 1046 }; 1047 1048 pinctrl_uart1: uart1grp { 1049 fsl,pins = < 1050 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 1051 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 1052 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 1053 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 1054 >; 1055 }; 1056 1057 pinctrl_sai2: sai2grp { 1058 fsl,pins = < 1059 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 1060 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 1061 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 1062 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 1063 >; 1064 }; 1065 1066 pinctrl_sai3: sai3grp { 1067 fsl,pins = < 1068 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 1069 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 1070 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 1071 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 1072 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 1073 >; 1074 }; 1075 1076 pinctrl_uart2: uart2grp { 1077 fsl,pins = < 1078 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 1079 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 1080 >; 1081 }; 1082 1083 pinctrl_usb1_vbus: usb1grp { 1084 fsl,pins = < 1085 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 1086 >; 1087 }; 1088 1089 pinctrl_uart3: uart3grp { 1090 fsl,pins = < 1091 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 1092 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 1093 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 1094 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 1095 >; 1096 }; 1097 1098 pinctrl_usdhc2: usdhc2grp { 1099 fsl,pins = < 1100 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 1101 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 1102 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 1103 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 1104 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 1105 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 1106 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 1107 >; 1108 }; 1109 1110 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1111 fsl,pins = < 1112 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 1113 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 1114 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 1115 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 1116 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 1117 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 1118 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 1119 >; 1120 }; 1121 1122 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1123 fsl,pins = < 1124 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 1125 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 1126 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 1127 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 1128 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 1129 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 1130 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 1131 >; 1132 }; 1133 1134 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 1135 fsl,pins = < 1136 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 1137 >; 1138 }; 1139 1140 pinctrl_usdhc3: usdhc3grp { 1141 fsl,pins = < 1142 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1143 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1144 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1145 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1146 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1147 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1148 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1149 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1150 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1151 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1152 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1153 >; 1154 }; 1155 1156 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1157 fsl,pins = < 1158 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1159 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1160 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1161 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1162 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1163 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1164 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1165 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1166 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1167 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1168 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1169 >; 1170 }; 1171 1172 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1173 fsl,pins = < 1174 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1175 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1176 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1177 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1178 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1179 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1180 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1181 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1182 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1183 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1184 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1185 >; 1186 }; 1187 1188 pinctrl_wdog: wdoggrp { 1189 fsl,pins = < 1190 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 1191 >; 1192 }; 1193}; 1194