1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "NXP i.MX8MPlus EVK board"; 13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 backlight_lvds: backlight-lvds { 20 compatible = "pwm-backlight"; 21 pwms = <&pwm2 0 100000 0>; 22 brightness-levels = <0 100>; 23 num-interpolated-steps = <100>; 24 default-brightness-level = <100>; 25 power-supply = <®_per_12v>; 26 status = "disabled"; 27 }; 28 29 hdmi-connector { 30 compatible = "hdmi-connector"; 31 label = "hdmi"; 32 type = "a"; 33 34 port { 35 hdmi_connector_in: endpoint { 36 remote-endpoint = <&adv7535_out>; 37 }; 38 }; 39 }; 40 41 gpio-leds { 42 compatible = "gpio-leds"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_led>; 45 46 status { 47 label = "yellow:status"; 48 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 49 default-state = "on"; 50 }; 51 }; 52 53 memory@40000000 { 54 device_type = "memory"; 55 reg = <0x0 0x40000000 0 0xc0000000>, 56 <0x1 0x00000000 0 0xc0000000>; 57 }; 58 59 native-hdmi-connector { 60 compatible = "hdmi-connector"; 61 label = "HDMI OUT"; 62 type = "a"; 63 64 port { 65 hdmi_in: endpoint { 66 remote-endpoint = <&hdmi_tx_out>; 67 }; 68 }; 69 }; 70 71 pcie0_refclk: pcie0-refclk { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <100000000>; 75 }; 76 77 reg_audio_3v3: regulator-audio-3v3 { 78 compatible = "regulator-fixed"; 79 regulator-name = "audio-3v3"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 regulator-always-on; 83 regulator-boot-on; 84 }; 85 86 reg_audio_1v8: regulator-audio-1v8 { 87 compatible = "regulator-fixed"; 88 regulator-name = "audio-1v8"; 89 regulator-min-microvolt = <1800000>; 90 regulator-max-microvolt = <1800000>; 91 regulator-always-on; 92 regulator-boot-on; 93 }; 94 95 reg_audio_pwr: regulator-audio-pwr { 96 compatible = "regulator-fixed"; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_audio_pwr_reg>; 99 regulator-name = "audio-pwr"; 100 regulator-min-microvolt = <3300000>; 101 regulator-max-microvolt = <3300000>; 102 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 103 enable-active-high; 104 }; 105 106 reg_can1_stby: regulator-can1-stby { 107 compatible = "regulator-fixed"; 108 regulator-name = "can1-stby"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_flexcan1_reg>; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 114 enable-active-high; 115 }; 116 117 reg_can2_stby: regulator-can2-stby { 118 compatible = "regulator-fixed"; 119 regulator-name = "can2-stby"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_flexcan2_reg>; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 125 enable-active-high; 126 }; 127 128 reg_pcie0: regulator-pcie { 129 compatible = "regulator-fixed"; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_pcie0_reg>; 132 regulator-name = "MPCIE_3V3"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; 136 enable-active-high; 137 }; 138 139 reg_per_12v: regulator-per-12v { 140 compatible = "regulator-fixed"; 141 regulator-name = "PER_12V"; 142 regulator-min-microvolt = <12000000>; 143 regulator-max-microvolt = <12000000>; 144 gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; 145 enable-active-high; 146 }; 147 148 reg_usdhc2_vmmc: regulator-usdhc2 { 149 compatible = "regulator-fixed"; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 152 regulator-name = "VSD_3V3"; 153 regulator-min-microvolt = <3300000>; 154 regulator-max-microvolt = <3300000>; 155 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 156 enable-active-high; 157 }; 158 159 reg_vext_3v3: regulator-vext-3v3 { 160 compatible = "regulator-fixed"; 161 regulator-name = "VEXT_3V3"; 162 regulator-min-microvolt = <3300000>; 163 regulator-max-microvolt = <3300000>; 164 }; 165 166 audio_codec_bt_sco: audio-codec-bt-sco { 167 compatible = "linux,bt-sco"; 168 #sound-dai-cells = <1>; 169 }; 170 171 sound-bt-sco { 172 compatible = "simple-audio-card"; 173 simple-audio-card,name = "bt-sco-audio"; 174 simple-audio-card,format = "dsp_a"; 175 simple-audio-card,bitclock-inversion; 176 simple-audio-card,frame-master = <&btcpu>; 177 simple-audio-card,bitclock-master = <&btcpu>; 178 179 btcpu: simple-audio-card,cpu { 180 sound-dai = <&sai2>; 181 dai-tdm-slot-num = <2>; 182 dai-tdm-slot-width = <16>; 183 }; 184 185 simple-audio-card,codec { 186 sound-dai = <&audio_codec_bt_sco 1>; 187 }; 188 }; 189 190 sound-hdmi { 191 compatible = "fsl,imx-audio-hdmi"; 192 model = "audio-hdmi"; 193 audio-cpu = <&aud2htx>; 194 hdmi-out; 195 }; 196 197 sound-micfil { 198 compatible = "fsl,imx-audio-card"; 199 model = "micfil-audio"; 200 201 pri-dai-link { 202 link-name = "micfil hifi"; 203 format = "i2s"; 204 205 cpu { 206 sound-dai = <&micfil>; 207 }; 208 }; 209 }; 210 211 sound-wm8960 { 212 compatible = "fsl,imx-audio-wm8960"; 213 audio-asrc = <&easrc>; 214 audio-codec = <&wm8960>; 215 audio-cpu = <&sai3>; 216 audio-routing = "Headphone Jack", "HP_L", 217 "Headphone Jack", "HP_R", 218 "Ext Spk", "SPK_LP", 219 "Ext Spk", "SPK_LN", 220 "Ext Spk", "SPK_RP", 221 "Ext Spk", "SPK_RN", 222 "LINPUT1", "Mic Jack", 223 "LINPUT3", "Mic Jack", 224 "Mic Jack", "MICB"; 225 hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 226 model = "wm8960-audio"; 227 pinctrl-0 = <&pinctrl_hpdet>; 228 pinctrl-names = "default"; 229 }; 230 231 sound-xcvr { 232 compatible = "fsl,imx-audio-card"; 233 model = "imx-audio-xcvr"; 234 235 pri-dai-link { 236 link-name = "XCVR PCM"; 237 238 cpu { 239 sound-dai = <&xcvr>; 240 }; 241 }; 242 }; 243 244 reserved-memory { 245 #address-cells = <2>; 246 #size-cells = <2>; 247 ranges; 248 249 dsp_vdev0vring0: vdev0vring0@942f0000 { 250 reg = <0 0x942f0000 0 0x8000>; 251 no-map; 252 }; 253 254 dsp_vdev0vring1: vdev0vring1@942f8000 { 255 reg = <0 0x942f8000 0 0x8000>; 256 no-map; 257 }; 258 259 dsp_vdev0buffer: vdev0buffer@94300000 { 260 compatible = "shared-dma-pool"; 261 reg = <0 0x94300000 0 0x100000>; 262 no-map; 263 }; 264 }; 265}; 266 267&flexspi { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_flexspi0>; 270 status = "okay"; 271 272 flash@0 { 273 compatible = "jedec,spi-nor"; 274 reg = <0>; 275 spi-max-frequency = <80000000>; 276 spi-tx-bus-width = <1>; 277 spi-rx-bus-width = <4>; 278 }; 279}; 280 281&A53_0 { 282 cpu-supply = <®_arm>; 283}; 284 285&A53_1 { 286 cpu-supply = <®_arm>; 287}; 288 289&A53_2 { 290 cpu-supply = <®_arm>; 291}; 292 293&A53_3 { 294 cpu-supply = <®_arm>; 295}; 296 297&aud2htx { 298 status = "okay"; 299}; 300 301&dsp_reserved { 302 status = "okay"; 303}; 304 305&dsp { 306 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, 307 <&dsp_vdev0vring1>, <&dsp_reserved>; 308 status = "okay"; 309}; 310 311&easrc { 312 fsl,asrc-rate = <48000>; 313 status = "okay"; 314}; 315 316&eqos { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_eqos>; 319 phy-mode = "rgmii-id"; 320 phy-handle = <ðphy0>; 321 snps,force_thresh_dma_mode; 322 snps,mtl-tx-config = <&mtl_tx_setup>; 323 snps,mtl-rx-config = <&mtl_rx_setup>; 324 status = "okay"; 325 326 mdio { 327 compatible = "snps,dwmac-mdio"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 ethphy0: ethernet-phy@1 { 332 compatible = "ethernet-phy-ieee802.3-c22"; 333 reg = <1>; 334 eee-broken-1000t; 335 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 336 reset-assert-us = <10000>; 337 reset-deassert-us = <80000>; 338 realtek,clkout-disable; 339 }; 340 }; 341 342 mtl_tx_setup: tx-queues-config { 343 snps,tx-queues-to-use = <5>; 344 345 queue0 { 346 snps,dcb-algorithm; 347 snps,priority = <0x1>; 348 }; 349 350 queue1 { 351 snps,dcb-algorithm; 352 snps,priority = <0x2>; 353 }; 354 355 queue2 { 356 snps,dcb-algorithm; 357 snps,priority = <0x4>; 358 }; 359 360 queue3 { 361 snps,dcb-algorithm; 362 snps,priority = <0x8>; 363 }; 364 365 queue4 { 366 snps,dcb-algorithm; 367 snps,priority = <0xf0>; 368 }; 369 }; 370 371 mtl_rx_setup: rx-queues-config { 372 snps,rx-queues-to-use = <5>; 373 snps,rx-sched-sp; 374 375 queue0 { 376 snps,dcb-algorithm; 377 snps,priority = <0x1>; 378 snps,map-to-dma-channel = <0>; 379 }; 380 381 queue1 { 382 snps,dcb-algorithm; 383 snps,priority = <0x2>; 384 snps,map-to-dma-channel = <1>; 385 }; 386 387 queue2 { 388 snps,dcb-algorithm; 389 snps,priority = <0x4>; 390 snps,map-to-dma-channel = <2>; 391 }; 392 393 queue3 { 394 snps,dcb-algorithm; 395 snps,priority = <0x8>; 396 snps,map-to-dma-channel = <3>; 397 }; 398 399 queue4 { 400 snps,dcb-algorithm; 401 snps,priority = <0xf0>; 402 snps,map-to-dma-channel = <4>; 403 }; 404 }; 405}; 406 407&fec { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_fec>; 410 phy-mode = "rgmii-id"; 411 phy-handle = <ðphy1>; 412 fsl,magic-packet; 413 status = "okay"; 414 415 mdio { 416 #address-cells = <1>; 417 #size-cells = <0>; 418 419 ethphy1: ethernet-phy@1 { 420 compatible = "ethernet-phy-ieee802.3-c22"; 421 reg = <1>; 422 eee-broken-1000t; 423 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 424 reset-assert-us = <10000>; 425 reset-deassert-us = <80000>; 426 realtek,clkout-disable; 427 }; 428 }; 429}; 430 431&flexcan1 { 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_flexcan1>; 434 xceiver-supply = <®_can1_stby>; 435 status = "okay"; 436}; 437 438&flexcan2 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_flexcan2>; 441 xceiver-supply = <®_can2_stby>; 442 status = "disabled";/* can2 pin conflict with pdm */ 443}; 444 445&hdmi_pvi { 446 status = "okay"; 447}; 448 449&hdmi_tx { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_hdmi>; 452 status = "okay"; 453 454 ports { 455 port@1 { 456 hdmi_tx_out: endpoint { 457 remote-endpoint = <&hdmi_in>; 458 }; 459 }; 460 }; 461}; 462 463&hdmi_tx_phy { 464 status = "okay"; 465}; 466 467&i2c1 { 468 clock-frequency = <400000>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_i2c1>; 471 status = "okay"; 472 473 pmic@25 { 474 compatible = "nxp,pca9450c"; 475 reg = <0x25>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_pmic>; 478 interrupt-parent = <&gpio1>; 479 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 480 481 regulators { 482 BUCK1 { 483 regulator-name = "BUCK1"; 484 regulator-min-microvolt = <720000>; 485 regulator-max-microvolt = <1000000>; 486 regulator-boot-on; 487 regulator-always-on; 488 regulator-ramp-delay = <3125>; 489 }; 490 491 reg_arm: BUCK2 { 492 regulator-name = "BUCK2"; 493 regulator-min-microvolt = <720000>; 494 regulator-max-microvolt = <1025000>; 495 regulator-boot-on; 496 regulator-always-on; 497 regulator-ramp-delay = <3125>; 498 nxp,dvs-run-voltage = <950000>; 499 nxp,dvs-standby-voltage = <850000>; 500 }; 501 502 BUCK4 { 503 regulator-name = "BUCK4"; 504 regulator-min-microvolt = <3000000>; 505 regulator-max-microvolt = <3600000>; 506 regulator-boot-on; 507 regulator-always-on; 508 }; 509 510 reg_buck5: BUCK5 { 511 regulator-name = "BUCK5"; 512 regulator-min-microvolt = <1650000>; 513 regulator-max-microvolt = <1950000>; 514 regulator-boot-on; 515 regulator-always-on; 516 }; 517 518 BUCK6 { 519 regulator-name = "BUCK6"; 520 regulator-min-microvolt = <1045000>; 521 regulator-max-microvolt = <1155000>; 522 regulator-boot-on; 523 regulator-always-on; 524 }; 525 526 LDO1 { 527 regulator-name = "LDO1"; 528 regulator-min-microvolt = <1650000>; 529 regulator-max-microvolt = <1950000>; 530 regulator-boot-on; 531 regulator-always-on; 532 }; 533 534 LDO3 { 535 regulator-name = "LDO3"; 536 regulator-min-microvolt = <1710000>; 537 regulator-max-microvolt = <1890000>; 538 regulator-boot-on; 539 regulator-always-on; 540 }; 541 542 LDO5 { 543 regulator-name = "LDO5"; 544 regulator-min-microvolt = <1800000>; 545 regulator-max-microvolt = <3300000>; 546 regulator-boot-on; 547 regulator-always-on; 548 }; 549 }; 550 }; 551}; 552 553&i2c2 { 554 clock-frequency = <400000>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&pinctrl_i2c2>; 557 status = "okay"; 558 559 hdmi@3d { 560 compatible = "adi,adv7535"; 561 reg = <0x3d>; 562 interrupt-parent = <&gpio1>; 563 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 564 adi,dsi-lanes = <4>; 565 avdd-supply = <®_buck5>; 566 dvdd-supply = <®_buck5>; 567 pvdd-supply = <®_buck5>; 568 a2vdd-supply = <®_buck5>; 569 v3p3-supply = <®_vext_3v3>; 570 v1p2-supply = <®_buck5>; 571 572 ports { 573 #address-cells = <1>; 574 #size-cells = <0>; 575 576 port@0 { 577 reg = <0>; 578 579 adv7535_in: endpoint { 580 remote-endpoint = <&dsi_out>; 581 }; 582 }; 583 584 port@1 { 585 reg = <1>; 586 587 adv7535_out: endpoint { 588 remote-endpoint = <&hdmi_connector_in>; 589 }; 590 }; 591 592 }; 593 }; 594}; 595 596&i2c3 { 597 clock-frequency = <400000>; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&pinctrl_i2c3>; 600 status = "okay"; 601 602 wm8960: codec@1a { 603 compatible = "wlf,wm8960"; 604 reg = <0x1a>; 605 #sound-dai-cells = <0>; 606 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; 607 clock-names = "mclk"; 608 wlf,shared-lrclk; 609 wlf,hp-cfg = <3 2 3>; 610 wlf,gpio-cfg = <1 3>; 611 AVDD-supply = <®_audio_3v3>; 612 DBVDD-supply = <®_audio_1v8>; 613 DCVDD-supply = <®_audio_1v8>; 614 SPKVDD1-supply = <®_audio_pwr>; 615 SPKVDD2-supply = <®_audio_pwr>; 616 }; 617 618 pca6416: gpio@20 { 619 compatible = "ti,tca6416"; 620 reg = <0x20>; 621 gpio-controller; 622 #gpio-cells = <2>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&pinctrl_pca6416_int>; 627 interrupt-parent = <&gpio1>; 628 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 629 gpio-line-names = "EXT_PWREN1", 630 "EXT_PWREN2", 631 "CAN1/I2C5_SEL", 632 "PDM/CAN2_SEL", 633 "FAN_EN", 634 "PWR_MEAS_IO1", 635 "PWR_MEAS_IO2", 636 "EXP_P0_7", 637 "EXP_P1_0", 638 "EXP_P1_1", 639 "EXP_P1_2", 640 "EXP_P1_3", 641 "EXP_P1_4", 642 "EXP_P1_5", 643 "EXP_P1_6", 644 "EXP_P1_7"; 645 }; 646}; 647 648/* I2C on expansion connector J22. */ 649&i2c5 { 650 clock-frequency = <100000>; /* Lower clock speed for external bus. */ 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_i2c5>; 653 status = "disabled"; /* can1 pins conflict with i2c5 */ 654 655 /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: 656 * LOW: CAN1 (default, pull-down) 657 * HIGH: I2C5 658 * You need to set it to high to enable I2C5 (for example, add gpio-hog 659 * in pca6416 node). 660 */ 661}; 662 663&lcdif1 { 664 status = "okay"; 665}; 666 667&lcdif3 { 668 status = "okay"; 669}; 670 671&micfil { 672 #sound-dai-cells = <0>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&pinctrl_pdm>; 675 assigned-clocks = <&clk IMX8MP_CLK_PDM>; 676 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 677 assigned-clock-rates = <196608000>; 678 status = "okay"; 679}; 680 681&mipi_dsi { 682 samsung,esc-clock-frequency = <10000000>; 683 status = "okay"; 684 685 ports { 686 port@1 { 687 reg = <1>; 688 689 dsi_out: endpoint { 690 remote-endpoint = <&adv7535_in>; 691 data-lanes = <1 2 3 4>; 692 }; 693 }; 694 }; 695}; 696 697&mu2 { 698 status = "okay"; 699}; 700 701&pcie_phy { 702 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 703 clocks = <&pcie0_refclk>; 704 clock-names = "ref"; 705 status = "okay"; 706}; 707 708&pcie0 { 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pinctrl_pcie0>; 711 reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; 712 vpcie-supply = <®_pcie0>; 713 status = "okay"; 714}; 715 716&pcie0_ep { 717 pinctrl-0 = <&pinctrl_pcie0>; 718 pinctrl-names = "default"; 719 status = "disabled"; 720}; 721 722&pwm1 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_pwm1>; 725 status = "okay"; 726}; 727 728&pwm2 { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_pwm2>; 731 status = "okay"; 732}; 733 734&pwm4 { 735 pinctrl-names = "default"; 736 pinctrl-0 = <&pinctrl_pwm4>; 737 status = "okay"; 738}; 739 740&sai2 { 741 #sound-dai-cells = <0>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&pinctrl_sai2>; 744 assigned-clocks = <&clk IMX8MP_CLK_SAI2>; 745 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 746 assigned-clock-rates = <12288000>; 747 fsl,sai-mclk-direction-output; 748 status = "okay"; 749}; 750 751&sai3 { 752 pinctrl-names = "default"; 753 pinctrl-0 = <&pinctrl_sai3>; 754 assigned-clocks = <&clk IMX8MP_CLK_SAI3>; 755 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 756 assigned-clock-rates = <12288000>; 757 fsl,sai-mclk-direction-output; 758 status = "okay"; 759}; 760 761&snvs_pwrkey { 762 status = "okay"; 763}; 764 765&uart1 { /* BT */ 766 pinctrl-names = "default"; 767 pinctrl-0 = <&pinctrl_uart1>; 768 assigned-clocks = <&clk IMX8MP_CLK_UART1>; 769 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 770 uart-has-rtscts; 771 status = "okay"; 772}; 773 774&uart2 { 775 /* console */ 776 pinctrl-names = "default"; 777 pinctrl-0 = <&pinctrl_uart2>; 778 status = "okay"; 779}; 780 781&usb3_phy1 { 782 status = "okay"; 783}; 784 785&usb3_1 { 786 status = "okay"; 787}; 788 789&usb_dwc3_1 { 790 pinctrl-names = "default"; 791 pinctrl-0 = <&pinctrl_usb1_vbus>; 792 dr_mode = "host"; 793 status = "okay"; 794}; 795 796&uart3 { 797 pinctrl-names = "default"; 798 pinctrl-0 = <&pinctrl_uart3>; 799 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 800 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 801 uart-has-rtscts; 802 status = "okay"; 803}; 804 805&usdhc2 { 806 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 807 assigned-clock-rates = <400000000>; 808 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 809 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 810 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 811 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 812 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 813 vmmc-supply = <®_usdhc2_vmmc>; 814 bus-width = <4>; 815 status = "okay"; 816}; 817 818&usdhc3 { 819 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 820 assigned-clock-rates = <400000000>; 821 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 822 pinctrl-0 = <&pinctrl_usdhc3>; 823 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 824 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 825 bus-width = <8>; 826 non-removable; 827 status = "okay"; 828}; 829 830&wdog1 { 831 pinctrl-names = "default"; 832 pinctrl-0 = <&pinctrl_wdog>; 833 fsl,ext-reset-output; 834 status = "okay"; 835}; 836 837&xcvr { 838 #sound-dai-cells = <0>; 839 status = "okay"; 840}; 841 842&iomuxc { 843 pinctrl-names = "default"; 844 pinctrl-0 = <&pinctrl_hog>; 845 846 pinctrl_audio_pwr_reg: audiopwrreggrp { 847 fsl,pins = < 848 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 849 >; 850 }; 851 852 pinctrl_eqos: eqosgrp { 853 fsl,pins = < 854 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 855 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 856 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 857 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 858 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 859 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 860 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 861 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 862 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 863 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 864 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 865 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 866 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 867 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 868 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 869 >; 870 }; 871 872 pinctrl_fec: fecgrp { 873 fsl,pins = < 874 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 875 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 876 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 877 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 878 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 879 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 880 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 881 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 882 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 883 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 884 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 885 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 886 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 887 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 888 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 889 >; 890 }; 891 892 pinctrl_flexcan1: flexcan1grp { 893 fsl,pins = < 894 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 895 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 896 >; 897 }; 898 899 pinctrl_flexcan2: flexcan2grp { 900 fsl,pins = < 901 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 902 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 903 >; 904 }; 905 906 pinctrl_flexcan1_reg: flexcan1reggrp { 907 fsl,pins = < 908 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ 909 >; 910 }; 911 912 pinctrl_flexcan2_reg: flexcan2reggrp { 913 fsl,pins = < 914 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ 915 >; 916 }; 917 918 pinctrl_flexspi0: flexspi0grp { 919 fsl,pins = < 920 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 921 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 922 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 923 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 924 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 925 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 926 >; 927 }; 928 929 pinctrl_gpio_led: gpioledgrp { 930 fsl,pins = < 931 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 932 >; 933 }; 934 935 pinctrl_hdmi: hdmigrp { 936 fsl,pins = < 937 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 938 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 939 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 940 >; 941 }; 942 943 pinctrl_hog: hoggrp { 944 fsl,pins = < 945 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 946 >; 947 }; 948 949 pinctrl_hpdet: hpdetgrp { 950 fsl,pins = < 951 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0xd6 952 >; 953 }; 954 955 pinctrl_i2c1: i2c1grp { 956 fsl,pins = < 957 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 958 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 959 >; 960 }; 961 962 pinctrl_i2c2: i2c2grp { 963 fsl,pins = < 964 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 965 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 966 >; 967 }; 968 969 pinctrl_i2c3: i2c3grp { 970 fsl,pins = < 971 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 972 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 973 >; 974 }; 975 976 pinctrl_i2c5: i2c5grp { 977 fsl,pins = < 978 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 979 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 980 >; 981 }; 982 983 pinctrl_lvds_en: lvdsengrp { 984 fsl,pins = < 985 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0 986 >; 987 }; 988 989 pinctrl_pcie0: pcie0grp { 990 fsl,pins = < 991 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ 992 MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 993 >; 994 }; 995 996 pinctrl_pcie0_reg: pcie0reggrp { 997 fsl,pins = < 998 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 999 >; 1000 }; 1001 1002 pinctrl_pdm: pdmgrp { 1003 fsl,pins = < 1004 MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 1005 MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 1006 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 1007 MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 1008 MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 1009 >; 1010 }; 1011 1012 pinctrl_pmic: pmicgrp { 1013 fsl,pins = < 1014 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 1015 >; 1016 }; 1017 1018 pinctrl_pca6416_int: pca6416_int_grp { 1019 fsl,pins = < 1020 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ 1021 >; 1022 }; 1023 1024 pinctrl_pwm1: pwm1grp { 1025 fsl,pins = < 1026 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 1027 >; 1028 }; 1029 1030 pinctrl_pwm2: pwm2grp { 1031 fsl,pins = < 1032 MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 1033 >; 1034 }; 1035 1036 pinctrl_pwm4: pwm4grp { 1037 fsl,pins = < 1038 MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 1039 >; 1040 }; 1041 1042 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 1043 fsl,pins = < 1044 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 1045 >; 1046 }; 1047 1048 pinctrl_uart1: uart1grp { 1049 fsl,pins = < 1050 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 1051 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 1052 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 1053 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 1054 >; 1055 }; 1056 1057 pinctrl_sai2: sai2grp { 1058 fsl,pins = < 1059 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 1060 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 1061 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 1062 MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 1063 >; 1064 }; 1065 1066 pinctrl_sai3: sai3grp { 1067 fsl,pins = < 1068 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 1069 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 1070 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 1071 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 1072 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 1073 >; 1074 }; 1075 1076 pinctrl_uart2: uart2grp { 1077 fsl,pins = < 1078 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 1079 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 1080 >; 1081 }; 1082 1083 pinctrl_usb1_vbus: usb1grp { 1084 fsl,pins = < 1085 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 1086 >; 1087 }; 1088 1089 pinctrl_uart3: uart3grp { 1090 fsl,pins = < 1091 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 1092 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 1093 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 1094 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 1095 >; 1096 }; 1097 1098 pinctrl_usdhc2: usdhc2grp { 1099 fsl,pins = < 1100 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 1101 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 1102 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 1103 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 1104 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 1105 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 1106 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 1107 >; 1108 }; 1109 1110 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1111 fsl,pins = < 1112 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 1113 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 1114 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 1115 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 1116 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 1117 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 1118 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 1119 >; 1120 }; 1121 1122 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1123 fsl,pins = < 1124 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 1125 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 1126 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 1127 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 1128 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 1129 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 1130 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 1131 >; 1132 }; 1133 1134 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 1135 fsl,pins = < 1136 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 1137 >; 1138 }; 1139 1140 pinctrl_usdhc3: usdhc3grp { 1141 fsl,pins = < 1142 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1143 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1144 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1145 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1146 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1147 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1148 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1149 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1150 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1151 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1152 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1153 >; 1154 }; 1155 1156 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1157 fsl,pins = < 1158 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1159 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1160 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1161 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1162 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1163 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1164 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1165 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1166 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1167 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1168 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1169 >; 1170 }; 1171 1172 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1173 fsl,pins = < 1174 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1175 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1176 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1177 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1178 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1179 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1180 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1181 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1182 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1183 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1184 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1185 >; 1186 }; 1187 1188 pinctrl_wdog: wdoggrp { 1189 fsl,pins = < 1190 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 1191 >; 1192 }; 1193}; 1194