1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> 4 */ 5 6#include "imx8mp.dtsi" 7 8/ { 9 model = "DH electronics i.MX8M Plus DHCOM SoM"; 10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; 11 12 aliases { 13 ethernet0 = &eqos; 14 ethernet1 = &fec; 15 rtc0 = &rv3032; 16 rtc1 = &snvs_rtc; 17 spi0 = &flexspi; 18 }; 19 20 memory@40000000 { 21 device_type = "memory"; 22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ 23 reg = <0x0 0x40000000 0 0x08000000>; 24 }; 25 26 reg_eth_vio: regulator-eth-vio { 27 compatible = "regulator-fixed"; 28 gpio = <&ioexp 2 GPIO_ACTIVE_LOW>; 29 regulator-always-on; 30 regulator-boot-on; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 regulator-name = "eth_vio"; 34 vin-supply = <&buck4>; 35 }; 36 37 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 38 compatible = "regulator-fixed"; 39 enable-active-high; 40 gpio = <&gpio2 19 0>; /* SD2_RESET */ 41 off-on-delay-us = <12000>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 44 regulator-max-microvolt = <3300000>; 45 regulator-min-microvolt = <3300000>; 46 regulator-name = "VDD_3V3_SD"; 47 startup-delay-us = <100>; 48 vin-supply = <&buck4>; 49 }; 50 51 reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */ 52 compatible = "regulator-fixed"; 53 regulator-always-on; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 regulator-name = "VDD_3P3V_AWO"; 57 }; 58 59 wlan_pwrseq: wifi-pwrseq { 60 compatible = "mmc-pwrseq-simple"; 61 reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>; 62 }; 63}; 64 65&A53_0 { 66 cpu-supply = <&buck2>; 67}; 68 69&A53_1 { 70 cpu-supply = <&buck2>; 71}; 72 73&A53_2 { 74 cpu-supply = <&buck2>; 75}; 76 77&A53_3 { 78 cpu-supply = <&buck2>; 79}; 80 81&audio_blk_ctrl { 82 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>; 83 assigned-clock-rates = <393216000>; 84}; 85 86&ecspi1 { 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_ecspi1>; 89 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 90 status = "disabled"; 91}; 92 93&ecspi2 { 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_ecspi2>; 96 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 97 status = "disabled"; 98}; 99 100&eqos { /* First ethernet */ 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_eqos_rgmii>; 103 phy-handle = <ðphy0g>; 104 phy-mode = "rgmii-id"; 105 status = "okay"; 106 107 mdio { 108 compatible = "snps,dwmac-mdio"; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 112 /* Up to one of these two PHYs may be populated. */ 113 ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 114 compatible = "ethernet-phy-id0007.c110", 115 "ethernet-phy-ieee802.3-c22"; 116 interrupt-parent = <&gpio3>; 117 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 118 pinctrl-0 = <&pinctrl_ethphy0>; 119 pinctrl-names = "default"; 120 reg = <1>; 121 reset-assert-us = <1000>; 122 reset-deassert-us = <1000>; 123 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; 124 /* Non-default PHY population option. */ 125 status = "disabled"; 126 }; 127 128 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ 129 compatible = "ethernet-phy-id0022.1642", 130 "ethernet-phy-ieee802.3-c22"; 131 interrupt-parent = <&gpio3>; 132 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 133 micrel,led-mode = <0>; 134 pinctrl-0 = <&pinctrl_ethphy0>; 135 pinctrl-names = "default"; 136 reg = <5>; 137 reset-assert-us = <1000>; 138 reset-deassert-us = <1000>; 139 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; 140 /* Default PHY population option. */ 141 status = "okay"; 142 }; 143 }; 144}; 145 146&fec { /* Second ethernet */ 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_fec_rmii>; 149 phy-handle = <ðphy1f>; 150 phy-mode = "rmii"; 151 fsl,magic-packet; 152 status = "okay"; 153 154 mdio { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 /* Up to one PHY may be populated. */ 159 ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */ 160 compatible = "ethernet-phy-id0007.c110", 161 "ethernet-phy-ieee802.3-c22"; 162 interrupt-parent = <&gpio4>; 163 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 164 pinctrl-0 = <&pinctrl_ethphy1>; 165 pinctrl-names = "default"; 166 reg = <2>; 167 reset-assert-us = <1000>; 168 reset-deassert-us = <1000>; 169 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 170 /* Non-default PHY population option. */ 171 status = "disabled"; 172 }; 173 }; 174}; 175 176&flexcan1 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_flexcan1>; 179 status = "disabled"; 180}; 181 182&flexcan2 { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_flexcan2>; 185 status = "disabled"; 186}; 187 188&flexspi { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_flexspi>; 191 status = "okay"; 192 193 flash@0 { /* W25Q128JWPIM */ 194 compatible = "jedec,spi-nor"; 195 reg = <0>; 196 spi-max-frequency = <80000000>; 197 spi-tx-bus-width = <4>; 198 spi-rx-bus-width = <4>; 199 }; 200}; 201 202&gpio1 { 203 gpio-line-names = 204 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", 205 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", 206 "", "", "", "", "", "", "", "", 207 "", "", "", "", "", "", "", ""; 208}; 209 210&gpio2 { 211 gpio-line-names = 212 "", "", "", "", "", "", "", "", 213 "", "", "", "DHCOM-K", "", "", "", "", 214 "", "", "", "", "DHCOM-INT", "", "", "", 215 "", "", "", "", "", "", "", ""; 216}; 217 218&gpio3 { 219 gpio-line-names = 220 "", "", "", "", "", "", "", "", 221 "", "", "", "", "", "", "SOM-HW0", "", 222 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", 223 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; 224}; 225 226&gpio4 { 227 gpio-line-names = 228 "", "", "", "", "", "", "", "", 229 "", "", "", "", "", "", "", "", 230 "", "", "", "SOM-HW1", "", "", "", "", 231 "", "", "", "DHCOM-D", "", "", "", ""; 232}; 233 234&gpio5 { 235 gpio-line-names = 236 "", "", "DHCOM-C", "", "", "", "", "", 237 "", "", "", "", "", "", "", "", 238 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", 239 "", "", "", "", "", "", "", ""; 240}; 241 242&i2c3 { 243 clock-frequency = <100000>; 244 pinctrl-names = "default", "gpio"; 245 pinctrl-0 = <&pinctrl_i2c3>; 246 pinctrl-1 = <&pinctrl_i2c3_gpio>; 247 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 248 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 249 status = "okay"; 250 251 tc_bridge: bridge@f { 252 compatible = "toshiba,tc9595", "toshiba,tc358767"; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_tc9595>; 255 reg = <0xf>; 256 clock-names = "ref"; 257 clocks = <&clk IMX8MP_CLK_CLKOUT2>; 258 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>, 259 <&clk IMX8MP_CLK_CLKOUT2>, 260 <&clk IMX8MP_AUDIO_PLL2_OUT>; 261 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; 262 assigned-clock-rates = <13000000>, <13000000>, <208000000>; 263 reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 264 status = "disabled"; 265 266 ports { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 270 port@0 { 271 reg = <0>; 272 273 tc_bridge_in: endpoint { 274 data-lanes = <1 2 3 4>; 275 remote-endpoint = <&dsi_out>; 276 }; 277 }; 278 }; 279 }; 280 281 pmic: pmic@25 { 282 compatible = "nxp,pca9450c"; 283 reg = <0x25>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_pmic>; 286 interrupt-parent = <&gpio1>; 287 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 288 289 /* 290 * i.MX 8M Plus Data Sheet for Consumer Products 291 * 3.1.4 Operating ranges 292 * MIMX8ML8CVNKZAB 293 */ 294 regulators { 295 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 296 regulator-min-microvolt = <850000>; 297 regulator-max-microvolt = <1000000>; 298 regulator-ramp-delay = <3125>; 299 regulator-always-on; 300 regulator-boot-on; 301 }; 302 303 buck2: BUCK2 { /* VDD_ARM */ 304 nxp,dvs-run-voltage = <950000>; 305 nxp,dvs-standby-voltage = <850000>; 306 regulator-min-microvolt = <850000>; 307 regulator-max-microvolt = <1000000>; 308 regulator-ramp-delay = <3125>; 309 regulator-always-on; 310 regulator-boot-on; 311 }; 312 313 buck4: BUCK4 { /* VDD_3V3 */ 314 regulator-min-microvolt = <3300000>; 315 regulator-max-microvolt = <3300000>; 316 regulator-always-on; 317 regulator-boot-on; 318 }; 319 320 buck5: BUCK5 { /* VDD_1V8 */ 321 regulator-min-microvolt = <1800000>; 322 regulator-max-microvolt = <1800000>; 323 regulator-always-on; 324 regulator-boot-on; 325 }; 326 327 buck6: BUCK6 { /* NVCC_DRAM_1V1 */ 328 regulator-min-microvolt = <1100000>; 329 regulator-max-microvolt = <1100000>; 330 regulator-always-on; 331 regulator-boot-on; 332 }; 333 334 ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 335 regulator-min-microvolt = <1800000>; 336 regulator-max-microvolt = <1800000>; 337 regulator-always-on; 338 regulator-boot-on; 339 }; 340 341 ldo3: LDO3 { /* VDDA_1V8 */ 342 regulator-min-microvolt = <1800000>; 343 regulator-max-microvolt = <1800000>; 344 regulator-always-on; 345 regulator-boot-on; 346 }; 347 348 ldo4: LDO4 { /* PMIC_LDO4 */ 349 regulator-min-microvolt = <3300000>; 350 regulator-max-microvolt = <3300000>; 351 }; 352 353 ldo5: LDO5 { /* NVCC_SD2 */ 354 regulator-min-microvolt = <1800000>; 355 regulator-max-microvolt = <3300000>; 356 }; 357 }; 358 }; 359 360 adc@48 { 361 compatible = "ti,ads1015"; 362 reg = <0x48>; 363 interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 367 channel@0 { /* Voltage over AIN0 and AIN1. */ 368 reg = <0>; 369 }; 370 371 channel@1 { /* Voltage over AIN0 and AIN3. */ 372 reg = <1>; 373 }; 374 375 channel@2 { /* Voltage over AIN1 and AIN3. */ 376 reg = <2>; 377 }; 378 379 channel@3 { /* Voltage over AIN2 and AIN3. */ 380 reg = <3>; 381 }; 382 383 channel@4 { /* Voltage over AIN0 and GND. */ 384 reg = <4>; 385 }; 386 387 channel@5 { /* Voltage over AIN1 and GND. */ 388 reg = <5>; 389 }; 390 391 channel@6 { /* Voltage over AIN2 and GND. */ 392 reg = <6>; 393 }; 394 395 channel@7 { /* Voltage over AIN3 and GND. */ 396 reg = <7>; 397 }; 398 }; 399 400 touchscreen@49 { 401 compatible = "ti,tsc2004"; 402 reg = <0x49>; 403 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&pinctrl_touch>; 406 vio-supply = <&buck4>; 407 }; 408 409 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ 410 compatible = "atmel,24c32"; /* M24C32-D */ 411 pagesize = <32>; 412 reg = <0x50>; 413 }; 414 415 rv3032: rtc@51 { 416 compatible = "microcrystal,rv3032"; 417 reg = <0x51>; 418 interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>; 419 wakeup-source; 420 }; 421 422 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ 423 compatible = "atmel,24c32"; /* M24C32-D */ 424 pagesize = <32>; 425 reg = <0x53>; 426 }; 427 428 eeprom0wl: eeprom@58 { 429 compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */ 430 pagesize = <32>; 431 reg = <0x58>; 432 }; 433 434 eeprom1wl: eeprom@5b { 435 compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */ 436 pagesize = <32>; 437 reg = <0x5b>; 438 }; 439 440 ioexp: gpio@74 { 441 compatible = "nxp,pca9539"; 442 reg = <0x74>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_ioexp>; 450 wakeup-source; 451 452 gpio-line-names = 453 "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT", 454 "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY", 455 "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", 456 "BT_HOST_WAKE", "BT_DEV_WAKE", "", ""; 457 }; 458}; 459 460&i2c4 { 461 clock-frequency = <100000>; 462 pinctrl-names = "default", "gpio"; 463 pinctrl-0 = <&pinctrl_i2c4>; 464 pinctrl-1 = <&pinctrl_i2c4_gpio>; 465 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 466 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 467 status = "okay"; 468}; 469 470&i2c5 { /* HDMI EDID bus */ 471 clock-frequency = <100000>; 472 pinctrl-names = "default", "gpio"; 473 pinctrl-0 = <&pinctrl_i2c5>; 474 pinctrl-1 = <&pinctrl_i2c5_gpio>; 475 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 476 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 477 status = "okay"; 478}; 479 480&mipi_dsi { 481 samsung,burst-clock-frequency = <160000000>; 482 samsung,esc-clock-frequency = <10000000>; 483 484 ports { 485 port@1 { 486 reg = <1>; 487 488 dsi_out: endpoint { 489 data-lanes = <1 2 3 4>; 490 remote-endpoint = <&tc_bridge_in>; 491 }; 492 }; 493 }; 494}; 495 496&pwm1 { 497 pinctrl-0 = <&pinctrl_pwm1>; 498 pinctrl-names = "default"; 499 status = "disabled"; 500}; 501 502&uart1 { 503 /* CA53 console */ 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_uart1>; 506 status = "okay"; 507 wakeup-source; 508}; 509 510&uart2 { 511 /* Bluetooth */ 512 pinctrl-names = "default"; 513 pinctrl-0 = <&pinctrl_uart2>; 514 uart-has-rtscts; 515 status = "okay"; 516 517 /* 518 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock, 519 * which with 16x oversampling yields 5 Mbdps baud base, 520 * which can be well divided by 5/4 to achieve 4 Mbdps, 521 * which is exactly the maximum rate supported by muRata 522 * 2AE bluetooth UART. 523 */ 524 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 525 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 526 assigned-clock-rates = <80000000>; 527 528 bluetooth { 529 compatible = "cypress,cyw4373a0-bt"; 530 shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>; 531 max-speed = <4000000>; 532 }; 533}; 534 535&uart3 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_uart3>; 538 uart-has-rtscts; 539 status = "okay"; 540}; 541 542&uart4 { 543 pinctrl-names = "default"; 544 pinctrl-0 = <&pinctrl_uart4>; 545 status = "okay"; 546}; 547 548&usb3_phy0 { 549 status = "okay"; 550}; 551 552&usb3_0 { 553 status = "okay"; 554}; 555 556&usb_dwc3_0 { 557 dr_mode = "otg"; 558 status = "okay"; 559}; 560 561&usb3_phy1 { 562 status = "okay"; 563}; 564 565&usb3_1 { 566 status = "okay"; 567}; 568 569&usb_dwc3_1 { 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_usb1_vbus>; 572 dr_mode = "host"; 573 status = "okay"; 574}; 575 576/* SDIO WiFi */ 577&usdhc1 { 578 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 579 pinctrl-0 = <&pinctrl_usdhc1>; 580 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 581 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 582 mmc-pwrseq = <&wlan_pwrseq>; 583 vmmc-supply = <&buck4>; 584 bus-width = <4>; 585 non-removable; 586 cap-power-off-card; 587 keep-power-in-suspend; 588 status = "okay"; 589 590 #address-cells = <1>; 591 #size-cells = <0>; 592 593 brcmf: bcrmf@1 { /* muRata 2AE */ 594 reg = <1>; 595 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 596 /* 597 * The "host-wake" interrupt output is by default not 598 * connected to the SoC, but can be connected on to 599 * SoC pin on the carrier board. 600 */ 601 }; 602}; 603 604/* SD slot */ 605&usdhc2 { 606 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 607 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 608 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 609 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 610 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 611 vmmc-supply = <®_usdhc2_vmmc>; 612 bus-width = <4>; 613 status = "okay"; 614}; 615 616/* eMMC */ 617&usdhc3 { 618 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 619 pinctrl-0 = <&pinctrl_usdhc3>; 620 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 621 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 622 vmmc-supply = <&buck4>; 623 vqmmc-supply = <&buck5>; 624 bus-width = <8>; 625 non-removable; 626 status = "okay"; 627}; 628 629&wdog1 { 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pinctrl_wdog>; 632 fsl,ext-reset-output; 633 status = "okay"; 634}; 635 636&iomuxc { 637 pinctrl-0 = <&pinctrl_hog_base 638 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 639 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 640 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i 641 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l 642 &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o 643 &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r 644 &pinctrl_dhcom_s &pinctrl_dhcom_int>; 645 pinctrl-names = "default"; 646 647 pinctrl_dhcom_a: dhcom-a-grp { 648 fsl,pins = < 649 /* ENET_QOS_EVENT0-OUT */ 650 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 651 >; 652 }; 653 654 pinctrl_dhcom_b: dhcom-b-grp { 655 fsl,pins = < 656 /* ENET_QOS_EVENT0-IN */ 657 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 658 >; 659 }; 660 661 pinctrl_dhcom_c: dhcom-c-grp { 662 fsl,pins = < 663 /* GPIO_C */ 664 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 665 >; 666 }; 667 668 pinctrl_dhcom_d: dhcom-d-grp { 669 fsl,pins = < 670 /* GPIO_D */ 671 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 672 >; 673 }; 674 675 pinctrl_dhcom_e: dhcom-e-grp { 676 fsl,pins = < 677 /* GPIO_E */ 678 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 679 >; 680 }; 681 682 pinctrl_dhcom_f: dhcom-f-grp { 683 fsl,pins = < 684 /* GPIO_F */ 685 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 686 >; 687 }; 688 689 pinctrl_dhcom_g: dhcom-g-grp { 690 fsl,pins = < 691 /* GPIO_G */ 692 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 693 >; 694 }; 695 696 pinctrl_dhcom_h: dhcom-h-grp { 697 fsl,pins = < 698 /* GPIO_H */ 699 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 700 >; 701 }; 702 703 pinctrl_dhcom_i: dhcom-i-grp { 704 fsl,pins = < 705 /* CSI1_SYNC */ 706 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 707 >; 708 }; 709 710 pinctrl_dhcom_j: dhcom-j-grp { 711 fsl,pins = < 712 /* CSIx_#RST */ 713 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 714 >; 715 }; 716 717 pinctrl_dhcom_k: dhcom-k-grp { 718 fsl,pins = < 719 /* CSIx_PWDN */ 720 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 721 >; 722 }; 723 724 pinctrl_dhcom_l: dhcom-l-grp { 725 fsl,pins = < 726 /* CSI2_SYNC */ 727 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 728 >; 729 }; 730 731 pinctrl_dhcom_m: dhcom-m-grp { 732 fsl,pins = < 733 /* CSIx_MCLK */ 734 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2 735 >; 736 }; 737 738 pinctrl_dhcom_n: dhcom-n-grp { 739 fsl,pins = < 740 /* CSI2_D3- */ 741 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2 742 >; 743 }; 744 745 pinctrl_dhcom_o: dhcom-o-grp { 746 fsl,pins = < 747 /* CSI2_D3+ */ 748 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2 749 >; 750 }; 751 752 pinctrl_dhcom_p: dhcom-p-grp { 753 fsl,pins = < 754 /* CSI2_D2- */ 755 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2 756 >; 757 }; 758 759 pinctrl_dhcom_q: dhcom-q-grp { 760 fsl,pins = < 761 /* CSI2_D2+ */ 762 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2 763 >; 764 }; 765 766 pinctrl_dhcom_r: dhcom-r-grp { 767 fsl,pins = < 768 /* CSI2_D1- */ 769 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2 770 >; 771 }; 772 773 pinctrl_dhcom_s: dhcom-s-grp { 774 fsl,pins = < 775 /* CSI2_D1+ */ 776 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2 777 >; 778 }; 779 780 pinctrl_dhcom_int: dhcom-int-grp { 781 fsl,pins = < 782 /* INT_HIGHEST_PRIO */ 783 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 784 >; 785 }; 786 787 pinctrl_hog_base: dhcom-hog-base-grp { 788 fsl,pins = < 789 /* GPIOs for memory coding */ 790 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 791 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 792 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 793 /* GPIOs for hardware coding */ 794 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 795 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 796 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 797 >; 798 }; 799 800 pinctrl_ecspi1: dhcom-ecspi1-grp { 801 fsl,pins = < 802 MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44 803 MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44 804 MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44 805 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40 806 >; 807 }; 808 809 pinctrl_ecspi2: dhcom-ecspi2-grp { 810 fsl,pins = < 811 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 812 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 813 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 814 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 815 >; 816 }; 817 818 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */ 819 fsl,pins = < 820 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 821 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 822 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 823 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 824 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 825 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 826 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 827 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 828 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 829 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 830 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 831 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 832 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 833 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 834 >; 835 }; 836 837 pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */ 838 fsl,pins = < 839 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 840 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 841 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 842 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 843 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 844 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f 845 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 846 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 847 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 848 /* Clock */ 849 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f 850 >; 851 }; 852 853 pinctrl_ethphy0: dhcom-ethphy0-grp { 854 fsl,pins = < 855 /* ENET_QOS_#INT Interrupt */ 856 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 857 >; 858 }; 859 860 pinctrl_ethphy1: dhcom-ethphy1-grp { 861 fsl,pins = < 862 /* ENET1_#RST Reset */ 863 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 864 /* ENET1_#INT Interrupt */ 865 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 866 >; 867 }; 868 869 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */ 870 fsl,pins = < 871 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f 872 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 873 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 874 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 875 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 876 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 877 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 878 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 879 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 880 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 881 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 882 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 883 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 884 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 885 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 886 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f 887 >; 888 }; 889 890 pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */ 891 fsl,pins = < 892 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 893 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 894 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 895 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 896 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 897 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91 898 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 899 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 900 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 901 /* Clock */ 902 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f 903 >; 904 }; 905 906 pinctrl_flexcan1: dhcom-flexcan1-grp { 907 fsl,pins = < 908 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 909 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 910 >; 911 }; 912 913 pinctrl_flexcan2: dhcom-flexcan2-grp { 914 fsl,pins = < 915 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 916 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 917 >; 918 }; 919 920 pinctrl_flexspi: dhcom-flexspi-grp { 921 fsl,pins = < 922 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 923 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 924 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 925 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 926 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 927 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 928 >; 929 }; 930 931 pinctrl_hdmi: dhcom-hdmi-grp { 932 fsl,pins = < 933 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 934 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 935 >; 936 }; 937 938 pinctrl_i2c3: dhcom-i2c3-grp { 939 fsl,pins = < 940 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 941 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 942 >; 943 }; 944 945 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { 946 fsl,pins = < 947 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 948 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 949 >; 950 }; 951 952 pinctrl_i2c4: dhcom-i2c4-grp { 953 fsl,pins = < 954 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 955 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 956 >; 957 }; 958 959 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { 960 fsl,pins = < 961 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 962 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 963 >; 964 }; 965 966 pinctrl_i2c5: dhcom-i2c5-grp { 967 fsl,pins = < 968 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 969 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 970 >; 971 }; 972 973 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { 974 fsl,pins = < 975 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 976 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 977 >; 978 }; 979 980 pinctrl_ioexp: dhcom-ioexp-grp { 981 fsl,pins = < 982 /* #GPIO_EXP_INT */ 983 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 984 >; 985 }; 986 987 pinctrl_pmic: dhcom-pmic-grp { 988 fsl,pins = < 989 /* PMIC_nINT */ 990 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 991 >; 992 }; 993 994 pinctrl_pwm1: dhcom-pwm1-grp { 995 fsl,pins = < 996 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 997 >; 998 }; 999 1000 pinctrl_tc9595: dhcom-tc9595-grp { 1001 fsl,pins = < 1002 /* RESET_DSIBRIDGE */ 1003 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 1004 /* DSI-CONV_INT Interrupt */ 1005 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 1006 >; 1007 }; 1008 1009 pinctrl_sai3: dhcom-sai3-grp { 1010 fsl,pins = < 1011 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 1012 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 1013 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 1014 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 1015 >; 1016 }; 1017 1018 pinctrl_touch: dhcom-touch-grp { 1019 fsl,pins = < 1020 /* #TOUCH_INT */ 1021 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 1022 >; 1023 }; 1024 1025 pinctrl_uart1: dhcom-uart1-grp { 1026 fsl,pins = < 1027 /* Console UART */ 1028 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 1029 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 1030 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 1031 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 1032 >; 1033 }; 1034 1035 pinctrl_uart2: dhcom-uart2-grp { 1036 fsl,pins = < 1037 /* Bluetooth UART */ 1038 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 1039 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 1040 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 1041 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 1042 >; 1043 }; 1044 1045 pinctrl_uart3: dhcom-uart3-grp { 1046 fsl,pins = < 1047 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 1048 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 1049 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 1050 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 1051 >; 1052 }; 1053 1054 pinctrl_uart4: dhcom-uart4-grp { 1055 fsl,pins = < 1056 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 1057 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 1058 >; 1059 }; 1060 1061 pinctrl_usb1_vbus: dhcom-usb1-grp { 1062 fsl,pins = < 1063 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 1064 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 1065 >; 1066 }; 1067 1068 pinctrl_usdhc1: dhcom-usdhc1-grp { 1069 fsl,pins = < 1070 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 1071 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 1072 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 1073 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 1074 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 1075 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 1076 >; 1077 }; 1078 1079 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { 1080 fsl,pins = < 1081 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 1082 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 1083 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 1084 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 1085 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 1086 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 1087 >; 1088 }; 1089 1090 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { 1091 fsl,pins = < 1092 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 1093 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 1094 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 1095 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 1096 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 1097 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 1098 >; 1099 }; 1100 1101 pinctrl_usdhc2: dhcom-usdhc2-grp { 1102 fsl,pins = < 1103 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 1104 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 1105 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 1106 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 1107 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 1108 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 1109 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1110 >; 1111 }; 1112 1113 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { 1114 fsl,pins = < 1115 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 1116 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 1117 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 1118 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 1119 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 1120 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 1121 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1122 >; 1123 }; 1124 1125 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { 1126 fsl,pins = < 1127 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 1128 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 1129 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 1130 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 1131 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 1132 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 1133 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1134 >; 1135 }; 1136 1137 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { 1138 fsl,pins = < 1139 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 1140 >; 1141 }; 1142 1143 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { 1144 fsl,pins = < 1145 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 1146 >; 1147 }; 1148 1149 pinctrl_usdhc3: dhcom-usdhc3-grp { 1150 fsl,pins = < 1151 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1152 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1153 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1154 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1155 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1156 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1157 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1158 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1159 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1160 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1161 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1162 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1163 >; 1164 }; 1165 1166 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { 1167 fsl,pins = < 1168 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1169 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1170 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1171 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1172 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1173 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1174 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1175 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1176 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1177 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1178 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1179 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1180 >; 1181 }; 1182 1183 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { 1184 fsl,pins = < 1185 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1186 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1187 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1188 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1189 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1190 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1191 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1192 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1193 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1194 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1195 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1196 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1197 >; 1198 }; 1199 1200 pinctrl_wdog: dhcom-wdog-grp { 1201 fsl,pins = < 1202 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 1203 >; 1204 }; 1205}; 1206