1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de> 4 */ 5 6#include "imx8mp.dtsi" 7 8/ { 9 model = "DH electronics i.MX8M Plus DHCOM SoM"; 10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp"; 11 12 aliases { 13 ethernet0 = &eqos; 14 ethernet1 = &fec; 15 rtc0 = &rv3032; 16 rtc1 = &snvs_rtc; 17 spi0 = &flexspi; 18 }; 19 20 memory@40000000 { 21 device_type = "memory"; 22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */ 23 reg = <0x0 0x40000000 0 0x08000000>; 24 }; 25 26 reg_eth_vio: regulator-eth-vio { 27 compatible = "regulator-fixed"; 28 gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; 29 pinctrl-0 = <&pinctrl_enet_vio>; 30 pinctrl-names = "default"; 31 regulator-always-on; 32 regulator-boot-on; 33 regulator-min-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>; 35 regulator-name = "eth_vio"; 36 vin-supply = <&buck4>; 37 }; 38 39 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 40 compatible = "regulator-fixed"; 41 enable-active-high; 42 gpio = <&gpio2 19 0>; /* SD2_RESET */ 43 off-on-delay-us = <12000>; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 46 regulator-max-microvolt = <3300000>; 47 regulator-min-microvolt = <3300000>; 48 regulator-name = "VDD_3V3_SD"; 49 startup-delay-us = <100>; 50 vin-supply = <&buck4>; 51 }; 52}; 53 54&A53_0 { 55 cpu-supply = <&buck2>; 56}; 57 58&A53_1 { 59 cpu-supply = <&buck2>; 60}; 61 62&A53_2 { 63 cpu-supply = <&buck2>; 64}; 65 66&A53_3 { 67 cpu-supply = <&buck2>; 68}; 69 70&ecspi1 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_ecspi1>; 73 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; 74 status = "disabled"; 75}; 76 77&ecspi2 { 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_ecspi2>; 80 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 81 status = "disabled"; 82}; 83 84&eqos { /* First ethernet */ 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_eqos_rgmii>; 87 phy-handle = <ðphy0g>; 88 phy-mode = "rgmii-id"; 89 status = "okay"; 90 91 mdio { 92 compatible = "snps,dwmac-mdio"; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 /* Up to one of these two PHYs may be populated. */ 97 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */ 98 compatible = "ethernet-phy-id0007.c110", 99 "ethernet-phy-ieee802.3-c22"; 100 interrupt-parent = <&gpio3>; 101 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 102 pinctrl-0 = <&pinctrl_ethphy0>; 103 pinctrl-names = "default"; 104 reg = <0>; 105 reset-assert-us = <1000>; 106 reset-deassert-us = <1000>; 107 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 108 /* Non-default PHY population option. */ 109 status = "disabled"; 110 }; 111 112 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */ 113 compatible = "ethernet-phy-id0022.1642", 114 "ethernet-phy-ieee802.3-c22"; 115 interrupt-parent = <&gpio3>; 116 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 117 micrel,led-mode = <0>; 118 pinctrl-0 = <&pinctrl_ethphy0>; 119 pinctrl-names = "default"; 120 reg = <5>; 121 reset-assert-us = <1000>; 122 reset-deassert-us = <1000>; 123 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 124 /* Default PHY population option. */ 125 status = "okay"; 126 }; 127 }; 128}; 129 130&fec { /* Second ethernet */ 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_fec_rmii>; 133 phy-handle = <ðphy1f>; 134 phy-mode = "rmii"; 135 fsl,magic-packet; 136 status = "okay"; 137 138 mdio { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 142 /* Up to one PHY may be populated. */ 143 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 144 compatible = "ethernet-phy-id0007.c110", 145 "ethernet-phy-ieee802.3-c22"; 146 interrupt-parent = <&gpio4>; 147 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 148 pinctrl-0 = <&pinctrl_ethphy1>; 149 pinctrl-names = "default"; 150 reg = <1>; 151 reset-assert-us = <1000>; 152 reset-deassert-us = <1000>; 153 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 154 /* Non-default PHY population option. */ 155 status = "disabled"; 156 }; 157 }; 158}; 159 160&flexcan1 { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_flexcan1>; 163 status = "disabled"; 164}; 165 166&flexcan2 { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_flexcan2>; 169 status = "disabled"; 170}; 171 172&flexspi { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_flexspi>; 175 status = "okay"; 176 177 flash@0 { /* W25Q128JWPIM */ 178 compatible = "jedec,spi-nor"; 179 reg = <0>; 180 spi-max-frequency = <80000000>; 181 spi-tx-bus-width = <4>; 182 spi-rx-bus-width = <4>; 183 }; 184}; 185 186&gpio1 { 187 gpio-line-names = 188 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L", 189 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "", 190 "", "", "", "", "", "", "", "", 191 "", "", "", "", "", "", "", ""; 192}; 193 194&gpio2 { 195 gpio-line-names = 196 "", "", "", "", "", "", "", "", 197 "", "", "", "DHCOM-K", "", "", "", "", 198 "", "", "", "", "DHCOM-INT", "", "", "", 199 "", "", "", "", "", "", "", ""; 200}; 201 202&gpio3 { 203 gpio-line-names = 204 "", "", "", "", "", "", "", "", 205 "", "", "", "", "", "", "SOM-HW0", "", 206 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1", 207 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", ""; 208}; 209 210&gpio4 { 211 gpio-line-names = 212 "", "", "", "", "", "", "", "", 213 "", "", "", "", "", "", "", "", 214 "", "", "", "SOM-HW1", "", "", "", "", 215 "", "", "", "DHCOM-D", "", "", "", ""; 216}; 217 218&gpio5 { 219 gpio-line-names = 220 "", "", "DHCOM-C", "", "", "", "", "", 221 "", "", "", "", "", "", "", "", 222 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F", 223 "", "", "", "", "", "", "", ""; 224}; 225 226&i2c3 { 227 clock-frequency = <100000>; 228 pinctrl-names = "default", "gpio"; 229 pinctrl-0 = <&pinctrl_i2c3>; 230 pinctrl-1 = <&pinctrl_i2c3_gpio>; 231 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 232 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 233 status = "okay"; 234 235 tc_bridge: bridge@f { 236 compatible = "toshiba,tc9595", "toshiba,tc358767"; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_tc9595>; 239 reg = <0xf>; 240 clock-names = "ref"; 241 clocks = <&clk IMX8MP_CLK_CLKOUT2>; 242 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>, 243 <&clk IMX8MP_CLK_CLKOUT2>, 244 <&clk IMX8MP_AUDIO_PLL2_OUT>; 245 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; 246 assigned-clock-rates = <13000000>, <13000000>, <156000000>; 247 reset-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 248 status = "disabled"; 249 250 ports { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 254 port@0 { 255 reg = <0>; 256 257 tc_bridge_in: endpoint { 258 data-lanes = <1 2 3 4>; 259 remote-endpoint = <&dsi_out>; 260 }; 261 }; 262 }; 263 }; 264 265 pmic: pmic@25 { 266 compatible = "nxp,pca9450c"; 267 reg = <0x25>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_pmic>; 270 interrupt-parent = <&gpio1>; 271 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 272 273 /* 274 * i.MX 8M Plus Data Sheet for Consumer Products 275 * 3.1.4 Operating ranges 276 * MIMX8ML8CVNKZAB 277 */ 278 regulators { 279 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 280 regulator-min-microvolt = <850000>; 281 regulator-max-microvolt = <1000000>; 282 regulator-ramp-delay = <3125>; 283 regulator-always-on; 284 regulator-boot-on; 285 }; 286 287 buck2: BUCK2 { /* VDD_ARM */ 288 regulator-min-microvolt = <850000>; 289 regulator-max-microvolt = <1000000>; 290 regulator-ramp-delay = <3125>; 291 regulator-always-on; 292 regulator-boot-on; 293 }; 294 295 buck4: BUCK4 { /* VDD_3V3 */ 296 regulator-min-microvolt = <3300000>; 297 regulator-max-microvolt = <3300000>; 298 regulator-always-on; 299 regulator-boot-on; 300 }; 301 302 buck5: BUCK5 { /* VDD_1V8 */ 303 regulator-min-microvolt = <1800000>; 304 regulator-max-microvolt = <1800000>; 305 regulator-always-on; 306 regulator-boot-on; 307 }; 308 309 buck6: BUCK6 { /* NVCC_DRAM_1V1 */ 310 regulator-min-microvolt = <1100000>; 311 regulator-max-microvolt = <1100000>; 312 regulator-always-on; 313 regulator-boot-on; 314 }; 315 316 ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 317 regulator-min-microvolt = <1800000>; 318 regulator-max-microvolt = <1800000>; 319 regulator-always-on; 320 regulator-boot-on; 321 }; 322 323 ldo3: LDO3 { /* VDDA_1V8 */ 324 regulator-min-microvolt = <1800000>; 325 regulator-max-microvolt = <1800000>; 326 regulator-always-on; 327 regulator-boot-on; 328 }; 329 330 ldo4: LDO4 { /* PMIC_LDO4 */ 331 regulator-min-microvolt = <3300000>; 332 regulator-max-microvolt = <3300000>; 333 }; 334 335 ldo5: LDO5 { /* NVCC_SD2 */ 336 regulator-min-microvolt = <1800000>; 337 regulator-max-microvolt = <3300000>; 338 }; 339 }; 340 }; 341 342 adc@48 { 343 compatible = "ti,tla2024"; 344 reg = <0x48>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 channel@0 { /* Voltage over AIN0 and AIN1. */ 349 reg = <0>; 350 }; 351 352 channel@1 { /* Voltage over AIN0 and AIN3. */ 353 reg = <1>; 354 }; 355 356 channel@2 { /* Voltage over AIN1 and AIN3. */ 357 reg = <2>; 358 }; 359 360 channel@3 { /* Voltage over AIN2 and AIN3. */ 361 reg = <3>; 362 }; 363 364 channel@4 { /* Voltage over AIN0 and GND. */ 365 reg = <4>; 366 }; 367 368 channel@5 { /* Voltage over AIN1 and GND. */ 369 reg = <5>; 370 }; 371 372 channel@6 { /* Voltage over AIN2 and GND. */ 373 reg = <6>; 374 }; 375 376 channel@7 { /* Voltage over AIN3 and GND. */ 377 reg = <7>; 378 }; 379 }; 380 381 touchscreen@49 { 382 compatible = "ti,tsc2004"; 383 reg = <0x49>; 384 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_touch>; 387 vio-supply = <&buck4>; 388 }; 389 390 eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ 391 compatible = "atmel,24c02"; 392 pagesize = <16>; 393 reg = <0x50>; 394 }; 395 396 rv3032: rtc@51 { 397 compatible = "microcrystal,rv3032"; 398 reg = <0x51>; 399 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_rtc>; 402 }; 403 404 eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ 405 compatible = "atmel,24c02"; 406 pagesize = <16>; 407 reg = <0x53>; 408 }; 409}; 410 411&i2c4 { 412 clock-frequency = <100000>; 413 pinctrl-names = "default", "gpio"; 414 pinctrl-0 = <&pinctrl_i2c4>; 415 pinctrl-1 = <&pinctrl_i2c4_gpio>; 416 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 417 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 418 status = "okay"; 419}; 420 421&i2c5 { /* HDMI EDID bus */ 422 clock-frequency = <100000>; 423 pinctrl-names = "default", "gpio"; 424 pinctrl-0 = <&pinctrl_i2c5>; 425 pinctrl-1 = <&pinctrl_i2c5_gpio>; 426 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 427 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 428 status = "okay"; 429}; 430 431&mipi_dsi { 432 samsung,burst-clock-frequency = <160000000>; 433 samsung,esc-clock-frequency = <10000000>; 434 435 ports { 436 port@1 { 437 reg = <1>; 438 439 dsi_out: endpoint { 440 data-lanes = <1 2 3 4>; 441 remote-endpoint = <&tc_bridge_in>; 442 }; 443 }; 444 }; 445}; 446 447&pwm1 { 448 pinctrl-0 = <&pinctrl_pwm1>; 449 pinctrl-names = "default"; 450 status = "disabled"; 451}; 452 453&uart1 { 454 /* CA53 console */ 455 pinctrl-names = "default"; 456 pinctrl-0 = <&pinctrl_uart1>; 457 status = "okay"; 458}; 459 460&uart2 { 461 /* Bluetooth */ 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_uart2>; 464 uart-has-rtscts; 465 status = "okay"; 466 467 /* 468 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock, 469 * which with 16x oversampling yields 5 Mbdps baud base, 470 * which can be well divided by 5/4 to achieve 4 Mbdps, 471 * which is exactly the maximum rate supported by muRata 472 * 2AE bluetooth UART. 473 */ 474 assigned-clocks = <&clk IMX8MP_CLK_UART2>; 475 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 476 assigned-clock-rates = <80000000>; 477 478 bluetooth { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_uart2_bt>; 481 compatible = "cypress,cyw4373a0-bt"; 482 shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 483 max-speed = <4000000>; 484 }; 485}; 486 487&uart3 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_uart3>; 490 uart-has-rtscts; 491 status = "okay"; 492}; 493 494&uart4 { 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pinctrl_uart4>; 497 status = "okay"; 498}; 499 500&usb3_phy0 { 501 status = "okay"; 502}; 503 504&usb3_0 { 505 status = "okay"; 506}; 507 508&usb_dwc3_0 { 509 pinctrl-names = "default"; 510 pinctrl-0 = <&pinctrl_usb0_vbus>; 511 dr_mode = "otg"; 512 status = "okay"; 513}; 514 515&usb3_phy1 { 516 status = "okay"; 517}; 518 519&usb3_1 { 520 status = "okay"; 521}; 522 523&usb_dwc3_1 { 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_usb1_vbus>; 526 dr_mode = "host"; 527 status = "okay"; 528}; 529 530/* SDIO WiFi */ 531&usdhc1 { 532 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 533 pinctrl-0 = <&pinctrl_usdhc1>; 534 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 535 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 536 vmmc-supply = <&buck4>; 537 bus-width = <4>; 538 non-removable; 539 cap-power-off-card; 540 keep-power-in-suspend; 541 status = "okay"; 542 543 #address-cells = <1>; 544 #size-cells = <0>; 545 546 brcmf: bcrmf@1 { /* muRata 2AE */ 547 reg = <1>; 548 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; 549 /* 550 * The "host-wake" interrupt output is by default not 551 * connected to the SoC, but can be connected on to 552 * SoC pin on the carrier board. 553 */ 554 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 555 }; 556}; 557 558/* SD slot */ 559&usdhc2 { 560 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 561 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 562 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 563 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 564 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 565 vmmc-supply = <®_usdhc2_vmmc>; 566 bus-width = <4>; 567 status = "okay"; 568}; 569 570/* eMMC */ 571&usdhc3 { 572 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 573 pinctrl-0 = <&pinctrl_usdhc3>; 574 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 575 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 576 vmmc-supply = <&buck4>; 577 vqmmc-supply = <&buck5>; 578 bus-width = <8>; 579 non-removable; 580 status = "okay"; 581}; 582 583&wdog1 { 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_wdog>; 586 fsl,ext-reset-output; 587 status = "okay"; 588}; 589 590&iomuxc { 591 pinctrl-0 = <&pinctrl_hog_base 592 &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 593 &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 594 &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i 595 &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l 596 /* GPIO_M is connected to CLKOUT1 */ 597 &pinctrl_dhcom_int>; 598 pinctrl-names = "default"; 599 600 pinctrl_dhcom_a: dhcom-a-grp { 601 fsl,pins = < 602 /* ENET_QOS_EVENT0-OUT */ 603 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x2 604 >; 605 }; 606 607 pinctrl_dhcom_b: dhcom-b-grp { 608 fsl,pins = < 609 /* ENET_QOS_EVENT0-IN */ 610 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x2 611 >; 612 }; 613 614 pinctrl_dhcom_c: dhcom-c-grp { 615 fsl,pins = < 616 /* GPIO_C */ 617 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x2 618 >; 619 }; 620 621 pinctrl_dhcom_d: dhcom-d-grp { 622 fsl,pins = < 623 /* GPIO_D */ 624 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x2 625 >; 626 }; 627 628 pinctrl_dhcom_e: dhcom-e-grp { 629 fsl,pins = < 630 /* GPIO_E */ 631 MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x2 632 >; 633 }; 634 635 pinctrl_dhcom_f: dhcom-f-grp { 636 fsl,pins = < 637 /* GPIO_F */ 638 MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x2 639 >; 640 }; 641 642 pinctrl_dhcom_g: dhcom-g-grp { 643 fsl,pins = < 644 /* GPIO_G */ 645 MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 646 >; 647 }; 648 649 pinctrl_dhcom_h: dhcom-h-grp { 650 fsl,pins = < 651 /* GPIO_H */ 652 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x2 653 >; 654 }; 655 656 pinctrl_dhcom_i: dhcom-i-grp { 657 fsl,pins = < 658 /* CSI1_SYNC */ 659 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 660 >; 661 }; 662 663 pinctrl_dhcom_j: dhcom-j-grp { 664 fsl,pins = < 665 /* CSIx_#RST */ 666 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x2 667 >; 668 }; 669 670 pinctrl_dhcom_k: dhcom-k-grp { 671 fsl,pins = < 672 /* CSIx_PWDN */ 673 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x2 674 >; 675 }; 676 677 pinctrl_dhcom_l: dhcom-l-grp { 678 fsl,pins = < 679 /* CSI2_SYNC */ 680 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x2 681 >; 682 }; 683 684 pinctrl_dhcom_int: dhcom-int-grp { 685 fsl,pins = < 686 /* INT_HIGHEST_PRIO */ 687 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x2 688 >; 689 }; 690 691 pinctrl_hog_base: dhcom-hog-base-grp { 692 fsl,pins = < 693 /* GPIOs for memory coding */ 694 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x40000080 695 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40000080 696 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000080 697 /* GPIOs for hardware coding */ 698 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000080 699 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000080 700 MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x40000080 701 >; 702 }; 703 704 pinctrl_ecspi1: dhcom-ecspi1-grp { 705 fsl,pins = < 706 MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x44 707 MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x44 708 MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x44 709 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x40 710 >; 711 }; 712 713 pinctrl_ecspi2: dhcom-ecspi2-grp { 714 fsl,pins = < 715 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 716 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 717 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 718 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 719 >; 720 }; 721 722 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */ 723 fsl,pins = < 724 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 725 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 726 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 727 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 728 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 729 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 730 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 731 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 732 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 733 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 734 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 735 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 736 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 737 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 738 >; 739 }; 740 741 pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */ 742 fsl,pins = < 743 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 744 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 745 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 746 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 747 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 748 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f 749 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 750 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 751 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 752 /* Clock */ 753 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f 754 >; 755 }; 756 757 pinctrl_enet_vio: dhcom-enet-vio-grp { 758 fsl,pins = < 759 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 760 >; 761 }; 762 763 pinctrl_ethphy0: dhcom-ethphy0-grp { 764 fsl,pins = < 765 /* ENET_QOS_#RST Reset */ 766 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 767 /* ENET_QOS_#INT Interrupt */ 768 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 769 >; 770 }; 771 772 pinctrl_ethphy1: dhcom-ethphy1-grp { 773 fsl,pins = < 774 /* ENET1_#RST Reset */ 775 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x11 776 /* ENET1_#INT Interrupt */ 777 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x11 778 >; 779 }; 780 781 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */ 782 fsl,pins = < 783 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f 784 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 785 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 786 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 787 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 788 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 789 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 790 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 791 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 792 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 793 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 794 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 795 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 796 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 797 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 798 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x1f 799 >; 800 }; 801 802 pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */ 803 fsl,pins = < 804 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 805 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 806 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 807 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 808 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 809 MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91 810 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 811 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 812 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 813 /* Clock */ 814 MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f 815 >; 816 }; 817 818 pinctrl_flexcan1: dhcom-flexcan1-grp { 819 fsl,pins = < 820 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 821 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 822 >; 823 }; 824 825 pinctrl_flexcan2: dhcom-flexcan2-grp { 826 fsl,pins = < 827 MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 828 MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 829 >; 830 }; 831 832 pinctrl_flexspi: dhcom-flexspi-grp { 833 fsl,pins = < 834 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 835 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 836 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 837 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 838 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 839 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 840 >; 841 }; 842 843 pinctrl_hdmi: dhcom-hdmi-grp { 844 fsl,pins = < 845 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 846 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 847 >; 848 }; 849 850 pinctrl_i2c3: dhcom-i2c3-grp { 851 fsl,pins = < 852 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 853 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 854 >; 855 }; 856 857 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp { 858 fsl,pins = < 859 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 860 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 861 >; 862 }; 863 864 pinctrl_i2c4: dhcom-i2c4-grp { 865 fsl,pins = < 866 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 867 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 868 >; 869 }; 870 871 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp { 872 fsl,pins = < 873 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 874 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 875 >; 876 }; 877 878 pinctrl_i2c5: dhcom-i2c5-grp { 879 fsl,pins = < 880 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 881 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 882 >; 883 }; 884 885 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp { 886 fsl,pins = < 887 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 888 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 889 >; 890 }; 891 892 pinctrl_pmic: dhcom-pmic-grp { 893 fsl,pins = < 894 /* PMIC_nINT */ 895 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 896 >; 897 }; 898 899 pinctrl_pwm1: dhcom-pwm1-grp { 900 fsl,pins = < 901 MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x6 902 >; 903 }; 904 905 pinctrl_rtc: dhcom-rtc-grp { 906 fsl,pins = < 907 /* RTC_#INT Interrupt */ 908 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 909 >; 910 }; 911 912 pinctrl_tc9595: dhcom-tc9595-grp { 913 fsl,pins = < 914 /* RESET_DSIBRIDGE */ 915 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 916 /* DSI-CONV_INT Interrupt */ 917 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 918 >; 919 }; 920 921 pinctrl_touch: dhcom-touch-grp { 922 fsl,pins = < 923 /* #TOUCH_INT */ 924 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x40000080 925 >; 926 }; 927 928 pinctrl_uart1: dhcom-uart1-grp { 929 fsl,pins = < 930 /* Console UART */ 931 MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x49 932 MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x49 933 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 934 MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x49 935 >; 936 }; 937 938 pinctrl_uart2: dhcom-uart2-grp { 939 fsl,pins = < 940 /* Bluetooth UART */ 941 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 942 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 943 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 944 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 945 >; 946 }; 947 948 pinctrl_uart2_bt: dhcom-uart2-bt-grp { 949 fsl,pins = < 950 /* BT_REG_EN */ 951 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 952 >; 953 }; 954 955 pinctrl_uart3: dhcom-uart3-grp { 956 fsl,pins = < 957 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 958 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x49 959 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x49 960 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x49 961 >; 962 }; 963 964 pinctrl_uart4: dhcom-uart4-grp { 965 fsl,pins = < 966 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 967 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 968 >; 969 }; 970 971 pinctrl_usb0_vbus: dhcom-usb0-grp { 972 fsl,pins = < 973 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 974 >; 975 }; 976 977 pinctrl_usb1_vbus: dhcom-usb1-grp { 978 fsl,pins = < 979 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 980 MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x80 981 >; 982 }; 983 984 pinctrl_usdhc1: dhcom-usdhc1-grp { 985 fsl,pins = < 986 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 987 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 988 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 989 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 990 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 991 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 992 /* WL_REG_EN */ 993 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 994 >; 995 }; 996 997 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp { 998 fsl,pins = < 999 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 1000 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 1001 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 1002 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 1003 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 1004 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 1005 /* WL_REG_EN */ 1006 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 1007 >; 1008 }; 1009 1010 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp { 1011 fsl,pins = < 1012 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 1013 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 1014 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 1015 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 1016 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 1017 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 1018 /* WL_REG_EN */ 1019 MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 1020 >; 1021 }; 1022 1023 pinctrl_usdhc2: dhcom-usdhc2-grp { 1024 fsl,pins = < 1025 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 1026 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 1027 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 1028 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 1029 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 1030 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 1031 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1032 >; 1033 }; 1034 1035 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp { 1036 fsl,pins = < 1037 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 1038 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 1039 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 1040 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 1041 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 1042 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 1043 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1044 >; 1045 }; 1046 1047 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp { 1048 fsl,pins = < 1049 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 1050 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 1051 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 1052 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 1053 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 1054 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 1055 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 1056 >; 1057 }; 1058 1059 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp { 1060 fsl,pins = < 1061 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 1062 >; 1063 }; 1064 1065 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp { 1066 fsl,pins = < 1067 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 1068 >; 1069 }; 1070 1071 pinctrl_usdhc3: dhcom-usdhc3-grp { 1072 fsl,pins = < 1073 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 1074 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 1075 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 1076 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 1077 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 1078 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 1079 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 1080 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 1081 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 1082 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 1083 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 1084 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1085 >; 1086 }; 1087 1088 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp { 1089 fsl,pins = < 1090 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 1091 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 1092 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 1093 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 1094 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 1095 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 1096 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 1097 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 1098 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 1099 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 1100 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 1101 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1102 >; 1103 }; 1104 1105 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp { 1106 fsl,pins = < 1107 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 1108 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 1109 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 1110 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 1111 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 1112 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 1113 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 1114 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 1115 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 1116 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 1117 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 1118 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 1119 >; 1120 }; 1121 1122 pinctrl_wdog: dhcom-wdog-grp { 1123 fsl,pins = < 1124 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 1125 >; 1126 }; 1127}; 1128