xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts (revision 55d0969c451159cff86949b38c39171cab962069) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2024 Marek Vasut <marex@denx.de>
4 *
5 * DHCOM iMX8MP variant:
6 * DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * DRC02 PCB number: 568-100 or newer
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/leds/common.h>
14#include <dt-bindings/phy/phy-imx8-pcie.h>
15#include "imx8mp-dhcom-som.dtsi"
16
17/ {
18	model = "DH electronics i.MX8M Plus DHCOM on DRC02";
19	compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som",
20		     "fsl,imx8mp";
21
22	chosen {
23		stdout-path = &uart1;
24	};
25};
26
27&eqos {	/* First ethernet */
28	pinctrl-0 = <&pinctrl_eqos_rmii>;
29	phy-handle = <&ethphy0f>;
30	phy-mode = "rmii";
31
32	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
33				 <&clk IMX8MP_SYS_PLL2_100M>,
34				 <&clk IMX8MP_SYS_PLL2_50M>;
35	assigned-clock-rates = <0>, <100000000>, <50000000>;
36};
37
38&ethphy0g {	/* Micrel KSZ9131RNXI */
39	status = "disabled";
40};
41
42&ethphy0f {	/* SMSC LAN8740Ai */
43	status = "okay";
44};
45
46&fec {	/* Second ethernet */
47	pinctrl-0 = <&pinctrl_fec_rmii>;
48	phy-handle = <&ethphy1f>;
49	phy-mode = "rmii";
50	status = "okay";
51
52	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
53				 <&clk IMX8MP_SYS_PLL2_100M>,
54				 <&clk IMX8MP_SYS_PLL2_50M>,
55				 <&clk IMX8MP_SYS_PLL2_50M>;
56	assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
57};
58
59&ethphy1f {	/* SMSC LAN8740Ai */
60	status = "okay";
61};
62
63&flexcan1 {
64	status = "okay";
65};
66
67&flexcan2 {
68	status = "okay";
69};
70
71&gpio1 {
72	gpio-line-names =
73		"DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0",
74		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
75		"", "", "", "", "", "", "", "",
76		"", "", "", "", "", "", "", "";
77
78	/*
79	 * NOTE: On DRC02, the RS485_RX_En is controlled by a separate
80	 * GPIO line, however the i.MX8 UART driver assumes RX happens
81	 * during TX anyway and that it only controls drive enable DE
82	 * line. Hence, the RX is always enabled here.
83	 */
84	rs485-rx-en-hog {
85		gpio-hog;
86		gpios = <13 0>; /* GPIO Q */
87		line-name = "rs485-rx-en";
88		output-low;
89	};
90};
91
92&gpio2 {
93	gpio-line-names =
94		"", "", "", "", "", "", "", "",
95		"DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "",
96		"", "", "", "", "DRC02-In2", "", "", "",
97		"", "", "", "", "", "", "", "";
98};
99
100&gpio3 {
101	gpio-line-names =
102		"", "", "", "", "", "", "", "",
103		"", "", "", "", "", "", "SOM-HW0", "",
104		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
105		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
106};
107
108&gpio4 {
109	gpio-line-names =
110		"", "", "", "", "", "", "", "",
111		"", "", "", "", "", "", "", "",
112		"", "", "", "SOM-HW1", "", "", "", "",
113		"", "", "", "DRC02-Out2", "", "", "", "";
114};
115
116&gpio5 {
117	gpio-line-names =
118		"", "", "DHCOM-C", "", "", "", "", "",
119		"", "", "", "", "", "", "", "",
120		"", "", "", "", "", "", "DHCOM-E", "DRC02-Out1",
121		"", "", "", "", "", "", "", "";
122};
123
124/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */
125&hdmi_blk_ctrl {
126	status = "disabled";
127};
128
129&hdmi_pvi {
130	status = "disabled";
131};
132
133&hdmi_tx {
134	status = "disabled";
135};
136
137&hdmi_tx_phy {
138	status = "disabled";
139};
140
141&i2c3 {
142	/* Resistive touch controller not populated on this one SoM variant. */
143	touchscreen@49 {
144		status = "disabled";
145	};
146};
147
148&irqsteer_hdmi {
149	status = "disabled";
150};
151
152&lcdif3 {
153	status = "disabled";
154};
155
156&pcie_phy {
157	status = "disabled";
158};
159
160&pcie {
161	status = "disabled";
162};
163
164/* Console UART */
165&pinctrl_uart1 {
166	fsl,pins = <
167		/* No pull-ups on DRC02, enable in-SoC pull-ups */
168		MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x149
169		MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x149
170	>;
171};
172
173&pinctrl_uart3 {
174	fsl,pins = <
175		/* No pull-ups on DRC02, enable in-SoC pull-ups */
176		MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x149
177		MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x149
178	>;
179};
180
181&uart1 {
182	/*
183	 * Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to
184	 * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs
185	 * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
186	 */
187	/delete-property/ uart-has-rtscts;
188	cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */
189	pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
190	pinctrl-names = "default";
191	rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
192};
193
194&uart3 {
195	/*
196	 * On DRC02 this UART is used as RS485 interface and RS485_TX_En is
197	 * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
198	 * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
199	 * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
200	 * node above.
201	 */
202	/delete-property/ uart-has-rtscts;
203	linux,rs485-enabled-at-boot-time;
204	pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>;
205	pinctrl-names = "default";
206	rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */
207};
208
209/* No WiFi/BT chipset on this SoM variant. */
210&uart2 {
211	bluetooth {
212		status = "disabled";
213	};
214};
215
216/* USB_OTG port is not routed out on DRC02. */
217&usb3_0 {
218	status = "disabled";
219};
220
221&usb_dwc3_0 {
222	status = "disabled";
223};
224
225/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */
226&usb3_1 {
227	fsl,disable-port-power-control;
228	fsl,permanently-attached;
229};
230
231&usb_dwc3_1 {
232	dr_mode = "host";
233	maximum-speed = "high-speed";
234};
235
236/* No WiFi/BT chipset on this SoM variant. */
237&usdhc1 {
238	status = "disabled";
239};
240
241&iomuxc {
242	/*
243	 * GPIO I is connected to UART1_RTS
244	 * GPIO M is connected to UART1_CTS
245	 * GPIO P is connected to RS485_TX_En
246	 * GPIO Q is connected to RS485_RX_En
247	 */
248	pinctrl-0 = <&pinctrl_hog_base
249		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
250		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
251		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j
252		     &pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n
253		     &pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s
254		     &pinctrl_dhcom_int>;
255};
256