1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> 5 */ 6 7#include "imx8mp.dtsi" 8 9#include <dt-bindings/leds/common.h> 10 11/ { 12 model = "Polyhex i.MX8MPlus Debix SOM A"; 13 compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; 14 15 reg_usdhc2_vmmc: regulator-usdhc2 { 16 compatible = "regulator-fixed"; 17 pinctrl-names = "default"; 18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 19 regulator-name = "VSD_3V3"; 20 regulator-min-microvolt = <3300000>; 21 regulator-max-microvolt = <3300000>; 22 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 23 enable-active-high; 24 }; 25 26 gpio-leds { 27 compatible = "gpio-leds"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_gpio_led>; 30 31 led-0 { 32 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 33 default-state = "on"; 34 linux,default-trigger = "heartbeat"; 35 function = LED_FUNCTION_STATUS; 36 color = <LED_COLOR_ID_GREEN>; 37 }; 38 }; 39}; 40 41&A53_0 { 42 cpu-supply = <&buck2>; 43}; 44 45&A53_1 { 46 cpu-supply = <&buck2>; 47}; 48 49&A53_2 { 50 cpu-supply = <&buck2>; 51}; 52 53&A53_3 { 54 cpu-supply = <&buck2>; 55}; 56 57&i2c1 { 58 clock-frequency = <400000>; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_i2c1>; 61 status = "okay"; 62 63 pmic@25 { 64 compatible = "nxp,pca9450c"; 65 reg = <0x25>; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_pmic>; 68 interrupt-parent = <&gpio1>; 69 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 70 71 regulators { 72 buck1: BUCK1 { 73 regulator-name = "BUCK1"; 74 regulator-min-microvolt = <600000>; 75 regulator-max-microvolt = <2187500>; 76 regulator-boot-on; 77 regulator-always-on; 78 regulator-ramp-delay = <3125>; 79 }; 80 81 buck2: BUCK2 { 82 regulator-name = "BUCK2"; 83 regulator-min-microvolt = <600000>; 84 regulator-max-microvolt = <2187500>; 85 regulator-boot-on; 86 regulator-always-on; 87 regulator-ramp-delay = <3125>; 88 nxp,dvs-run-voltage = <950000>; 89 nxp,dvs-standby-voltage = <850000>; 90 }; 91 92 buck4: BUCK4 { 93 regulator-name = "BUCK4"; 94 regulator-min-microvolt = <600000>; 95 regulator-max-microvolt = <3400000>; 96 regulator-boot-on; 97 regulator-always-on; 98 }; 99 100 buck5: BUCK5 { 101 regulator-name = "BUCK5"; 102 regulator-min-microvolt = <600000>; 103 regulator-max-microvolt = <3400000>; 104 regulator-boot-on; 105 regulator-always-on; 106 }; 107 108 buck6: BUCK6 { 109 regulator-name = "BUCK6"; 110 regulator-min-microvolt = <600000>; 111 regulator-max-microvolt = <3400000>; 112 regulator-boot-on; 113 regulator-always-on; 114 }; 115 116 ldo1: LDO1 { 117 regulator-name = "LDO1"; 118 regulator-min-microvolt = <1600000>; 119 regulator-max-microvolt = <3300000>; 120 regulator-boot-on; 121 regulator-always-on; 122 }; 123 124 ldo2: LDO2 { 125 regulator-name = "LDO2"; 126 regulator-min-microvolt = <800000>; 127 regulator-max-microvolt = <1150000>; 128 regulator-boot-on; 129 regulator-always-on; 130 }; 131 132 ldo3: LDO3 { 133 regulator-name = "LDO3"; 134 regulator-min-microvolt = <800000>; 135 regulator-max-microvolt = <3300000>; 136 regulator-boot-on; 137 regulator-always-on; 138 }; 139 140 ldo4: LDO4 { 141 regulator-name = "LDO4"; 142 regulator-min-microvolt = <800000>; 143 regulator-max-microvolt = <3300000>; 144 regulator-boot-on; 145 regulator-always-on; 146 }; 147 148 ldo5: LDO5 { 149 regulator-name = "LDO5"; 150 regulator-min-microvolt = <1800000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 }; 156 }; 157}; 158 159&i2c4 { 160 clock-frequency = <400000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_i2c4>; 163 status = "okay"; 164 165 adc@48 { 166 compatible = "ti,ads1115"; 167 reg = <0x48>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 channel@4 { 172 reg = <4>; 173 ti,gain = <1>; 174 ti,datarate = <7>; 175 }; 176 177 channel@5 { 178 reg = <5>; 179 ti,gain = <1>; 180 ti,datarate = <7>; 181 }; 182 183 channel@6 { 184 reg = <6>; 185 ti,gain = <1>; 186 ti,datarate = <7>; 187 }; 188 189 channel@7 { 190 reg = <7>; 191 ti,gain = <1>; 192 ti,datarate = <7>; 193 }; 194 }; 195}; 196 197&snvs_pwrkey { 198 status = "okay"; 199}; 200 201/* eMMC */ 202&usdhc3 { 203 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 204 pinctrl-0 = <&pinctrl_usdhc3>; 205 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 206 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 207 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 208 assigned-clock-rates = <400000000>; 209 bus-width = <8>; 210 non-removable; 211 status = "okay"; 212}; 213 214&wdog1 { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_wdog>; 217 fsl,ext-reset-output; 218 status = "okay"; 219}; 220 221&iomuxc { 222 pinctrl_gpio_led: gpioledgrp { 223 fsl,pins = < 224 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 225 >; 226 }; 227 228 pinctrl_i2c1: i2c1grp { 229 fsl,pins = < 230 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 231 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 232 >; 233 }; 234 235 pinctrl_i2c4: i2c4grp { 236 fsl,pins = < 237 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 238 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 239 >; 240 }; 241 242 pinctrl_pmic: pmicgrp { 243 fsl,pins = < 244 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 245 >; 246 }; 247 248 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 249 fsl,pins = < 250 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 251 >; 252 }; 253 254 pinctrl_usdhc3: usdhc3grp { 255 fsl,pins = < 256 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 257 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 258 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 259 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 260 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 261 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 262 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 263 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 264 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 265 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 266 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 267 >; 268 }; 269 270 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 271 fsl,pins = < 272 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 273 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 274 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 275 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 276 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 277 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 278 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 279 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 280 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 281 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 282 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 283 >; 284 }; 285 286 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 287 fsl,pins = < 288 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 289 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 290 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 291 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 292 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 293 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 294 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 295 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 296 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 297 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 298 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 299 >; 300 }; 301 302 pinctrl_wdog: wdoggrp { 303 fsl,pins = < 304 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 305 >; 306 }; 307}; 308