1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> 5 */ 6 7/dts-v1/; 8 9#include "imx8mp-debix-som-a.dtsi" 10 11/ { 12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; 13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", 14 "fsl,imx8mp"; 15 16 aliases { 17 ethernet0 = &eqos; 18 ethernet1 = &fec; 19 }; 20 21 chosen { 22 stdout-path = &uart2; 23 }; 24 25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { 26 compatible = "regulator-fixed"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 regulator-name = "BB_VDD3V3"; 30 /* Required timings for ethernet phy's */ 31 startup-delay-us = <50000>; 32 off-on-delay-us = <110000>; 33 gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; 34 enable-active-high; 35 }; 36 37 reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { 38 compatible = "regulator-fixed"; 39 regulator-min-microvolt = <5000000>; 40 regulator-max-microvolt = <5000000>; 41 regulator-name = "BB_VDD5V"; 42 gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; 43 enable-active-high; 44 }; 45 46 regulator-som-vdd1v8 { 47 compatible = "regulator-fixed"; 48 regulator-min-microvolt = <1800000>; 49 regulator-max-microvolt = <1800000>; 50 regulator-name = "SOM_VDD1V8_SW"; 51 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 regulator-always-on; 54 }; 55 56 regulator-som-vdd3v3 { 57 compatible = "regulator-fixed"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-name = "SOM_VDD3V3_SW"; 61 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; 62 enable-active-high; 63 regulator-always-on; 64 }; 65 66 reg_csi1_1v8: regulator-csi1-vdd1v8 { 67 compatible = "regulator-fixed"; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <1800000>; 70 regulator-name = "CSI1_VDD1V8"; 71 gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; 72 enable-active-high; 73 vin-supply = <®_baseboard_vdd3v3>; 74 }; 75 76 reg_csi1_3v3: regulator-csi1-vdd3v3 { 77 compatible = "regulator-fixed"; 78 regulator-min-microvolt = <3300000>; 79 regulator-max-microvolt = <3300000>; 80 regulator-name = "CSI1_VDD3V3"; 81 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; 82 enable-active-high; 83 vin-supply = <®_vdd5v0>; 84 }; 85 86 reg_csi2_1v8: regulator-csi2-vdd1v8 { 87 compatible = "regulator-fixed"; 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_reg_csi2_1v8>; 90 regulator-min-microvolt = <1800000>; 91 regulator-max-microvolt = <1800000>; 92 regulator-name = "CSI2_VDD1V8"; 93 gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; 94 enable-active-high; 95 vin-supply = <®_baseboard_vdd3v3>; 96 }; 97 98 reg_csi2_3v3: regulator-csi2-vdd3v3 { 99 compatible = "regulator-fixed"; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_reg_csi2_3v3>; 102 regulator-min-microvolt = <3300000>; 103 regulator-max-microvolt = <3300000>; 104 regulator-name = "CSI2_VDD3V3"; 105 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 vin-supply = <®_vdd5v0>; 108 }; 109 110 regulator-vbus-usb20 { 111 compatible = "regulator-fixed"; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 regulator-name = "USB20_5V"; 115 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 regulator-always-on; 118 vin-supply = <®_baseboard_vdd5v0>; 119 }; 120 121 regulator-vbus-usb30 { 122 compatible = "regulator-fixed"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 regulator-name = "USB30_5V"; 126 gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; 127 enable-active-high; 128 regulator-always-on; 129 vin-supply = <®_baseboard_vdd5v0>; 130 }; 131 132 reg_vdd5v0: regulator-vdd5v0 { 133 compatible = "regulator-fixed"; 134 regulator-min-microvolt = <5000000>; 135 regulator-max-microvolt = <5000000>; 136 regulator-name = "VDD_5V"; 137 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; 138 enable-active-high; 139 }; 140}; 141 142&eqos { 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_eqos>; 145 nvmem-cells = <ðmac1>; 146 nvmem-cell-names = "mac-address"; 147 phy-handle = <ðphy0>; 148 phy-mode = "rgmii-id"; 149 status = "okay"; 150 151 mdio { 152 compatible = "snps,dwmac-mdio"; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 ethphy0: ethernet-phy@1 { 157 compatible = "ethernet-phy-ieee802.3-c22"; 158 reg = <1>; 159 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 160 reset-assert-us = <20000>; 161 reset-deassert-us = <150000>; 162 eee-broken-1000t; 163 realtek,clkout-disable; 164 }; 165 }; 166}; 167 168&fec { 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_fec>; 171 nvmem-cells = <ðmac2>; 172 nvmem-cell-names = "mac-address"; 173 phy-supply = <®_baseboard_vdd3v3>; 174 phy-handle = <ðphy1>; 175 phy-mode = "rgmii-id"; 176 fsl,magic-packet; 177 status = "okay"; 178 179 mdio { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 183 ethphy1: ethernet-phy@1 { 184 compatible = "ethernet-phy-ieee802.3-c22"; 185 reg = <1>; 186 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; 187 reset-assert-us = <20000>; 188 reset-deassert-us = <150000>; 189 eee-broken-1000t; 190 realtek,clkout-disable; 191 }; 192 }; 193}; 194 195&flexcan1 { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_flexcan1>; 198 xceiver-supply = <®_vdd5v0>; 199 status = "okay"; 200}; 201 202&flexcan2 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_flexcan2>; 205 xceiver-supply = <®_vdd5v0>; 206 status = "okay"; 207}; 208 209&flexspi { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_flexspi0>; 212 status = "okay"; 213 214 flash: flash@0 { 215 compatible = "jedec,spi-nor"; 216 reg = <0>; 217 spi-max-frequency = <80000000>; 218 spi-tx-bus-width = <1>; 219 spi-rx-bus-width = <4>; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 }; 223}; 224 225&i2c4 { 226 expander0: gpio@20 { 227 compatible = "nxp,pca9535"; 228 reg = <0x20>; 229 gpio-controller; 230 #gpio-cells = <0x02>; 231 }; 232 233 expander1: gpio@23 { 234 compatible = "nxp,pca9535"; 235 reg = <0x23>; 236 gpio-controller; 237 #gpio-cells = <0x02>; 238 239 /* 240 * Since USB1 is bound to peripheral mode we need to ensure 241 * that VBUS is turned off. 242 */ 243 usb30-otg-hog { 244 gpio-hog; 245 gpios = <13 GPIO_ACTIVE_HIGH>; 246 output-low; 247 line-name = "USB30_OTG_EN"; 248 }; 249 }; 250 251 rtc@51 { 252 compatible = "haoyu,hym8563"; 253 reg = <0x51>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_rtc>; 256 interrupt-parent = <&gpio4>; 257 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 258 #clock-cells = <0>; 259 }; 260 261 eeprom@52 { 262 compatible = "atmel,24c02"; 263 reg = <0x52>; 264 pagesize = <16>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 268 /* MACs stored in ASCII */ 269 ethmac1: mac-address@0 { 270 reg = <0x0 0xc>; 271 }; 272 273 ethmac2: mac-address@c { 274 reg = <0xc 0xc>; 275 }; 276 }; 277}; 278 279&snvs_pwrkey { 280 status = "okay"; 281}; 282 283/* Debug */ 284&uart2 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_uart2>; 287 status = "okay"; 288}; 289 290&uart3 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_uart3>; 293 status = "okay"; 294}; 295 296&uart4 { 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_uart4>; 299 status = "okay"; 300}; 301 302&usb3_0 { 303 status = "okay"; 304}; 305 306&usb3_1 { 307 status = "okay"; 308}; 309 310&usb_dwc3_0 { 311 dr_mode = "peripheral"; 312 status = "okay"; 313}; 314 315&usb_dwc3_1 { 316 dr_mode = "host"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 status = "okay"; 320 321 /* 2.x hub on port 1 */ 322 usb_hub_2_x: hub@1 { 323 compatible = "usb5e3,610"; 324 reg = <1>; 325 reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; 326 vdd-supply = <®_vdd5v0>; 327 peer-hub = <&usb_hub_3_x>; 328 }; 329 330 /* 3.x hub on port 2 */ 331 usb_hub_3_x: hub@2 { 332 compatible = "usb5e3,620"; 333 reg = <2>; 334 reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; 335 vdd-supply = <®_vdd5v0>; 336 peer-hub = <&usb_hub_2_x>; 337 }; 338}; 339 340&usb3_phy0 { 341 status = "okay"; 342}; 343 344&usb3_phy1 { 345 status = "okay"; 346}; 347 348/* µSD Card */ 349&usdhc2 { 350 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 351 pinctrl-0 = <&pinctrl_usdhc2>; 352 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 353 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 354 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 355 assigned-clock-rates = <400000000>; 356 vmmc-supply = <®_usdhc2_vmmc>; 357 bus-width = <4>; 358 disable-wp; 359 no-sdio; 360 no-mmc; 361 status = "okay"; 362}; 363 364&iomuxc { 365 pinctrl_eqos: eqosgrp { 366 fsl,pins = < 367 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 368 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 369 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 370 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 371 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 372 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 373 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 374 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 375 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 376 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 377 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 378 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 379 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 380 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 381 382 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f 383 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 384 >; 385 }; 386 387 pinctrl_fec: fecgrp { 388 fsl,pins = < 389 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 390 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 391 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 392 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 393 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 394 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 395 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 396 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 397 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 398 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 399 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 400 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 401 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 402 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 403 MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f 404 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 405 >; 406 }; 407 408 pinctrl_flexcan1: flexcan1grp { 409 fsl,pins = < 410 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 411 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 412 >; 413 }; 414 415 pinctrl_flexcan2: flexcan2grp { 416 fsl,pins = < 417 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 418 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 419 >; 420 }; 421 422 pinctrl_flexspi0: flexspi0grp { 423 fsl,pins = < 424 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 425 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 426 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 427 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 428 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 429 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 430 >; 431 }; 432 433 pinctrl_i2c1: i2c1grp { 434 fsl,pins = < 435 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 436 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 437 >; 438 }; 439 440 pinctrl_i2c4: i2c4grp { 441 fsl,pins = < 442 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 443 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 444 >; 445 }; 446 447 pinctrl_rtc: rtcgrp { 448 fsl,pins = < 449 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 450 >; 451 }; 452 453 pinctrl_pmic: pmicgrp { 454 fsl,pins = < 455 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 456 >; 457 }; 458 459 pinctrl_reg_csi2_1v8: regcsi21v8grp { 460 fsl,pins = < 461 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19 462 >; 463 }; 464 465 pinctrl_reg_csi2_3v3: regcsi23v3grp { 466 fsl,pins = < 467 MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 468 >; 469 }; 470 471 pinctrl_uart2: uart2grp { 472 fsl,pins = < 473 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f 474 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f 475 >; 476 }; 477 478 pinctrl_uart3: uart3grp { 479 fsl,pins = < 480 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 481 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 482 >; 483 }; 484 485 pinctrl_uart4: uart4grp { 486 fsl,pins = < 487 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 488 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 489 >; 490 }; 491 492 pinctrl_usdhc2: usdhc2grp { 493 fsl,pins = < 494 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 495 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 496 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 497 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 498 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 499 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 500 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 501 >; 502 }; 503 504 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 505 fsl,pins = < 506 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 507 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 508 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 509 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 510 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 511 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 512 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 513 >; 514 }; 515 516 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 517 fsl,pins = < 518 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 519 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 520 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 521 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 522 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 523 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 524 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 525 >; 526 }; 527}; 528