1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright 2022 Ideas on Board Oy 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/usb/pd.h> 12 13#include "imx8mp.dtsi" 14 15/ { 16 model = "Polyhex Debix Model A i.MX8MPlus board"; 17 compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp"; 18 19 chosen { 20 stdout-path = &uart2; 21 }; 22 23 hdmi-connector { 24 compatible = "hdmi-connector"; 25 label = "hdmi"; 26 type = "a"; 27 28 port { 29 hdmi_connector_in: endpoint { 30 remote-endpoint = <&hdmi_tx_out>; 31 }; 32 }; 33 }; 34 35 leds { 36 compatible = "gpio-leds"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_gpio_led>; 39 40 led-0 { 41 function = LED_FUNCTION_POWER; 42 color = <LED_COLOR_ID_RED>; 43 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 44 default-state = "on"; 45 }; 46 }; 47 48 reg_usdhc2_vmmc: regulator-usdhc2 { 49 compatible = "regulator-fixed"; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 52 regulator-name = "VSD_3V3"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 56 enable-active-high; 57 }; 58 59 reg_usb_hub: regulator-usb-hub { 60 compatible = "regulator-fixed"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_reg_usb_hub>; 63 regulator-name = "USB_HUB"; 64 regulator-min-microvolt = <5000000>; 65 regulator-max-microvolt = <5000000>; 66 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 }; 69}; 70 71&A53_0 { 72 cpu-supply = <&buck2>; 73}; 74 75&A53_1 { 76 cpu-supply = <&buck2>; 77}; 78 79&A53_2 { 80 cpu-supply = <&buck2>; 81}; 82 83&A53_3 { 84 cpu-supply = <&buck2>; 85}; 86 87&eqos { 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_eqos>; 90 phy-mode = "rgmii-id"; 91 phy-handle = <ðphy0>; 92 status = "okay"; 93 94 mdio { 95 compatible = "snps,dwmac-mdio"; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 ethphy0: ethernet-phy@0 { /* RTL8211E */ 100 compatible = "ethernet-phy-ieee802.3-c22"; 101 reg = <0>; 102 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; 103 reset-assert-us = <20>; 104 reset-deassert-us = <200000>; 105 }; 106 }; 107}; 108 109&hdmi_pvi { 110 status = "okay"; 111}; 112 113&hdmi_tx { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_hdmi>; 116 status = "okay"; 117 118 ports { 119 port@1 { 120 hdmi_tx_out: endpoint { 121 remote-endpoint = <&hdmi_connector_in>; 122 }; 123 }; 124 }; 125}; 126 127&hdmi_tx_phy { 128 status = "okay"; 129}; 130 131&i2c1 { 132 clock-frequency = <400000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_i2c1>; 135 status = "okay"; 136 137 pmic@25 { 138 compatible = "nxp,pca9450c"; 139 reg = <0x25>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_pmic>; 142 interrupt-parent = <&gpio1>; 143 interrupts = <3 IRQ_TYPE_EDGE_RISING>; 144 145 regulators { 146 buck1: BUCK1 { 147 regulator-name = "BUCK1"; 148 regulator-min-microvolt = <600000>; 149 regulator-max-microvolt = <2187500>; 150 regulator-boot-on; 151 regulator-always-on; 152 regulator-ramp-delay = <3125>; 153 }; 154 155 buck2: BUCK2 { 156 regulator-name = "BUCK2"; 157 regulator-min-microvolt = <600000>; 158 regulator-max-microvolt = <2187500>; 159 regulator-boot-on; 160 regulator-always-on; 161 regulator-ramp-delay = <3125>; 162 nxp,dvs-run-voltage = <950000>; 163 nxp,dvs-standby-voltage = <850000>; 164 }; 165 166 buck4: BUCK4 { 167 regulator-name = "BUCK4"; 168 regulator-min-microvolt = <600000>; 169 regulator-max-microvolt = <3400000>; 170 regulator-boot-on; 171 regulator-always-on; 172 }; 173 174 buck5: BUCK5 { 175 regulator-name = "BUCK5"; 176 regulator-min-microvolt = <600000>; 177 regulator-max-microvolt = <3400000>; 178 regulator-boot-on; 179 regulator-always-on; 180 }; 181 182 buck6: BUCK6 { 183 regulator-name = "BUCK6"; 184 regulator-min-microvolt = <600000>; 185 regulator-max-microvolt = <3400000>; 186 regulator-boot-on; 187 regulator-always-on; 188 }; 189 190 ldo1: LDO1 { 191 regulator-name = "LDO1"; 192 regulator-min-microvolt = <1600000>; 193 regulator-max-microvolt = <3300000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 ldo2: LDO2 { 199 regulator-name = "LDO2"; 200 regulator-min-microvolt = <800000>; 201 regulator-max-microvolt = <1150000>; 202 regulator-boot-on; 203 regulator-always-on; 204 }; 205 206 ldo3: LDO3 { 207 regulator-name = "LDO3"; 208 regulator-min-microvolt = <800000>; 209 regulator-max-microvolt = <3300000>; 210 regulator-boot-on; 211 regulator-always-on; 212 }; 213 214 ldo4: LDO4 { 215 regulator-name = "LDO4"; 216 regulator-min-microvolt = <800000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-boot-on; 219 regulator-always-on; 220 }; 221 222 ldo5: LDO5 { 223 regulator-name = "LDO5"; 224 regulator-min-microvolt = <1800000>; 225 regulator-max-microvolt = <3300000>; 226 regulator-boot-on; 227 regulator-always-on; 228 }; 229 }; 230 }; 231}; 232 233&i2c2 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_i2c2>; 236}; 237 238&i2c3 { 239 clock-frequency = <400000>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_i2c3>; 242 status = "okay"; 243}; 244 245&i2c4 { 246 clock-frequency = <100000>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_i2c4>; 249 status = "okay"; 250 251 eeprom@50 { 252 compatible = "atmel,24c02"; 253 reg = <0x50>; 254 pagesize = <16>; 255 }; 256 257 rtc@51 { 258 compatible = "haoyu,hym8563"; 259 reg = <0x51>; 260 #clock-cells = <0>; 261 clock-output-names = "xin32k"; 262 interrupt-parent = <&gpio2>; 263 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_rtc_int>; 266 }; 267}; 268 269&i2c6 { 270 clock-frequency = <400000>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_i2c6>; 273 status = "okay"; 274}; 275 276&lcdif3 { 277 status = "okay"; 278}; 279 280&snvs_pwrkey { 281 status = "okay"; 282}; 283 284&uart2 { 285 /* console */ 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_uart2>; 288 status = "okay"; 289}; 290 291&uart3 { 292 pinctrl-names = "default"; 293 pinctrl-0 = <&pinctrl_uart3>; 294 status = "okay"; 295}; 296 297&uart4 { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_uart4>; 300 status = "okay"; 301}; 302 303&usb3_phy1 { 304 status = "okay"; 305}; 306 307&usb3_1 { 308 status = "okay"; 309}; 310 311&usb_dwc3_1 { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_usb1>; 316 dr_mode = "host"; 317 status = "okay"; 318 319 /* 2.x hub on port 1 */ 320 usb_hub_2_x: hub@1 { 321 compatible = "usbbda,5411"; 322 reg = <1>; 323 vdd-supply = <®_usb_hub>; 324 peer-hub = <&usb_hub_3_x>; 325 }; 326 327 /* 3.x hub on port 2 */ 328 usb_hub_3_x: hub@2 { 329 compatible = "usbbda,411"; 330 reg = <2>; 331 vdd-supply = <®_usb_hub>; 332 peer-hub = <&usb_hub_2_x>; 333 }; 334}; 335 336/* SD Card */ 337&usdhc2 { 338 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 339 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 340 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 341 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 342 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 343 vmmc-supply = <®_usdhc2_vmmc>; 344 bus-width = <4>; 345 status = "okay"; 346}; 347 348/* eMMC */ 349&usdhc3 { 350 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 351 assigned-clock-rates = <400000000>; 352 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 353 pinctrl-0 = <&pinctrl_usdhc3>; 354 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 355 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 356 bus-width = <8>; 357 non-removable; 358 status = "okay"; 359}; 360 361&wdog1 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_wdog>; 364 fsl,ext-reset-output; 365 status = "okay"; 366}; 367 368&iomuxc { 369 pinctrl_eqos: eqosgrp { 370 fsl,pins = < 371 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 372 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 373 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 374 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 375 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 376 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 377 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 378 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 379 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 380 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 381 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 382 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 383 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 384 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 385 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f 386 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f 387 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 388 >; 389 }; 390 391 pinctrl_gpio_led: gpioledgrp { 392 fsl,pins = < 393 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 394 >; 395 }; 396 397 pinctrl_hdmi: hdmigrp { 398 fsl,pins = < 399 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 400 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 401 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 402 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19 403 >; 404 }; 405 406 pinctrl_i2c1: i2c1grp { 407 fsl,pins = < 408 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 409 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 410 >; 411 }; 412 413 pinctrl_i2c2: i2c2grp { 414 fsl,pins = < 415 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 416 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 417 >; 418 }; 419 420 pinctrl_i2c3: i2c3grp { 421 fsl,pins = < 422 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 423 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 424 >; 425 }; 426 427 pinctrl_i2c4: i2c4grp { 428 fsl,pins = < 429 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 430 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 431 >; 432 }; 433 434 pinctrl_i2c6: i2c6grp { 435 fsl,pins = < 436 MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 437 MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 438 >; 439 }; 440 441 pinctrl_pmic: pmicirqgrp { 442 fsl,pins = < 443 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 444 >; 445 }; 446 447 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 448 fsl,pins = < 449 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 450 >; 451 }; 452 453 pinctrl_reg_usb_hub: regusbhubgrp { 454 fsl,pins = < 455 MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x19 456 >; 457 }; 458 459 pinctrl_rtc_int: rtcintgrp { 460 fsl,pins = < 461 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 462 >; 463 }; 464 465 pinctrl_uart2: uart2grp { 466 fsl,pins = < 467 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f 468 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f 469 >; 470 }; 471 472 pinctrl_uart3: uart3grp { 473 fsl,pins = < 474 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 475 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 476 >; 477 }; 478 479 pinctrl_uart4: uart4grp { 480 fsl,pins = < 481 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 482 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 483 >; 484 }; 485 486 pinctrl_usb1: usb1grp { 487 fsl,pins = < 488 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 489 >; 490 }; 491 492 pinctrl_usdhc2: usdhc2grp { 493 fsl,pins = < 494 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 495 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 496 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 497 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 498 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 499 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 500 >; 501 }; 502 503 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 504 fsl,pins = < 505 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 506 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 507 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 508 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 509 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 510 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 511 >; 512 }; 513 514 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 515 fsl,pins = < 516 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 517 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 518 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 519 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 520 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 521 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 522 >; 523 }; 524 525 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 526 fsl,pins = < 527 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 528 >; 529 }; 530 531 pinctrl_usdhc3: usdhc3grp { 532 fsl,pins = < 533 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 534 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 535 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 536 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 537 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 538 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 539 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 540 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 541 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 542 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 543 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 544 >; 545 }; 546 547 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 548 fsl,pins = < 549 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 550 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 551 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 552 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 553 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 554 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 555 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 556 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 557 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 558 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 559 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 560 >; 561 }; 562 563 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 564 fsl,pins = < 565 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 566 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 567 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 568 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 569 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 570 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 571 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 572 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 573 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 574 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 575 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 576 >; 577 }; 578 579 pinctrl_wdog: wdoggrp { 580 fsl,pins = < 581 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 582 >; 583 }; 584}; 585