xref: /linux/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts (revision bb9ae1a66c85eeb626864efd812c62026e126ec0)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/net/qca-ar803x.h>
9#include <dt-bindings/phy/phy-imx8-pcie.h>
10#include "imx8mp.dtsi"
11
12/ {
13	model = "Data Modul i.MX8M Plus eDM SBC";
14	compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
15
16	aliases {
17		rtc0 = &rtc;
18		rtc1 = &snvs_rtc;
19	};
20
21	chosen {
22		stdout-path = &uart3;
23	};
24
25	memory@40000000 {
26		device_type = "memory";
27		/* There are 1/2/4 GiB options, adjusted by bootloader. */
28		reg = <0x0 0x40000000 0 0x40000000>;
29	};
30
31	backlight: backlight {
32		compatible = "pwm-backlight";
33		pinctrl-names = "default";
34		pinctrl-0 = <&pinctrl_panel_backlight>;
35		brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
36		default-brightness-level = <7>;
37		enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
38		pwms = <&pwm1 0 5000000 0>;
39		/* Disabled by default, unless display board plugged in. */
40		status = "disabled";
41	};
42
43	clk_xtal25: clock-xtal25 {
44		compatible = "fixed-clock";
45		#clock-cells = <0>;
46		clock-frequency = <25000000>;
47	};
48
49	clk_pwm4: clock-pwm4 {
50		compatible = "pwm-clock";
51		#clock-cells = <0>;
52		clock-frequency = <12000000>;
53		clock-output-names = "codec-pwm4";
54		/*
55		 * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz
56		 * and the calculated PWM period is 1 and duty cycle is 50%, the
57		 * result is exactly 12 MHz, which is fine for SGTL5000 MCLK.
58		 */
59		pwms = <&pwm4 0 83 0>;
60	};
61
62	hdmi-connector {
63		compatible = "hdmi-connector";
64		label = "J17";
65		type = "a";
66
67		port {
68			hdmi_connector_in: endpoint {
69				remote-endpoint = <&hdmi_tx_out>;
70			};
71		};
72	};
73
74	panel: panel {
75		/* Compatible string is filled in by panel board DT Overlay. */
76		backlight = <&backlight>;
77		power-supply = <&reg_panel_vcc>;
78		/* Disabled by default, unless display board plugged in. */
79		status = "disabled";
80	};
81
82	reg_panel_vcc: regulator-panel-vcc {
83		compatible = "regulator-fixed";
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_panel_vcc_reg>;
86		regulator-min-microvolt = <5000000>;
87		regulator-max-microvolt = <5000000>;
88		regulator-name = "PANEL_VCC";
89		/* GPIO flags are ignored, enable-active-high applies. */
90		gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>;
91		enable-active-high;
92		/* Disabled by default, unless display board plugged in. */
93		status = "disabled";
94	};
95
96	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
97		compatible = "regulator-fixed";
98		pinctrl-names = "default";
99		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
100		regulator-max-microvolt = <3300000>;
101		regulator-min-microvolt = <3300000>;
102		regulator-name = "VDD_3V3_SD";
103		/* GPIO flags are ignored, enable-active-high applies. */
104		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */
105		enable-active-high;
106		off-on-delay-us = <12000>;
107		startup-delay-us = <100>;
108		vin-supply = <&buck4>;
109	};
110
111	sound {
112		compatible = "simple-audio-card";
113		simple-audio-card,name = "SGTL5000-Card";
114		simple-audio-card,format = "i2s";
115		simple-audio-card,bitclock-master = <&codec_dai>;
116		simple-audio-card,frame-master = <&codec_dai>;
117		simple-audio-card,widgets = "Headphone", "Headphone Jack";
118		simple-audio-card,routing = "Headphone Jack", "HP_OUT";
119
120		cpu_dai: simple-audio-card,cpu {
121			sound-dai = <&sai3>;
122		};
123
124		codec_dai: simple-audio-card,codec {
125			sound-dai = <&sgtl5000>;
126		};
127	};
128
129	watchdog { /* TPS3813 */
130		compatible = "linux,wdt-gpio";
131		pinctrl-names = "default";
132		pinctrl-0 = <&pinctrl_watchdog_gpio>;
133		always-running;
134		gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
135		hw_algo = "level";
136		/* Reset triggers in 2..3 seconds */
137		hw_margin_ms = <1500>;
138		/* Disabled by default */
139		status = "disabled";
140	};
141};
142
143&A53_0 {
144	cpu-supply = <&buck2>;
145};
146
147&A53_1 {
148	cpu-supply = <&buck2>;
149};
150
151&A53_2 {
152	cpu-supply = <&buck2>;
153};
154
155&A53_3 {
156	cpu-supply = <&buck2>;
157};
158
159&ecspi1 {
160	pinctrl-names = "default";
161	pinctrl-0 = <&pinctrl_ecspi1>;
162	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
163	status = "okay";
164
165	flash@0 {	/* W25Q128JVEI */
166		compatible = "jedec,spi-nor";
167		reg = <0>;
168		spi-max-frequency = <40000000>;
169		spi-tx-bus-width = <1>;
170		spi-rx-bus-width = <1>;
171	};
172};
173
174&ecspi2 {	/* Feature connector SPI */
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_ecspi2>;
177	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
178	/* Disabled by default, unless feature board plugged in. */
179	status = "disabled";
180};
181
182&ecspi3 {	/* Display connector SPI */
183	pinctrl-names = "default";
184	pinctrl-0 = <&pinctrl_ecspi3>;
185	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
186	/* Disabled by default, unless display board plugged in. */
187	status = "disabled";
188};
189
190&eqos {	/* First ethernet */
191	pinctrl-names = "default";
192	pinctrl-0 = <&pinctrl_eqos>;
193	phy-handle = <&phy_eqos>;
194	phy-mode = "rgmii-id";
195	status = "okay";
196
197	mdio {
198		compatible = "snps,dwmac-mdio";
199		#address-cells = <1>;
200		#size-cells = <0>;
201
202		/* Atheros AR8031 PHY */
203		phy_eqos: ethernet-phy@0 {
204			compatible = "ethernet-phy-ieee802.3-c22";
205			reg = <0>;
206			/*
207			 * Dedicated ENET_WOL# signal is unused, the PHY
208			 * can wake the SoC up via INT signal as well.
209			 */
210			interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
211			reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
212			reset-assert-us = <10000>;
213			reset-deassert-us = <10000>;
214			qca,keep-pll-enabled;
215			vddio-supply = <&vddio_eqos>;
216
217			vddio_eqos: vddio-regulator {
218				regulator-name = "VDDIO_EQOS";
219				regulator-min-microvolt = <1800000>;
220				regulator-max-microvolt = <1800000>;
221			};
222
223			vddh_eqos: vddh-regulator {
224				regulator-name = "VDDH_EQOS";
225			};
226		};
227	};
228};
229
230&fec {	/* Second ethernet */
231	pinctrl-names = "default";
232	pinctrl-0 = <&pinctrl_fec>;
233	phy-handle = <&phy_fec>;
234	phy-mode = "rgmii-id";
235	fsl,magic-packet;
236	status = "okay";
237
238	mdio {
239		#address-cells = <1>;
240		#size-cells = <0>;
241
242		/* Atheros AR8031 PHY */
243		phy_fec: ethernet-phy@0 {
244			compatible = "ethernet-phy-ieee802.3-c22";
245			reg = <0>;
246			/*
247			 * Dedicated ENET_WOL# signal is unused, the PHY
248			 * can wake the SoC up via INT signal as well.
249			 */
250			interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>;
251			reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
252			reset-assert-us = <10000>;
253			reset-deassert-us = <10000>;
254			qca,keep-pll-enabled;
255			vddio-supply = <&vddio_fec>;
256
257			vddio_fec: vddio-regulator {
258				regulator-name = "VDDIO_FEC";
259				regulator-min-microvolt = <1800000>;
260				regulator-max-microvolt = <1800000>;
261			};
262
263			vddh_fec: vddh-regulator {
264				regulator-name = "VDDH_FEC";
265			};
266		};
267	};
268};
269
270&flexcan1 {
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_flexcan1>;
273	status = "okay";
274};
275
276&gpio1 {
277	gpio-line-names =
278		"", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#",
279		"", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03",
280		"GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#",
281		"", "", "", "ENET_RST#",
282		"", "", "", "", "", "", "", "",
283		"", "", "", "", "", "", "", "";
284};
285
286&gpio2 {
287	gpio-line-names =
288		"", "", "ENET2_INT#", "", "", "", "", "",
289		"WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#",
290		"", "", "", "",
291		"", "", "", "SD2_RESET#", "", "", "", "",
292		"", "", "", "", "", "", "", "";
293};
294
295&gpio3 {
296	gpio-line-names =
297		"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
298		"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
299		"CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "",
300		"", "", "EEPROM_WP_1V8#", "", "", "", "", "",
301		"MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#",
302		"", "M2_W_DISABLE1_1V8#",
303		"M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3",
304		"", "", "", "";
305};
306
307&gpio4 {
308	gpio-line-names =
309		"DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "",
310		"", "", "", "", "", "", "", "",
311		"", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#",
312		"", "DIS_USB_DN1", "DIS_USB_DN2", "",
313		"", "", "", "", "", "", "", "";
314};
315
316&gpio5 {
317	gpio-line-names =
318		"", "", "", "", "", "WDOG_EN", "", "",
319		"", "SPI1_CS#", "", "",
320		"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
321		"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
322		"", "", "", "",
323		"", "SPI3_CS#", "", "", "", "", "", "";
324};
325
326&hdmi_pvi {
327	status = "okay";
328};
329
330&hdmi_tx {
331	ddc-i2c-bus = <&i2c5>;
332	pinctrl-names = "default";
333	pinctrl-0 = <&pinctrl_hdmi>;
334	status = "okay";
335
336	ports {
337		port@1 {
338			hdmi_tx_out: endpoint {
339				remote-endpoint = <&hdmi_connector_in>;
340			};
341		};
342	};
343};
344
345&hdmi_tx_phy {
346	status = "okay";
347};
348
349&lcdif3 {
350	status = "okay";
351};
352
353&i2c1 {
354	clock-frequency = <100000>;
355	pinctrl-names = "default", "gpio";
356	pinctrl-0 = <&pinctrl_i2c1>;
357	pinctrl-1 = <&pinctrl_i2c1_gpio>;
358	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
359	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
360	status = "okay";
361
362	sgtl5000: audio-codec@a {
363		compatible = "fsl,sgtl5000";
364		reg = <0x0a>;
365		#sound-dai-cells = <0>;
366		clocks = <&clk_pwm4>;
367		VDDA-supply = <&buck4>;
368		VDDIO-supply = <&buck4>;
369	};
370
371	usb-hub@2c {
372		compatible = "microchip,usb2514bi";
373		reg = <0x2c>;
374		pinctrl-names = "default";
375		pinctrl-0 = <&pinctrl_usb_hub>;
376		individual-port-switching;
377		reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
378		self-powered;
379	};
380
381	eeprom: eeprom@50 {
382		compatible = "atmel,24c32";
383		reg = <0x50>;
384		pagesize = <32>;
385	};
386
387	rtc: rtc@68 {
388		compatible = "st,m41t62";
389		reg = <0x68>;
390		pinctrl-names = "default";
391		pinctrl-0 = <&pinctrl_rtc>;
392		interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>;
393	};
394
395	pcieclk: clk@6a {
396		compatible = "renesas,9fgv0241";
397		reg = <0x6a>;
398		clocks = <&clk_xtal25>;
399		#clock-cells = <1>;
400	};
401};
402
403&i2c2 {
404	clock-frequency = <100000>;
405	pinctrl-names = "default", "gpio";
406	pinctrl-0 = <&pinctrl_i2c2>;
407	pinctrl-1 = <&pinctrl_i2c2_gpio>;
408	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
409	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
410	status = "okay";
411};
412
413&i2c3 {
414	clock-frequency = <100000>;
415	pinctrl-names = "default", "gpio";
416	pinctrl-0 = <&pinctrl_i2c3>;
417	pinctrl-1 = <&pinctrl_i2c3_gpio>;
418	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
419	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
420	status = "okay";
421
422	pmic: pmic@25 {
423		compatible = "nxp,pca9450c";
424		reg = <0x25>;
425		pinctrl-names = "default";
426		pinctrl-0 = <&pinctrl_pmic>;
427		interrupt-parent = <&gpio1>;
428		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
429
430		/*
431		 * i.MX 8M Plus Data Sheet for Consumer Products
432		 * 3.1.4 Operating ranges
433		 * MIMX8ML8CVNKZAB
434		 */
435		regulators {
436			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
437				regulator-min-microvolt = <850000>;
438				regulator-max-microvolt = <1000000>;
439				regulator-ramp-delay = <3125>;
440				regulator-always-on;
441				regulator-boot-on;
442			};
443
444			buck2: BUCK2 {	/* VDD_ARM */
445				nxp,dvs-run-voltage = <950000>;
446				nxp,dvs-standby-voltage = <850000>;
447				regulator-min-microvolt = <850000>;
448				regulator-max-microvolt = <1000000>;
449				regulator-ramp-delay = <3125>;
450				regulator-always-on;
451				regulator-boot-on;
452			};
453
454			buck4: BUCK4 {	/* VDD_3V3 */
455				regulator-min-microvolt = <3300000>;
456				regulator-max-microvolt = <3300000>;
457				regulator-always-on;
458				regulator-boot-on;
459			};
460
461			buck5: BUCK5 {	/* VDD_1V8 */
462				regulator-min-microvolt = <1800000>;
463				regulator-max-microvolt = <1800000>;
464				regulator-always-on;
465				regulator-boot-on;
466			};
467
468			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
469				regulator-min-microvolt = <1100000>;
470				regulator-max-microvolt = <1100000>;
471				regulator-always-on;
472				regulator-boot-on;
473			};
474
475			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
476				regulator-min-microvolt = <1800000>;
477				regulator-max-microvolt = <1800000>;
478				regulator-always-on;
479				regulator-boot-on;
480			};
481
482			ldo3: LDO3 {	/* VDDA_1V8 */
483				regulator-min-microvolt = <1800000>;
484				regulator-max-microvolt = <1800000>;
485				regulator-always-on;
486				regulator-boot-on;
487			};
488
489			ldo4: LDO4 {	/* PMIC_LDO4 */
490				regulator-min-microvolt = <3300000>;
491				regulator-max-microvolt = <3300000>;
492			};
493
494			ldo5: LDO5 {	/* NVCC_SD2 */
495				regulator-min-microvolt = <1800000>;
496				regulator-max-microvolt = <3300000>;
497			};
498		};
499	};
500};
501
502&i2c5 {	/* HDMI EDID bus */
503	clock-frequency = <100000>;
504	pinctrl-names = "default", "gpio";
505	pinctrl-0 = <&pinctrl_i2c5>;
506	pinctrl-1 = <&pinctrl_i2c5_gpio>;
507	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
508	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
509	status = "okay";
510};
511
512&pcie_phy {
513	clocks = <&pcieclk 0>;
514	clock-names = "ref";
515	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
516	status = "okay";
517};
518
519&pcie {
520	pinctrl-names = "default";
521	pinctrl-0 = <&pinctrl_pcie0>;
522	fsl,max-link-speed = <3>;
523	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
524	status = "okay";
525};
526
527&pwm1 {
528	pinctrl-names = "default";
529	pinctrl-0 = <&pinctrl_panel_pwm>;
530	/* Disabled by default, unless display board plugged in. */
531	status = "disabled";
532};
533
534&pwm4 {
535	pinctrl-names = "default";
536	pinctrl-0 = <&pinctrl_pwm4>;
537	status = "okay";
538};
539
540&sai3 {
541	#sound-dai-cells = <0>;
542	assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
543	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
544	assigned-clock-rates = <12288000>;
545	pinctrl-names = "default";
546	pinctrl-0 = <&pinctrl_sai3>;
547	status = "okay";
548};
549
550/* SD slot */
551&usdhc2 {
552	pinctrl-names = "default", "state_100mhz", "state_200mhz";
553	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
554	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
555	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
556	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
557	vmmc-supply = <&reg_usdhc2_vmmc>;
558	bus-width = <4>;
559	status = "okay";
560};
561
562/* eMMC */
563&usdhc3 {
564	pinctrl-names = "default", "state_100mhz", "state_200mhz";
565	pinctrl-0 = <&pinctrl_usdhc3>;
566	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
567	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
568	vmmc-supply = <&buck4>;
569	vqmmc-supply = <&buck5>;
570	bus-width = <8>;
571	no-sd;
572	no-sdio;
573	non-removable;
574	status = "okay";
575};
576
577&uart1 {	/* RS485 */
578	pinctrl-names = "default";
579	pinctrl-0 = <&pinctrl_uart1>;
580	uart-has-rtscts;
581	status = "disabled";	/* Optional */
582};
583
584&uart2 {
585	pinctrl-names = "default";
586	pinctrl-0 = <&pinctrl_uart2>;
587	uart-has-rtscts;
588	status = "okay";
589};
590
591&uart3 {	/* A53 Debug */
592	pinctrl-names = "default";
593	pinctrl-0 = <&pinctrl_uart3>;
594	status = "okay";
595};
596
597&uart4 {
598	pinctrl-names = "default";
599	pinctrl-0 = <&pinctrl_uart4>;
600	status = "disabled";
601};
602
603&usb3_phy0 {
604	status = "okay";
605};
606
607&usb3_0 {
608	fsl,over-current-active-low;
609	status = "okay";
610};
611
612&usb_dwc3_0 {	/* Lower plug direct */
613	pinctrl-names = "default";
614	pinctrl-0 = <&pinctrl_usb1>;
615	dr_mode = "host";
616	status = "okay";
617};
618
619&usb3_phy1 {
620	status = "okay";
621};
622
623&usb3_1 {
624	status = "okay";
625};
626
627&usb_dwc3_1 {	/* Upper plug via HUB */
628	dr_mode = "host";
629	status = "okay";
630};
631
632&wdog1 {
633	status = "okay";
634};
635
636/* IOMUXC node should be at the end of DT to improve readability. */
637&iomuxc {
638	pinctrl-names = "default";
639	pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
640		    <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
641		    <&pinctrl_panel_expansion>;
642
643	pinctrl_ecspi1: ecspi1-grp {
644		fsl,pins = <
645			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x44
646			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x44
647			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x44
648			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x40
649		>;
650	};
651
652	pinctrl_ecspi2: ecspi2-grp {
653		fsl,pins = <
654			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
655			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
656			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
657			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
658		>;
659	};
660
661	pinctrl_ecspi3: ecspi3-grp {
662		fsl,pins = <
663			MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK		0x44
664			MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI		0x44
665			MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO		0x44
666			MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25		0x40
667		>;
668	};
669
670	pinctrl_eqos: eqos-grp {
671		fsl,pins = <
672			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
673			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
674			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
675			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
676			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
677			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
678			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
679			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
680			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
681			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
682			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
683			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
684			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
685			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
686			/* ENET_RST# */
687			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x6
688			/* ENET_INT# */
689			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x40000090
690		>;
691	};
692
693	pinctrl_fec: fec-grp {
694		fsl,pins = <
695			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
696			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
697			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
698			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
699			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
700			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
701			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
702			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
703			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
704			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
705			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
706			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
707			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
708			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
709			/* ENET2_RST# */
710			MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x6
711			/* ENET2_INT# */
712			MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02		0x40000090
713		>;
714	};
715
716	pinctrl_flexcan1: flexcan1-grp {
717		fsl,pins = <
718			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
719			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
720		>;
721	};
722
723	pinctrl_hdmi: hdmi-grp {
724		fsl,pins = <
725			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
726			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
727		>;
728	};
729
730	pinctrl_hog_feature: hog-feature-grp {
731		fsl,pins = <
732			/* GPIO5_IO03 */
733			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x40000006
734			/* GPIO5_IO04 */
735			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x40000006
736
737			/* CAN_INT# */
738			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x40000090
739		>;
740	};
741
742	pinctrl_hog_panel: hog-panel-grp {
743		fsl,pins = <
744			/* GRAPHICS_GPIO0_1V8 */
745			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07		0x26
746		>;
747	};
748
749	pinctrl_hog_misc: hog-misc-grp {
750		fsl,pins = <
751			/* ENET_WOL# -- shared by both PHYs */
752			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x40000090
753
754			/* PG_V_IN_VAR# */
755			MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01		0x40000000
756			/* CSI2_PD_1V8 */
757			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08		0x0
758			/* CSI2_RESET_1V8# */
759			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09		0x0
760
761			/* DIS_USB_DN1 */
762			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x0
763			/* DIS_USB_DN2 */
764			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x0
765
766			/* EEPROM_WP_1V8# */
767			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x100
768			/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
769			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x0
770			/* GRAPHICS_PRSNT_1V8# */
771			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x40000000
772
773			/* CLK_CCM_CLKO1_3V3 */
774			MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1		0x10
775		>;
776	};
777
778	pinctrl_hog_sbc: hog-sbc-grp {
779		fsl,pins = <
780			/* MEMCFG[0..2] straps */
781			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x40000140
782			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x40000140
783			MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x40000140
784		>;
785	};
786
787	pinctrl_i2c1: i2c1-grp {
788		fsl,pins = <
789			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL			0x40000084
790			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA			0x40000084
791		>;
792	};
793
794	pinctrl_i2c1_gpio: i2c1-gpio-grp {
795		fsl,pins = <
796			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x84
797			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x84
798		>;
799	};
800
801	pinctrl_i2c2: i2c2-grp {
802		fsl,pins = <
803			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x40000084
804			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x40000084
805		>;
806	};
807
808	pinctrl_i2c2_gpio: i2c2-gpio-grp {
809		fsl,pins = <
810			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x84
811			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x84
812		>;
813	};
814
815	pinctrl_i2c3: i2c3-grp {
816		fsl,pins = <
817			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
818			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
819		>;
820	};
821
822	pinctrl_i2c3_gpio: i2c3-gpio-grp {
823		fsl,pins = <
824			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
825			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
826		>;
827	};
828
829	pinctrl_i2c5: i2c5-grp {
830		fsl,pins = <
831			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
832			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
833		>;
834	};
835
836	pinctrl_i2c5_gpio: i2c5-gpio-grp {
837		fsl,pins = <
838			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
839			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
840		>;
841	};
842
843	pinctrl_panel_backlight: panel-backlight-grp {
844		fsl,pins = <
845			/* BL_ENABLE_1V8 */
846			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00		0x104
847		>;
848	};
849
850	pinctrl_panel_expansion: panel-expansion-grp {
851		fsl,pins = <
852			/* DSI_RESET_1V8# */
853			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x2
854			/* DSI_IRQ_1V8# */
855			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000090
856		>;
857	};
858
859	pinctrl_panel_pwm: panel-pwm-grp {
860		fsl,pins = <
861			/* BL_PWM_3V3 */
862			MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT			0x12
863		>;
864	};
865
866	pinctrl_panel_vcc_reg: panel-vcc-grp {
867		fsl,pins = <
868			/* TFT_ENABLE_1V8 */
869			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06		0x104
870		>;
871	};
872
873	pinctrl_pcie0: pcie-grp {
874		fsl,pins = <
875			/* M2_PCIE_RST# */
876			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
877			/* M2_W_DISABLE1_1V8# */
878			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x2
879			/* M2_W_DISABLE2_1V8# */
880			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x2
881			/* CLK_M2_32K768 */
882			MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1		0x14
883			/* M2_PCIE_WAKE# */
884			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x40000140
885			/* M2_PCIE_CLKREQ# */
886			MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B		0x61
887		>;
888	};
889
890	pinctrl_pdm: pdm-grp {
891		fsl,pins = <
892			/* PDM_SEL */
893			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x0
894			MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK		0x0
895			MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00	0x0
896		>;
897	};
898
899	pinctrl_pmic: pmic-grp {
900		fsl,pins = <
901			/* PMIC_nINT */
902			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
903		>;
904	};
905
906	pinctrl_pwm4: pwm4-grp {
907		fsl,pins = <
908			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT		0xd6
909		>;
910	};
911
912	pinctrl_rtc: rtc-grp {
913		fsl,pins = <
914			/* RTC_IRQ# */
915			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x40000090
916		>;
917	};
918
919	pinctrl_sai1: sai1-grp {
920		fsl,pins = <
921			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC	0xd6
922			MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00	0xd6
923			MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK	0xd6
924			MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK	0xd6
925			MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00	0xd6
926		>;
927	};
928
929	pinctrl_sai2: sai2-grp {
930		fsl,pins = <
931			MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC	0xd6
932			MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00	0xd6
933			MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK	0xd6
934			MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK	0xd6
935		>;
936	};
937
938	pinctrl_sai3: sai3-grp {
939		fsl,pins = <
940			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
941			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
942			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
943			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
944		>;
945	};
946
947	pinctrl_uart1: uart1-grp {
948		fsl,pins = <
949			MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX		0x49
950			MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX		0x49
951			MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS		0x49
952			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
953		>;
954	};
955
956	pinctrl_uart2: uart2-grp {
957		fsl,pins = <
958			MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX		0x49
959			MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX		0x49
960			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
961			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
962		>;
963	};
964
965	pinctrl_uart3: uart3-grp {
966		fsl,pins = <
967			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x49
968			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x49
969		>;
970	};
971
972	pinctrl_uart4: uart4-grp {
973		fsl,pins = <
974			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
975			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
976		>;
977	};
978
979	pinctrl_usdhc2: usdhc2-grp {
980		fsl,pins = <
981			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
982			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
983			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
984			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
985			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
986			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
987			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
988		>;
989	};
990
991	pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
992		fsl,pins = <
993			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
994			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
995			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
996			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
997			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
998			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
999			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1000		>;
1001	};
1002
1003	pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
1004		fsl,pins = <
1005			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
1006			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
1007			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
1008			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
1009			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
1010			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
1011			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
1012		>;
1013	};
1014
1015	pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
1016		fsl,pins = <
1017			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
1018		>;
1019	};
1020
1021	pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
1022		fsl,pins = <
1023			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
1024		>;
1025	};
1026
1027	pinctrl_usdhc3: usdhc3-grp {
1028		fsl,pins = <
1029			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
1030			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
1031			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
1032			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
1033			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
1034			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
1035			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
1036			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
1037			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
1038			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
1039			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
1040			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1041		>;
1042	};
1043
1044	pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
1045		fsl,pins = <
1046			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
1047			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
1048			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
1049			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
1050			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
1051			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
1052			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
1053			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
1054			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
1055			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
1056			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
1057			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1058		>;
1059	};
1060
1061	pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
1062		fsl,pins = <
1063			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
1064			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
1065			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
1066			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
1067			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
1068			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
1069			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
1070			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
1071			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
1072			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
1073			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
1074			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1075		>;
1076	};
1077
1078	pinctrl_usb_hub: usb-hub-grp {
1079		fsl,pins = <
1080			/* USBHUB_RESET# */
1081			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x4
1082		>;
1083	};
1084
1085	pinctrl_usb1: usb1-grp {
1086		fsl,pins = <
1087			MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR		0x6
1088			MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC		0x80
1089		>;
1090	};
1091
1092	pinctrl_watchdog_gpio: watchdog-gpio-grp {
1093		fsl,pins = <
1094			/* WDOG_B# */
1095			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0x26
1096			/* WDOG_EN -- ungate WDT RESET# signal propagation */
1097			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x6
1098			/* WDOG_KICK# / WDI */
1099			MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x26
1100		>;
1101	};
1102};
1103