1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clocks = <&clk IMX8MN_CLK_ARM>; 66 enable-method = "psci"; 67 i-cache-size = <0x8000>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <256>; 70 d-cache-size = <0x8000>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&A53_L2>; 74 operating-points-v2 = <&a53_opp_table>; 75 nvmem-cells = <&cpu_speed_grade>; 76 nvmem-cell-names = "speed_grade"; 77 cpu-idle-states = <&cpu_pd_wait>; 78 #cooling-cells = <2>; 79 }; 80 81 A53_1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x1>; 85 clocks = <&clk IMX8MN_CLK_ARM>; 86 enable-method = "psci"; 87 i-cache-size = <0x8000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <256>; 90 d-cache-size = <0x8000>; 91 d-cache-line-size = <64>; 92 d-cache-sets = <128>; 93 next-level-cache = <&A53_L2>; 94 operating-points-v2 = <&a53_opp_table>; 95 cpu-idle-states = <&cpu_pd_wait>; 96 #cooling-cells = <2>; 97 }; 98 99 A53_2: cpu@2 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x2>; 103 clocks = <&clk IMX8MN_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 operating-points-v2 = <&a53_opp_table>; 113 cpu-idle-states = <&cpu_pd_wait>; 114 #cooling-cells = <2>; 115 }; 116 117 A53_3: cpu@3 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x3>; 121 clocks = <&clk IMX8MN_CLK_ARM>; 122 enable-method = "psci"; 123 i-cache-size = <0x8000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <256>; 126 d-cache-size = <0x8000>; 127 d-cache-line-size = <64>; 128 d-cache-sets = <128>; 129 next-level-cache = <&A53_L2>; 130 operating-points-v2 = <&a53_opp_table>; 131 cpu-idle-states = <&cpu_pd_wait>; 132 #cooling-cells = <2>; 133 }; 134 135 A53_L2: l2-cache0 { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 cache-size = <0x80000>; 140 cache-line-size = <64>; 141 cache-sets = <512>; 142 }; 143 }; 144 145 a53_opp_table: opp-table { 146 compatible = "operating-points-v2"; 147 opp-shared; 148 149 opp-1200000000 { 150 opp-hz = /bits/ 64 <1200000000>; 151 opp-microvolt = <850000>; 152 opp-supported-hw = <0xb00>, <0x7>; 153 clock-latency-ns = <150000>; 154 opp-suspend; 155 }; 156 157 opp-1400000000 { 158 opp-hz = /bits/ 64 <1400000000>; 159 opp-microvolt = <950000>; 160 opp-supported-hw = <0x300>, <0x7>; 161 clock-latency-ns = <150000>; 162 opp-suspend; 163 }; 164 165 opp-1500000000 { 166 opp-hz = /bits/ 64 <1500000000>; 167 opp-microvolt = <1000000>; 168 opp-supported-hw = <0x100>, <0x3>; 169 clock-latency-ns = <150000>; 170 opp-suspend; 171 }; 172 }; 173 174 osc_32k: clock-osc-32k { 175 compatible = "fixed-clock"; 176 #clock-cells = <0>; 177 clock-frequency = <32768>; 178 clock-output-names = "osc_32k"; 179 }; 180 181 osc_24m: clock-osc-24m { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <24000000>; 185 clock-output-names = "osc_24m"; 186 }; 187 188 clk_ext1: clock-ext1 { 189 compatible = "fixed-clock"; 190 #clock-cells = <0>; 191 clock-frequency = <133000000>; 192 clock-output-names = "clk_ext1"; 193 }; 194 195 clk_ext2: clock-ext2 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <133000000>; 199 clock-output-names = "clk_ext2"; 200 }; 201 202 clk_ext3: clock-ext3 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <133000000>; 206 clock-output-names = "clk_ext3"; 207 }; 208 209 clk_ext4: clock-ext4 { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <133000000>; 213 clock-output-names = "clk_ext4"; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 }; 258 259 timer { 260 compatible = "arm,armv8-timer"; 261 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 262 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 263 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 264 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 265 clock-frequency = <8000000>; 266 arm,no-tick-in-suspend; 267 }; 268 269 soc: soc@0 { 270 compatible = "fsl,imx8mn-soc", "simple-bus"; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges = <0x0 0x0 0x0 0x3e000000>; 274 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 275 nvmem-cells = <&imx8mn_uid>; 276 nvmem-cell-names = "soc_unique_id"; 277 278 aips1: bus@30000000 { 279 compatible = "fsl,aips-bus", "simple-bus"; 280 reg = <0x30000000 0x400000>; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 ranges; 284 285 spba2: spba-bus@30000000 { 286 compatible = "fsl,spba-bus", "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 reg = <0x30000000 0x100000>; 290 ranges; 291 292 sai2: sai@30020000 { 293 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 294 reg = <0x30020000 0x10000>; 295 #sound-dai-cells = <0>; 296 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 298 <&clk IMX8MN_CLK_DUMMY>, 299 <&clk IMX8MN_CLK_SAI2_ROOT>, 300 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 302 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 303 dma-names = "rx", "tx"; 304 status = "disabled"; 305 }; 306 307 sai3: sai@30030000 { 308 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 309 reg = <0x30030000 0x10000>; 310 #sound-dai-cells = <0>; 311 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 313 <&clk IMX8MN_CLK_DUMMY>, 314 <&clk IMX8MN_CLK_SAI3_ROOT>, 315 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 316 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 317 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 318 dma-names = "rx", "tx"; 319 status = "disabled"; 320 }; 321 322 sai5: sai@30050000 { 323 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 324 reg = <0x30050000 0x10000>; 325 #sound-dai-cells = <0>; 326 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 328 <&clk IMX8MN_CLK_DUMMY>, 329 <&clk IMX8MN_CLK_SAI5_ROOT>, 330 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 331 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 332 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 333 dma-names = "rx", "tx"; 334 fsl,shared-interrupt; 335 fsl,dataline = <0 0xf 0xf>; 336 status = "disabled"; 337 }; 338 339 sai6: sai@30060000 { 340 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 341 reg = <0x30060000 0x10000>; 342 #sound-dai-cells = <0>; 343 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 345 <&clk IMX8MN_CLK_DUMMY>, 346 <&clk IMX8MN_CLK_SAI6_ROOT>, 347 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 348 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 micfil: audio-controller@30080000 { 355 compatible = "fsl,imx8mm-micfil"; 356 reg = <0x30080000 0x10000>; 357 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 362 <&clk IMX8MN_CLK_PDM_ROOT>, 363 <&clk IMX8MN_AUDIO_PLL1_OUT>, 364 <&clk IMX8MN_AUDIO_PLL2_OUT>, 365 <&clk IMX8MN_CLK_EXT3>; 366 clock-names = "ipg_clk", "ipg_clk_app", 367 "pll8k", "pll11k", "clkext3"; 368 dmas = <&sdma2 24 25 0x80000000>; 369 dma-names = "rx"; 370 #sound-dai-cells = <0>; 371 status = "disabled"; 372 }; 373 374 spdif1: spdif@30090000 { 375 compatible = "fsl,imx35-spdif"; 376 reg = <0x30090000 0x10000>; 377 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 379 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 380 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 381 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 382 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 383 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 384 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 386 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 387 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 388 clock-names = "core", "rxtx0", 389 "rxtx1", "rxtx2", 390 "rxtx3", "rxtx4", 391 "rxtx5", "rxtx6", 392 "rxtx7", "spba"; 393 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 394 dma-names = "rx", "tx"; 395 status = "disabled"; 396 }; 397 398 sai7: sai@300b0000 { 399 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 400 reg = <0x300b0000 0x10000>; 401 #sound-dai-cells = <0>; 402 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 404 <&clk IMX8MN_CLK_DUMMY>, 405 <&clk IMX8MN_CLK_SAI7_ROOT>, 406 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 408 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 409 dma-names = "rx", "tx"; 410 status = "disabled"; 411 }; 412 413 easrc: easrc@300c0000 { 414 compatible = "fsl,imx8mn-easrc"; 415 reg = <0x300c0000 0x10000>; 416 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 418 clock-names = "mem"; 419 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 420 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 421 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 422 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 423 dma-names = "ctx0_rx", "ctx0_tx", 424 "ctx1_rx", "ctx1_tx", 425 "ctx2_rx", "ctx2_tx", 426 "ctx3_rx", "ctx3_tx"; 427 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 428 fsl,asrc-rate = <8000>; 429 fsl,asrc-format = <2>; 430 status = "disabled"; 431 }; 432 }; 433 434 gpio1: gpio@30200000 { 435 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 436 reg = <0x30200000 0x10000>; 437 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 gpio-ranges = <&iomuxc 0 10 30>; 445 }; 446 447 gpio2: gpio@30210000 { 448 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 449 reg = <0x30210000 0x10000>; 450 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 gpio-ranges = <&iomuxc 0 40 21>; 458 }; 459 460 gpio3: gpio@30220000 { 461 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 462 reg = <0x30220000 0x10000>; 463 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 gpio-ranges = <&iomuxc 0 61 26>; 471 }; 472 473 gpio4: gpio@30230000 { 474 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 475 reg = <0x30230000 0x10000>; 476 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 gpio-ranges = <&iomuxc 21 108 11>; 484 }; 485 486 gpio5: gpio@30240000 { 487 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 488 reg = <0x30240000 0x10000>; 489 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 gpio-ranges = <&iomuxc 0 119 30>; 497 }; 498 499 tmu: tmu@30260000 { 500 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 501 reg = <0x30260000 0x10000>; 502 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 503 nvmem-cells = <&tmu_calib>; 504 nvmem-cell-names = "calib"; 505 #thermal-sensor-cells = <0>; 506 }; 507 508 wdog1: watchdog@30280000 { 509 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 510 reg = <0x30280000 0x10000>; 511 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 513 status = "disabled"; 514 }; 515 516 wdog2: watchdog@30290000 { 517 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 518 reg = <0x30290000 0x10000>; 519 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 521 status = "disabled"; 522 }; 523 524 wdog3: watchdog@302a0000 { 525 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 526 reg = <0x302a0000 0x10000>; 527 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 529 status = "disabled"; 530 }; 531 532 sdma3: dma-controller@302b0000 { 533 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 534 reg = <0x302b0000 0x10000>; 535 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 537 <&clk IMX8MN_CLK_SDMA3_ROOT>; 538 clock-names = "ipg", "ahb"; 539 #dma-cells = <3>; 540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 541 }; 542 543 sdma2: dma-controller@302c0000 { 544 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 545 reg = <0x302c0000 0x10000>; 546 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 548 <&clk IMX8MN_CLK_SDMA2_ROOT>; 549 clock-names = "ipg", "ahb"; 550 #dma-cells = <3>; 551 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 552 }; 553 554 iomuxc: pinctrl@30330000 { 555 compatible = "fsl,imx8mn-iomuxc"; 556 reg = <0x30330000 0x10000>; 557 }; 558 559 gpr: syscon@30340000 { 560 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 561 reg = <0x30340000 0x10000>; 562 }; 563 564 ocotp: efuse@30350000 { 565 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 566 reg = <0x30350000 0x10000>; 567 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 571 /* 572 * The register address below maps to the MX8M 573 * Fusemap Description Table entries this way. 574 * Assuming 575 * reg = <ADDR SIZE>; 576 * then 577 * Fuse Address = (ADDR * 4) + 0x400 578 * Note that if SIZE is greater than 4, then 579 * each subsequent fuse is located at offset 580 * +0x10 in Fusemap Description Table (e.g. 581 * reg = <0x4 0x8> describes fuses 0x410 and 582 * 0x420). 583 */ 584 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ 585 reg = <0x4 0x8>; 586 }; 587 588 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 589 reg = <0x10 4>; 590 }; 591 592 tmu_calib: calib@3c { /* 0x4f0 */ 593 reg = <0x3c 4>; 594 }; 595 596 fec_mac_address: mac-address@90 { /* 0x640 */ 597 reg = <0x90 6>; 598 }; 599 }; 600 601 anatop: clock-controller@30360000 { 602 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; 603 reg = <0x30360000 0x10000>; 604 #clock-cells = <1>; 605 }; 606 607 snvs: snvs@30370000 { 608 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 609 reg = <0x30370000 0x10000>; 610 611 snvs_rtc: snvs-rtc-lp { 612 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 613 regmap = <&snvs>; 614 offset = <0x34>; 615 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 618 clock-names = "snvs-rtc"; 619 }; 620 621 snvs_pwrkey: snvs-powerkey { 622 compatible = "fsl,sec-v4.0-pwrkey"; 623 regmap = <&snvs>; 624 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 626 clock-names = "snvs-pwrkey"; 627 linux,keycode = <KEY_POWER>; 628 wakeup-source; 629 status = "disabled"; 630 }; 631 }; 632 633 clk: clock-controller@30380000 { 634 compatible = "fsl,imx8mn-ccm"; 635 reg = <0x30380000 0x10000>; 636 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 638 #clock-cells = <1>; 639 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 640 <&clk_ext3>, <&clk_ext4>; 641 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 642 "clk_ext3", "clk_ext4"; 643 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 644 <&clk IMX8MN_CLK_A53_CORE>, 645 <&clk IMX8MN_CLK_NOC>, 646 <&clk IMX8MN_CLK_AUDIO_AHB>, 647 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 648 <&clk IMX8MN_SYS_PLL3>, 649 <&clk IMX8MN_AUDIO_PLL1>, 650 <&clk IMX8MN_AUDIO_PLL2>; 651 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 652 <&clk IMX8MN_ARM_PLL_OUT>, 653 <&clk IMX8MN_SYS_PLL3_OUT>, 654 <&clk IMX8MN_SYS_PLL1_800M>; 655 assigned-clock-rates = <0>, <0>, <0>, 656 <400000000>, 657 <400000000>, 658 <600000000>, 659 <393216000>, 660 <361267200>; 661 }; 662 663 src: reset-controller@30390000 { 664 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 665 reg = <0x30390000 0x10000>; 666 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 667 #reset-cells = <1>; 668 }; 669 670 gpc: gpc@303a0000 { 671 compatible = "fsl,imx8mn-gpc"; 672 reg = <0x303a0000 0x10000>; 673 interrupt-parent = <&gic>; 674 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 675 676 pgc { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 pgc_hsiomix: power-domain@0 { 681 #power-domain-cells = <0>; 682 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 683 clocks = <&clk IMX8MN_CLK_USB_BUS>; 684 }; 685 686 pgc_otg1: power-domain@1 { 687 #power-domain-cells = <0>; 688 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 689 }; 690 691 pgc_gpumix: power-domain@2 { 692 #power-domain-cells = <0>; 693 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 694 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 695 <&clk IMX8MN_CLK_GPU_SHADER>, 696 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 697 <&clk IMX8MN_CLK_GPU_AHB>; 698 }; 699 700 pgc_dispmix: power-domain@3 { 701 #power-domain-cells = <0>; 702 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 703 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 704 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 705 }; 706 707 pgc_mipi: power-domain@4 { 708 #power-domain-cells = <0>; 709 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 710 power-domains = <&pgc_dispmix>; 711 }; 712 }; 713 }; 714 }; 715 716 aips2: bus@30400000 { 717 compatible = "fsl,aips-bus", "simple-bus"; 718 reg = <0x30400000 0x400000>; 719 #address-cells = <1>; 720 #size-cells = <1>; 721 ranges; 722 723 pwm1: pwm@30660000 { 724 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 725 reg = <0x30660000 0x10000>; 726 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 728 <&clk IMX8MN_CLK_PWM1_ROOT>; 729 clock-names = "ipg", "per"; 730 #pwm-cells = <3>; 731 status = "disabled"; 732 }; 733 734 pwm2: pwm@30670000 { 735 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 736 reg = <0x30670000 0x10000>; 737 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 739 <&clk IMX8MN_CLK_PWM2_ROOT>; 740 clock-names = "ipg", "per"; 741 #pwm-cells = <3>; 742 status = "disabled"; 743 }; 744 745 pwm3: pwm@30680000 { 746 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 747 reg = <0x30680000 0x10000>; 748 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 750 <&clk IMX8MN_CLK_PWM3_ROOT>; 751 clock-names = "ipg", "per"; 752 #pwm-cells = <3>; 753 status = "disabled"; 754 }; 755 756 pwm4: pwm@30690000 { 757 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 758 reg = <0x30690000 0x10000>; 759 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 761 <&clk IMX8MN_CLK_PWM4_ROOT>; 762 clock-names = "ipg", "per"; 763 #pwm-cells = <3>; 764 status = "disabled"; 765 }; 766 767 system_counter: timer@306a0000 { 768 compatible = "nxp,sysctr-timer"; 769 reg = <0x306a0000 0x20000>; 770 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&osc_24m>; 772 clock-names = "per"; 773 }; 774 }; 775 776 aips3: bus@30800000 { 777 compatible = "fsl,aips-bus", "simple-bus"; 778 reg = <0x30800000 0x400000>; 779 #address-cells = <1>; 780 #size-cells = <1>; 781 ranges; 782 783 spba1: spba-bus@30800000 { 784 compatible = "fsl,spba-bus", "simple-bus"; 785 #address-cells = <1>; 786 #size-cells = <1>; 787 reg = <0x30800000 0x100000>; 788 ranges; 789 790 ecspi1: spi@30820000 { 791 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 reg = <0x30820000 0x10000>; 795 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 797 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 798 clock-names = "ipg", "per"; 799 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 800 dma-names = "rx", "tx"; 801 status = "disabled"; 802 }; 803 804 ecspi2: spi@30830000 { 805 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 reg = <0x30830000 0x10000>; 809 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 811 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 812 clock-names = "ipg", "per"; 813 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 814 dma-names = "rx", "tx"; 815 status = "disabled"; 816 }; 817 818 ecspi3: spi@30840000 { 819 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 reg = <0x30840000 0x10000>; 823 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 825 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 826 clock-names = "ipg", "per"; 827 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 828 dma-names = "rx", "tx"; 829 status = "disabled"; 830 }; 831 832 uart1: serial@30860000 { 833 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 834 reg = <0x30860000 0x10000>; 835 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 837 <&clk IMX8MN_CLK_UART1_ROOT>; 838 clock-names = "ipg", "per"; 839 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 840 dma-names = "rx", "tx"; 841 status = "disabled"; 842 }; 843 844 uart3: serial@30880000 { 845 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 846 reg = <0x30880000 0x10000>; 847 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 849 <&clk IMX8MN_CLK_UART3_ROOT>; 850 clock-names = "ipg", "per"; 851 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 852 dma-names = "rx", "tx"; 853 status = "disabled"; 854 }; 855 856 uart2: serial@30890000 { 857 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 858 reg = <0x30890000 0x10000>; 859 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 861 <&clk IMX8MN_CLK_UART2_ROOT>; 862 clock-names = "ipg", "per"; 863 status = "disabled"; 864 }; 865 }; 866 867 crypto: crypto@30900000 { 868 compatible = "fsl,sec-v4.0"; 869 #address-cells = <1>; 870 #size-cells = <1>; 871 reg = <0x30900000 0x40000>; 872 ranges = <0 0x30900000 0x40000>; 873 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 874 clocks = <&clk IMX8MN_CLK_AHB>, 875 <&clk IMX8MN_CLK_IPG_ROOT>; 876 clock-names = "aclk", "ipg"; 877 878 sec_jr0: jr@1000 { 879 compatible = "fsl,sec-v4.0-job-ring"; 880 reg = <0x1000 0x1000>; 881 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 882 status = "disabled"; 883 }; 884 885 sec_jr1: jr@2000 { 886 compatible = "fsl,sec-v4.0-job-ring"; 887 reg = <0x2000 0x1000>; 888 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 889 }; 890 891 sec_jr2: jr@3000 { 892 compatible = "fsl,sec-v4.0-job-ring"; 893 reg = <0x3000 0x1000>; 894 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 895 }; 896 }; 897 898 i2c1: i2c@30a20000 { 899 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 reg = <0x30a20000 0x10000>; 903 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 905 status = "disabled"; 906 }; 907 908 i2c2: i2c@30a30000 { 909 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 reg = <0x30a30000 0x10000>; 913 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 915 status = "disabled"; 916 }; 917 918 i2c3: i2c@30a40000 { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 922 reg = <0x30a40000 0x10000>; 923 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 925 status = "disabled"; 926 }; 927 928 i2c4: i2c@30a50000 { 929 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 reg = <0x30a50000 0x10000>; 933 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 935 status = "disabled"; 936 }; 937 938 uart4: serial@30a60000 { 939 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 940 reg = <0x30a60000 0x10000>; 941 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 943 <&clk IMX8MN_CLK_UART4_ROOT>; 944 clock-names = "ipg", "per"; 945 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 946 dma-names = "rx", "tx"; 947 status = "disabled"; 948 }; 949 950 mu: mailbox@30aa0000 { 951 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 952 reg = <0x30aa0000 0x10000>; 953 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 955 #mbox-cells = <2>; 956 }; 957 958 usdhc1: mmc@30b40000 { 959 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 960 reg = <0x30b40000 0x10000>; 961 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 963 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 964 <&clk IMX8MN_CLK_USDHC1_ROOT>; 965 clock-names = "ipg", "ahb", "per"; 966 fsl,tuning-start-tap = <20>; 967 fsl,tuning-step = <2>; 968 bus-width = <4>; 969 status = "disabled"; 970 }; 971 972 usdhc2: mmc@30b50000 { 973 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 974 reg = <0x30b50000 0x10000>; 975 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 977 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 978 <&clk IMX8MN_CLK_USDHC2_ROOT>; 979 clock-names = "ipg", "ahb", "per"; 980 fsl,tuning-start-tap = <20>; 981 fsl,tuning-step = <2>; 982 bus-width = <4>; 983 status = "disabled"; 984 }; 985 986 usdhc3: mmc@30b60000 { 987 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 988 reg = <0x30b60000 0x10000>; 989 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 991 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 992 <&clk IMX8MN_CLK_USDHC3_ROOT>; 993 clock-names = "ipg", "ahb", "per"; 994 fsl,tuning-start-tap = <20>; 995 fsl,tuning-step = <2>; 996 bus-width = <4>; 997 status = "disabled"; 998 }; 999 1000 flexspi: spi@30bb0000 { 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 compatible = "nxp,imx8mm-fspi"; 1004 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1005 reg-names = "fspi_base", "fspi_mmap"; 1006 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 1008 <&clk IMX8MN_CLK_QSPI_ROOT>; 1009 clock-names = "fspi_en", "fspi"; 1010 status = "disabled"; 1011 }; 1012 1013 sdma1: dma-controller@30bd0000 { 1014 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 1015 reg = <0x30bd0000 0x10000>; 1016 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 1018 <&clk IMX8MN_CLK_AHB>; 1019 clock-names = "ipg", "ahb"; 1020 #dma-cells = <3>; 1021 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1022 }; 1023 1024 fec1: ethernet@30be0000 { 1025 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1026 reg = <0x30be0000 0x10000>; 1027 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 1032 <&clk IMX8MN_CLK_ENET1_ROOT>, 1033 <&clk IMX8MN_CLK_ENET_TIMER>, 1034 <&clk IMX8MN_CLK_ENET_REF>, 1035 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1036 clock-names = "ipg", "ahb", "ptp", 1037 "enet_clk_ref", "enet_out"; 1038 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 1039 <&clk IMX8MN_CLK_ENET_TIMER>, 1040 <&clk IMX8MN_CLK_ENET_REF>, 1041 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1042 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1043 <&clk IMX8MN_SYS_PLL2_100M>, 1044 <&clk IMX8MN_SYS_PLL2_125M>, 1045 <&clk IMX8MN_SYS_PLL2_50M>; 1046 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1047 fsl,num-tx-queues = <3>; 1048 fsl,num-rx-queues = <3>; 1049 nvmem-cells = <&fec_mac_address>; 1050 nvmem-cell-names = "mac-address"; 1051 fsl,stop-mode = <&gpr 0x10 3>; 1052 status = "disabled"; 1053 }; 1054 1055 }; 1056 1057 aips4: bus@32c00000 { 1058 compatible = "fsl,aips-bus", "simple-bus"; 1059 reg = <0x32c00000 0x400000>; 1060 #address-cells = <1>; 1061 #size-cells = <1>; 1062 ranges; 1063 1064 lcdif: lcdif@32e00000 { 1065 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; 1066 reg = <0x32e00000 0x10000>; 1067 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1068 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1069 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1070 clock-names = "pix", "axi", "disp_axi"; 1071 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; 1073 status = "disabled"; 1074 1075 port { 1076 lcdif_to_dsim: endpoint { 1077 remote-endpoint = <&dsim_from_lcdif>; 1078 }; 1079 }; 1080 }; 1081 1082 mipi_dsi: dsi@32e10000 { 1083 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 1084 reg = <0x32e10000 0x400>; 1085 clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1086 <&clk IMX8MN_CLK_DSI_PHY_REF>; 1087 clock-names = "bus_clk", "sclk_mipi"; 1088 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1089 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; 1090 status = "disabled"; 1091 1092 ports { 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 1096 port@0 { 1097 reg = <0>; 1098 1099 dsim_from_lcdif: endpoint { 1100 remote-endpoint = <&lcdif_to_dsim>; 1101 }; 1102 }; 1103 1104 port@1 { 1105 reg = <1>; 1106 1107 mipi_dsi_out: endpoint { 1108 }; 1109 }; 1110 }; 1111 }; 1112 1113 isi: isi@32e20000 { 1114 compatible = "fsl,imx8mn-isi"; 1115 reg = <0x32e20000 0x8000>; 1116 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1118 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 1119 clock-names = "axi", "apb"; 1120 fsl,blk-ctrl = <&disp_blk_ctrl>; 1121 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>; 1122 status = "disabled"; 1123 1124 ports { 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 1128 port@0 { 1129 reg = <0>; 1130 isi_in: endpoint { 1131 remote-endpoint = <&mipi_csi_out>; 1132 }; 1133 }; 1134 }; 1135 }; 1136 1137 disp_blk_ctrl: blk-ctrl@32e28000 { 1138 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 1139 reg = <0x32e28000 0x100>; 1140 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1141 <&pgc_dispmix>, <&pgc_mipi>, 1142 <&pgc_mipi>; 1143 power-domain-names = "bus", "isi", 1144 "lcdif", "mipi-dsi", 1145 "mipi-csi"; 1146 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 1147 <&clk IMX8MN_CLK_DISP_APB>, 1148 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1149 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1150 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1151 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1152 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1153 <&clk IMX8MN_CLK_DSI_CORE>, 1154 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1155 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1156 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 1157 clock-names = "disp_axi", "disp_apb", 1158 "disp_axi_root", "disp_apb_root", 1159 "lcdif-axi", "lcdif-apb", "lcdif-pix", 1160 "dsi-pclk", "dsi-ref", 1161 "csi-aclk", "csi-pclk"; 1162 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1163 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1164 <&clk IMX8MN_CLK_DISP_PIXEL>, 1165 <&clk IMX8MN_CLK_DISP_AXI>, 1166 <&clk IMX8MN_CLK_DISP_APB>; 1167 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1168 <&clk IMX8MN_CLK_24M>, 1169 <&clk IMX8MN_VIDEO_PLL1_OUT>, 1170 <&clk IMX8MN_SYS_PLL2_1000M>, 1171 <&clk IMX8MN_SYS_PLL1_800M>; 1172 assigned-clock-rates = <266000000>, 1173 <24000000>, 1174 <24000000>, 1175 <500000000>, 1176 <200000000>; 1177 #power-domain-cells = <1>; 1178 }; 1179 1180 mipi_csi: mipi-csi@32e30000 { 1181 compatible = "fsl,imx8mm-mipi-csi2"; 1182 reg = <0x32e30000 0x1000>; 1183 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1184 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>; 1185 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>; 1186 assigned-clock-rates = <333000000>; 1187 clock-frequency = <333000000>; 1188 clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1189 <&clk IMX8MN_CLK_CAMERA_PIXEL>, 1190 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1191 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1192 clock-names = "pclk", "wrap", "phy", "axi"; 1193 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>; 1194 status = "disabled"; 1195 1196 ports { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 1200 port@0 { 1201 reg = <0>; 1202 }; 1203 1204 port@1 { 1205 reg = <1>; 1206 1207 mipi_csi_out: endpoint { 1208 remote-endpoint = <&isi_in>; 1209 }; 1210 }; 1211 }; 1212 }; 1213 1214 usbotg1: usb@32e40000 { 1215 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1216 reg = <0x32e40000 0x200>; 1217 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1219 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1220 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1221 phys = <&usbphynop1>; 1222 fsl,usbmisc = <&usbmisc1 0>; 1223 power-domains = <&pgc_hsiomix>; 1224 status = "disabled"; 1225 }; 1226 1227 usbmisc1: usbmisc@32e40200 { 1228 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", 1229 "fsl,imx6q-usbmisc"; 1230 #index-cells = <1>; 1231 reg = <0x32e40200 0x200>; 1232 }; 1233 }; 1234 1235 dma_apbh: dma-controller@33000000 { 1236 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1237 reg = <0x33000000 0x2000>; 1238 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1242 #dma-cells = <1>; 1243 dma-channels = <4>; 1244 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1245 }; 1246 1247 gpmi: nand-controller@33002000 { 1248 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1252 reg-names = "gpmi-nand", "bch"; 1253 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "bch"; 1255 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1256 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1257 clock-names = "gpmi_io", "gpmi_bch_apb"; 1258 dmas = <&dma_apbh 0>; 1259 dma-names = "rx-tx"; 1260 status = "disabled"; 1261 }; 1262 1263 gpu: gpu@38000000 { 1264 compatible = "vivante,gc"; 1265 reg = <0x38000000 0x8000>; 1266 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&clk IMX8MN_CLK_GPU_AHB>, 1268 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 1269 <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 1270 <&clk IMX8MN_CLK_GPU_SHADER>; 1271 clock-names = "reg", "bus", "core", "shader"; 1272 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, 1273 <&clk IMX8MN_CLK_GPU_SHADER>, 1274 <&clk IMX8MN_CLK_GPU_AXI>, 1275 <&clk IMX8MN_CLK_GPU_AHB>, 1276 <&clk IMX8MN_GPU_PLL>; 1277 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, 1278 <&clk IMX8MN_GPU_PLL_OUT>, 1279 <&clk IMX8MN_SYS_PLL1_800M>, 1280 <&clk IMX8MN_SYS_PLL1_800M>; 1281 assigned-clock-rates = <400000000>, 1282 <400000000>, 1283 <800000000>, 1284 <400000000>, 1285 <1200000000>; 1286 power-domains = <&pgc_gpumix>; 1287 }; 1288 1289 gic: interrupt-controller@38800000 { 1290 compatible = "arm,gic-v3"; 1291 reg = <0x38800000 0x10000>, 1292 <0x38880000 0xc0000>; 1293 #interrupt-cells = <3>; 1294 interrupt-controller; 1295 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1296 }; 1297 1298 ddrc: memory-controller@3d400000 { 1299 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1300 reg = <0x3d400000 0x400000>; 1301 clock-names = "core", "pll", "alt", "apb"; 1302 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1303 <&clk IMX8MN_DRAM_PLL>, 1304 <&clk IMX8MN_CLK_DRAM_ALT>, 1305 <&clk IMX8MN_CLK_DRAM_APB>; 1306 }; 1307 1308 ddr-pmu@3d800000 { 1309 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1310 reg = <0x3d800000 0x400000>; 1311 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1312 }; 1313 }; 1314 1315 usbphynop1: usbphynop1 { 1316 #phy-cells = <0>; 1317 compatible = "usb-nop-xceiv"; 1318 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1319 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1320 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1321 clock-names = "main_clk"; 1322 power-domains = <&pgc_otg1>; 1323 }; 1324}; 1325