1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/net/ti-dp83867.h> 12 13#include "imx8mn.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7902 i.MX8MN board"; 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; 18 19 aliases { 20 rtc0 = &gsc_rtc; 21 rtc1 = &snvs_rtc; 22 usb0 = &usbotg1; 23 }; 24 25 chosen { 26 stdout-path = &uart2; 27 }; 28 29 memory@40000000 { 30 device_type = "memory"; 31 reg = <0x0 0x40000000 0 0x80000000>; 32 }; 33 34 can20m: can20m { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <20000000>; 38 clock-output-names = "can20m"; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 44 key-user-pb { 45 label = "user_pb"; 46 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 47 linux,code = <BTN_0>; 48 }; 49 50 key-user-pb1x { 51 label = "user_pb1x"; 52 linux,code = <BTN_1>; 53 interrupt-parent = <&gsc>; 54 interrupts = <0>; 55 }; 56 57 key-erased { 58 label = "key_erased"; 59 linux,code = <BTN_2>; 60 interrupt-parent = <&gsc>; 61 interrupts = <1>; 62 }; 63 64 key-eeprom-wp { 65 label = "eeprom_wp"; 66 linux,code = <BTN_3>; 67 interrupt-parent = <&gsc>; 68 interrupts = <2>; 69 }; 70 71 key-tamper { 72 label = "tamper"; 73 linux,code = <BTN_4>; 74 interrupt-parent = <&gsc>; 75 interrupts = <5>; 76 }; 77 78 switch-hold { 79 label = "switch_hold"; 80 linux,code = <BTN_5>; 81 interrupt-parent = <&gsc>; 82 interrupts = <7>; 83 }; 84 }; 85 86 led-controller { 87 compatible = "gpio-leds"; 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_gpio_leds>; 90 91 led-0 { 92 function = LED_FUNCTION_STATUS; 93 color = <LED_COLOR_ID_GREEN>; 94 label = "panel1"; 95 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 96 default-state = "off"; 97 }; 98 99 led-1 { 100 function = LED_FUNCTION_STATUS; 101 color = <LED_COLOR_ID_GREEN>; 102 label = "panel2"; 103 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 104 default-state = "off"; 105 }; 106 107 led-2 { 108 function = LED_FUNCTION_STATUS; 109 color = <LED_COLOR_ID_GREEN>; 110 label = "panel3"; 111 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 112 default-state = "off"; 113 }; 114 115 led-3 { 116 function = LED_FUNCTION_STATUS; 117 color = <LED_COLOR_ID_GREEN>; 118 label = "panel4"; 119 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 120 default-state = "off"; 121 }; 122 123 led-4 { 124 function = LED_FUNCTION_STATUS; 125 color = <LED_COLOR_ID_GREEN>; 126 label = "panel5"; 127 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 128 default-state = "off"; 129 }; 130 }; 131 132 pps { 133 compatible = "pps-gpio"; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_pps>; 136 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 137 status = "okay"; 138 }; 139 140 reg_3p3v: regulator-3p3v { 141 compatible = "regulator-fixed"; 142 regulator-name = "3P3V"; 143 regulator-min-microvolt = <3300000>; 144 regulator-max-microvolt = <3300000>; 145 regulator-always-on; 146 }; 147 148 reg_usb1_vbus: regulator-usb1 { 149 compatible = "regulator-fixed"; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_reg_usb1>; 152 regulator-name = "usb_usb1_vbus"; 153 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; 154 enable-active-high; 155 regulator-min-microvolt = <5000000>; 156 regulator-max-microvolt = <5000000>; 157 }; 158 159 reg_wifi: regulator-wifi { 160 compatible = "regulator-fixed"; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_reg_wl>; 163 regulator-name = "wifi"; 164 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 165 enable-active-high; 166 startup-delay-us = <100>; 167 regulator-min-microvolt = <3300000>; 168 regulator-max-microvolt = <3300000>; 169 }; 170}; 171 172&A53_0 { 173 cpu-supply = <&buck2>; 174}; 175 176&A53_1 { 177 cpu-supply = <&buck2>; 178}; 179 180&A53_2 { 181 cpu-supply = <&buck2>; 182}; 183 184&A53_3 { 185 cpu-supply = <&buck2>; 186}; 187 188&ddrc { 189 operating-points-v2 = <&ddrc_opp_table>; 190 191 ddrc_opp_table: opp-table { 192 compatible = "operating-points-v2"; 193 194 opp-25000000 { 195 opp-hz = /bits/ 64 <25000000>; 196 }; 197 198 opp-100000000 { 199 opp-hz = /bits/ 64 <100000000>; 200 }; 201 202 opp-750000000 { 203 opp-hz = /bits/ 64 <750000000>; 204 }; 205 }; 206}; 207 208&ecspi1 { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_spi1>; 211 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 212 status = "okay"; 213 214 can@0 { 215 compatible = "microchip,mcp2515"; 216 reg = <0>; 217 clocks = <&can20m>; 218 interrupt-parent = <&gpio2>; 219 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 220 spi-max-frequency = <10000000>; 221 }; 222}; 223 224&disp_blk_ctrl { 225 status = "disabled"; 226}; 227 228/* off-board header */ 229&ecspi2 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_spi2>; 232 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 233 status = "okay"; 234}; 235 236&fec1 { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_fec1>; 239 phy-mode = "rgmii-id"; 240 phy-handle = <ðphy0>; 241 local-mac-address = [00 00 00 00 00 00]; 242 status = "okay"; 243 244 mdio { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 248 ethphy0: ethernet-phy@0 { 249 compatible = "ethernet-phy-ieee802.3-c22"; 250 reg = <0>; 251 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 252 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 253 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 254 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 255 }; 256 }; 257}; 258 259&gpio1 { 260 gpio-line-names = "", "", "", "", "", "", "", "", 261 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", 262 "", "", "", "", "", "", "", "", 263 "", "", "", "", "", "", "", ""; 264}; 265 266&gpio2 { 267 gpio-line-names = "", "", "", "", "", "", "", "", 268 "uart2_en#", "", "", "", "", "", "", "", 269 "", "", "", "", "", "", "", "", 270 "", "", "", "", "", "", "", ""; 271}; 272 273&gpio3 { 274 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", 275 "", "", "", "", "", "", "", "", 276 "", "", "", "", "", "", "", "", 277 "", "", "", "", "", "", "", ""; 278}; 279 280&gpio4 { 281 gpio-line-names = "", "", "", "", "", "", "", "", 282 "", "", "", "", "", "", "", "", 283 "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", 284 "", "uart1_term", "uart1_half", "app_gpio2", 285 "mipi_gpio1", "", "", ""; 286}; 287 288&gpio5 { 289 gpio-line-names = "", "", "", "mipi_gpio4", 290 "mipi_gpio3", "mipi_gpio2", "", "", 291 "", "", "", "", "", "", "", "", 292 "", "", "", "", "", "", "", "", 293 "", "", "", "", "", "", "", ""; 294}; 295 296&gpu { 297 status = "disabled"; 298}; 299 300&i2c1 { 301 clock-frequency = <100000>; 302 pinctrl-names = "default", "gpio"; 303 pinctrl-0 = <&pinctrl_i2c1>; 304 pinctrl-1 = <&pinctrl_i2c1_gpio>; 305 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 306 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 307 status = "okay"; 308 309 gsc: gsc@20 { 310 compatible = "gw,gsc"; 311 reg = <0x20>; 312 pinctrl-0 = <&pinctrl_gsc>; 313 interrupt-parent = <&gpio2>; 314 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 315 interrupt-controller; 316 #interrupt-cells = <1>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 adc { 321 compatible = "gw,gsc-adc"; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 channel@6 { 326 gw,mode = <0>; 327 reg = <0x06>; 328 label = "temp"; 329 }; 330 331 channel@8 { 332 gw,mode = <3>; 333 reg = <0x08>; 334 label = "vdd_bat"; 335 }; 336 337 channel@82 { 338 gw,mode = <2>; 339 reg = <0x82>; 340 label = "vin"; 341 gw,voltage-divider-ohms = <22100 1000>; 342 gw,voltage-offset-microvolt = <700000>; 343 }; 344 345 channel@84 { 346 gw,mode = <2>; 347 reg = <0x84>; 348 label = "vin_4p0"; 349 gw,voltage-divider-ohms = <10000 10000>; 350 }; 351 352 channel@86 { 353 gw,mode = <2>; 354 reg = <0x86>; 355 label = "vdd_3p3"; 356 gw,voltage-divider-ohms = <10000 10000>; 357 }; 358 359 channel@88 { 360 gw,mode = <2>; 361 reg = <0x88>; 362 label = "vdd_0p9"; 363 }; 364 365 channel@8c { 366 gw,mode = <2>; 367 reg = <0x8c>; 368 label = "vdd_soc"; 369 }; 370 371 channel@8e { 372 gw,mode = <2>; 373 reg = <0x8e>; 374 label = "vdd_arm"; 375 }; 376 377 channel@90 { 378 gw,mode = <2>; 379 reg = <0x90>; 380 label = "vdd_1p8"; 381 }; 382 383 channel@92 { 384 gw,mode = <2>; 385 reg = <0x92>; 386 label = "vdd_dram"; 387 }; 388 389 channel@98 { 390 gw,mode = <2>; 391 reg = <0x98>; 392 label = "vdd_1p0"; 393 }; 394 395 channel@9a { 396 gw,mode = <2>; 397 reg = <0x9a>; 398 label = "vdd_2p5"; 399 gw,voltage-divider-ohms = <10000 10000>; 400 }; 401 402 channel@9c { 403 gw,mode = <2>; 404 reg = <0x9c>; 405 label = "vdd_5p0"; 406 gw,voltage-divider-ohms = <10000 10000>; 407 }; 408 409 channel@a2 { 410 gw,mode = <2>; 411 reg = <0xa2>; 412 label = "vdd_gsc"; 413 gw,voltage-divider-ohms = <10000 10000>; 414 }; 415 }; 416 }; 417 418 gpio: gpio@23 { 419 compatible = "nxp,pca9555"; 420 reg = <0x23>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupt-parent = <&gsc>; 424 interrupts = <4>; 425 }; 426 427 pmic@4b { 428 compatible = "rohm,bd71847"; 429 reg = <0x4b>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_pmic>; 432 interrupt-parent = <&gpio3>; 433 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 434 rohm,reset-snvs-powered; 435 #clock-cells = <0>; 436 clocks = <&osc_32k>; 437 clock-output-names = "clk-32k-out"; 438 439 regulators { 440 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 441 BUCK1 { 442 regulator-name = "buck1"; 443 regulator-min-microvolt = <700000>; 444 regulator-max-microvolt = <1300000>; 445 regulator-boot-on; 446 regulator-always-on; 447 regulator-ramp-delay = <1250>; 448 }; 449 450 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 451 buck2: BUCK2 { 452 regulator-name = "buck2"; 453 regulator-min-microvolt = <700000>; 454 regulator-max-microvolt = <1300000>; 455 regulator-boot-on; 456 regulator-always-on; 457 regulator-ramp-delay = <1250>; 458 rohm,dvs-run-voltage = <1000000>; 459 rohm,dvs-idle-voltage = <900000>; 460 }; 461 462 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 463 BUCK3 { 464 regulator-name = "buck3"; 465 regulator-min-microvolt = <700000>; 466 regulator-max-microvolt = <1350000>; 467 regulator-boot-on; 468 regulator-always-on; 469 }; 470 471 /* vdd_3p3 */ 472 BUCK4 { 473 regulator-name = "buck4"; 474 regulator-min-microvolt = <3000000>; 475 regulator-max-microvolt = <3300000>; 476 regulator-boot-on; 477 regulator-always-on; 478 }; 479 480 /* vdd_1p8 */ 481 BUCK5 { 482 regulator-name = "buck5"; 483 regulator-min-microvolt = <1605000>; 484 regulator-max-microvolt = <1995000>; 485 regulator-boot-on; 486 regulator-always-on; 487 }; 488 489 /* vdd_dram */ 490 BUCK6 { 491 regulator-name = "buck6"; 492 regulator-min-microvolt = <800000>; 493 regulator-max-microvolt = <1400000>; 494 regulator-boot-on; 495 regulator-always-on; 496 }; 497 498 /* nvcc_snvs_1p8 */ 499 LDO1 { 500 regulator-name = "ldo1"; 501 regulator-min-microvolt = <1600000>; 502 regulator-max-microvolt = <1900000>; 503 regulator-boot-on; 504 regulator-always-on; 505 }; 506 507 /* vdd_snvs_0p8 */ 508 LDO2 { 509 regulator-name = "ldo2"; 510 regulator-min-microvolt = <800000>; 511 regulator-max-microvolt = <900000>; 512 regulator-boot-on; 513 regulator-always-on; 514 }; 515 516 /* vdda_1p8 */ 517 LDO3 { 518 regulator-name = "ldo3"; 519 regulator-min-microvolt = <1800000>; 520 regulator-max-microvolt = <3300000>; 521 regulator-boot-on; 522 regulator-always-on; 523 }; 524 525 LDO4 { 526 regulator-name = "ldo4"; 527 regulator-min-microvolt = <900000>; 528 regulator-max-microvolt = <1800000>; 529 regulator-boot-on; 530 regulator-always-on; 531 }; 532 533 LDO6 { 534 regulator-name = "ldo6"; 535 regulator-min-microvolt = <900000>; 536 regulator-max-microvolt = <1800000>; 537 regulator-boot-on; 538 regulator-always-on; 539 }; 540 }; 541 }; 542 543 eeprom@50 { 544 compatible = "atmel,24c02"; 545 reg = <0x50>; 546 pagesize = <16>; 547 }; 548 549 eeprom@51 { 550 compatible = "atmel,24c02"; 551 reg = <0x51>; 552 pagesize = <16>; 553 }; 554 555 eeprom@52 { 556 compatible = "atmel,24c02"; 557 reg = <0x52>; 558 pagesize = <16>; 559 }; 560 561 eeprom@53 { 562 compatible = "atmel,24c02"; 563 reg = <0x53>; 564 pagesize = <16>; 565 }; 566 567 gsc_rtc: rtc@68 { 568 compatible = "dallas,ds1672"; 569 reg = <0x68>; 570 }; 571}; 572 573&i2c2 { 574 clock-frequency = <400000>; 575 pinctrl-names = "default", "gpio"; 576 pinctrl-0 = <&pinctrl_i2c2>; 577 pinctrl-1 = <&pinctrl_i2c2_gpio>; 578 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 579 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 580 status = "okay"; 581 582 accelerometer@19 { 583 compatible = "st,lis2de12"; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_accel>; 586 reg = <0x19>; 587 st,drdy-int-pin = <1>; 588 interrupt-parent = <&gpio1>; 589 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 590 }; 591}; 592 593/* off-board header */ 594&i2c3 { 595 clock-frequency = <400000>; 596 pinctrl-names = "default", "gpio"; 597 pinctrl-0 = <&pinctrl_i2c3>; 598 pinctrl-1 = <&pinctrl_i2c3_gpio>; 599 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 600 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 601 status = "okay"; 602}; 603 604/* off-board header */ 605&i2c4 { 606 clock-frequency = <400000>; 607 pinctrl-names = "default", "gpio"; 608 pinctrl-0 = <&pinctrl_i2c4>; 609 pinctrl-1 = <&pinctrl_i2c4_gpio>; 610 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 611 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 612 status = "okay"; 613}; 614 615&pgc_gpumix { 616 status = "disabled"; 617}; 618 619/* off-board header */ 620&sai3 { 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_sai3>; 623 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 624 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 625 assigned-clock-rates = <24576000>; 626 status = "okay"; 627}; 628 629/* RS232/RS485/RS422 selectable */ 630&uart1 { 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 633 status = "okay"; 634}; 635 636/* RS232 console */ 637&uart2 { 638 pinctrl-names = "default"; 639 pinctrl-0 = <&pinctrl_uart2>; 640 status = "okay"; 641}; 642 643/* bluetooth HCI */ 644&uart3 { 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 647 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 648 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 649 status = "okay"; 650 651 bluetooth { 652 compatible = "brcm,bcm4330-bt"; 653 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 654 }; 655}; 656 657/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ 658&uart4 { 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pinctrl_uart4>; 661 status = "okay"; 662}; 663 664&usbotg1 { 665 dr_mode = "host"; 666 vbus-supply = <®_usb1_vbus>; 667 disable-over-current; 668 status = "okay"; 669}; 670 671/* SDIO WiFi */ 672&usdhc2 { 673 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 674 pinctrl-0 = <&pinctrl_usdhc2>; 675 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 676 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 677 bus-width = <4>; 678 non-removable; 679 vmmc-supply = <®_wifi>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "okay"; 683 684 wifi@0 { 685 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 686 reg = <0>; 687 }; 688}; 689 690/* eMMC */ 691&usdhc3 { 692 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 693 pinctrl-0 = <&pinctrl_usdhc3>; 694 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 695 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 696 bus-width = <8>; 697 non-removable; 698 status = "okay"; 699}; 700 701&wdog1 { 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pinctrl_wdog>; 704 fsl,ext-reset-output; 705 status = "okay"; 706}; 707 708&iomuxc { 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pinctrl_hog>; 711 712 pinctrl_hog: hoggrp { 713 fsl,pins = < 714 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 715 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ 716 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ 717 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 718 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 719 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ 720 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ 721 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ 722 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ 723 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ 724 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ 725 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ 726 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ 727 >; 728 }; 729 730 pinctrl_accel: accelgrp { 731 fsl,pins = < 732 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 733 >; 734 }; 735 736 pinctrl_fec1: fec1grp { 737 fsl,pins = < 738 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 739 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 740 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 741 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 742 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 743 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 744 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 745 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 746 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 747 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 748 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 749 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 750 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 751 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 752 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ 753 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ 754 >; 755 }; 756 757 pinctrl_gsc: gscgrp { 758 fsl,pins = < 759 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 760 >; 761 }; 762 763 pinctrl_i2c1: i2c1grp { 764 fsl,pins = < 765 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 766 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 767 >; 768 }; 769 770 pinctrl_i2c1_gpio: i2c1gpiogrp { 771 fsl,pins = < 772 MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 773 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 774 >; 775 }; 776 777 pinctrl_i2c2: i2c2grp { 778 fsl,pins = < 779 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 780 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 781 >; 782 }; 783 784 pinctrl_i2c2_gpio: i2c2gpiogrp { 785 fsl,pins = < 786 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 787 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 788 >; 789 }; 790 791 pinctrl_i2c3: i2c3grp { 792 fsl,pins = < 793 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 794 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 795 >; 796 }; 797 798 pinctrl_i2c3_gpio: i2c3gpiogrp { 799 fsl,pins = < 800 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 801 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 802 >; 803 }; 804 805 pinctrl_i2c4: i2c4grp { 806 fsl,pins = < 807 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 808 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 809 >; 810 }; 811 812 pinctrl_i2c4_gpio: i2c4gpiogrp { 813 fsl,pins = < 814 MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 815 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 816 >; 817 }; 818 819 pinctrl_gpio_leds: gpioledgrp { 820 fsl,pins = < 821 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 822 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 823 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 824 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 825 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 826 >; 827 }; 828 829 pinctrl_pmic: pmicgrp { 830 fsl,pins = < 831 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 832 >; 833 }; 834 835 pinctrl_pps: ppsgrp { 836 fsl,pins = < 837 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ 838 >; 839 }; 840 841 pinctrl_reg_wl: regwlgrp { 842 fsl,pins = < 843 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ 844 >; 845 }; 846 847 pinctrl_reg_usb1: regusb1grp { 848 fsl,pins = < 849 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 850 >; 851 }; 852 853 pinctrl_sai3: sai3grp { 854 fsl,pins = < 855 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 856 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 857 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 858 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 859 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 860 >; 861 }; 862 863 pinctrl_spi1: spi1grp { 864 fsl,pins = < 865 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 866 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 867 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 868 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 869 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ 870 >; 871 }; 872 873 pinctrl_spi2: spi2grp { 874 fsl,pins = < 875 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 876 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 877 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 878 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ 879 >; 880 }; 881 882 pinctrl_uart1: uart1grp { 883 fsl,pins = < 884 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 885 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 886 >; 887 }; 888 889 pinctrl_uart1_gpio: uart1gpiogrp { 890 fsl,pins = < 891 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ 892 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ 893 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ 894 >; 895 }; 896 897 pinctrl_uart2: uart2grp { 898 fsl,pins = < 899 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 900 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 901 >; 902 }; 903 904 pinctrl_uart3_gpio: uart3_gpiogrp { 905 fsl,pins = < 906 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ 907 >; 908 }; 909 910 pinctrl_uart3: uart3grp { 911 fsl,pins = < 912 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 913 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 914 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ 915 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ 916 >; 917 }; 918 919 pinctrl_uart4: uart4grp { 920 fsl,pins = < 921 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 922 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 923 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ 924 >; 925 }; 926 927 pinctrl_usdhc2: usdhc2grp { 928 fsl,pins = < 929 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 930 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 931 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 932 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 933 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 934 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 935 >; 936 }; 937 938 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 939 fsl,pins = < 940 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 941 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 942 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 943 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 944 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 945 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 946 >; 947 }; 948 949 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 950 fsl,pins = < 951 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 952 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 953 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 954 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 955 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 956 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 957 >; 958 }; 959 960 pinctrl_usdhc3: usdhc3grp { 961 fsl,pins = < 962 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 963 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 964 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 965 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 966 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 967 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 968 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 969 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 970 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 971 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 972 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 973 >; 974 }; 975 976 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 977 fsl,pins = < 978 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 979 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 980 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 981 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 982 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 983 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 984 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 985 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 986 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 987 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 988 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 989 >; 990 }; 991 992 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 993 fsl,pins = < 994 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 995 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 996 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 997 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 998 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 999 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1000 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1001 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1002 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1003 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1004 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1005 >; 1006 }; 1007 1008 pinctrl_wdog: wdoggrp { 1009 fsl,pins = < 1010 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1011 >; 1012 }; 1013}; 1014