1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright 2020-2021 TQ-Systems GmbH 4 */ 5 6#include "imx8mn.dtsi" 7 8/ { 9 model = "TQ-Systems i.MX8MN TQMa8MxNL"; 10 compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; 11 12 memory@40000000 { 13 device_type = "memory"; 14 /* our minimum RAM config will be 1024 MiB */ 15 reg = <0x00000000 0x40000000 0 0x40000000>; 16 }; 17 18 /* e-MMC IO, needed for HS modes */ 19 reg_vcc1v8: regulator-vcc1v8 { 20 compatible = "regulator-fixed"; 21 regulator-name = "TQMA8MXNL_VCC1V8"; 22 regulator-min-microvolt = <1800000>; 23 regulator-max-microvolt = <1800000>; 24 }; 25 26 reg_vcc3v3: regulator-vcc3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "TQMA8MXNL_VCC3V3"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 }; 32 33 reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 /* global autoconfigured region for contiguous allocations */ 39 linux,cma { 40 compatible = "shared-dma-pool"; 41 reusable; 42 /* 640 MiB */ 43 size = <0 0x28000000>; 44 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ 45 alloc-ranges = <0 0x40000000 0 0x78000000>; 46 linux,cma-default; 47 }; 48 }; 49}; 50 51&A53_0 { 52 cpu-supply = <&buck2_reg>; 53}; 54 55&flexspi { 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_flexspi>; 58 status = "okay"; 59 60 flash0: flash@0 { 61 compatible = "jedec,spi-nor"; 62 reg = <0>; 63 spi-max-frequency = <84000000>; 64 spi-tx-bus-width = <1>; 65 spi-rx-bus-width = <4>; 66 67 partitions { 68 compatible = "fixed-partitions"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 }; 72 }; 73}; 74 75&i2c1 { 76 clock-frequency = <100000>; 77 pinctrl-names = "default", "gpio"; 78 pinctrl-0 = <&pinctrl_i2c1>; 79 pinctrl-1 = <&pinctrl_i2c1_gpio>; 80 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 81 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 82 status = "okay"; 83 84 sensor0: temperature-sensor@1b { 85 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 86 reg = <0x1b>; 87 }; 88 89 pca9450: pmic@25 { 90 compatible = "nxp,pca9450a"; 91 reg = <0x25>; 92 93 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 94 pinctrl-0 = <&pinctrl_pmic>; 95 pinctrl-names = "default"; 96 interrupt-parent = <&gpio1>; 97 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 98 99 regulators { 100 /* V_0V85_SOC: 0.85 .. 0.95 */ 101 buck1_reg: BUCK1 { 102 regulator-name = "BUCK1"; 103 regulator-min-microvolt = <850000>; 104 regulator-max-microvolt = <950000>; 105 regulator-boot-on; 106 regulator-always-on; 107 regulator-ramp-delay = <3125>; 108 }; 109 110 /* VDD_ARM */ 111 buck2_reg: BUCK2 { 112 regulator-name = "BUCK2"; 113 regulator-min-microvolt = <850000>; 114 regulator-max-microvolt = <1000000>; 115 regulator-boot-on; 116 regulator-always-on; 117 nxp,dvs-run-voltage = <950000>; 118 nxp,dvs-standby-voltage = <850000>; 119 regulator-ramp-delay = <3125>; 120 }; 121 122 /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ 123 buck3_reg: BUCK3 { 124 regulator-name = "BUCK3"; 125 regulator-min-microvolt = <850000>; 126 regulator-max-microvolt = <950000>; 127 regulator-boot-on; 128 regulator-always-on; 129 regulator-ramp-delay = <3125>; 130 }; 131 132 /* VCC3V3 -> VMMC, ... must not be changed */ 133 buck4_reg: BUCK4 { 134 regulator-name = "BUCK4"; 135 regulator-min-microvolt = <3300000>; 136 regulator-max-microvolt = <3300000>; 137 regulator-boot-on; 138 regulator-always-on; 139 }; 140 141 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 142 buck5_reg: BUCK5 { 143 regulator-name = "BUCK5"; 144 regulator-min-microvolt = <1800000>; 145 regulator-max-microvolt = <1800000>; 146 regulator-boot-on; 147 regulator-always-on; 148 }; 149 150 /* V_1V1 -> RAM, ... must not be changed */ 151 buck6_reg: BUCK6 { 152 regulator-name = "BUCK6"; 153 regulator-min-microvolt = <1100000>; 154 regulator-max-microvolt = <1100000>; 155 regulator-boot-on; 156 regulator-always-on; 157 }; 158 159 /* V_1V8_SNVS */ 160 ldo1_reg: LDO1 { 161 regulator-name = "LDO1"; 162 regulator-min-microvolt = <1800000>; 163 regulator-max-microvolt = <1800000>; 164 regulator-boot-on; 165 regulator-always-on; 166 }; 167 168 /* V_0V8_SNVS */ 169 ldo2_reg: LDO2 { 170 regulator-name = "LDO2"; 171 regulator-min-microvolt = <800000>; 172 regulator-max-microvolt = <850000>; 173 regulator-boot-on; 174 regulator-always-on; 175 }; 176 177 /* V_1V8_ANA */ 178 ldo3_reg: LDO3 { 179 regulator-name = "LDO3"; 180 regulator-min-microvolt = <1800000>; 181 regulator-max-microvolt = <1800000>; 182 regulator-boot-on; 183 regulator-always-on; 184 }; 185 186 /* V_0V9_MIPI */ 187 ldo4_reg: LDO4 { 188 regulator-name = "LDO4"; 189 regulator-min-microvolt = <900000>; 190 regulator-max-microvolt = <900000>; 191 regulator-boot-on; 192 regulator-always-on; 193 }; 194 195 /* VCC SD IO - switched using SD2 VSELECT */ 196 ldo5_reg: LDO5 { 197 regulator-name = "LDO5"; 198 regulator-min-microvolt = <1800000>; 199 regulator-max-microvolt = <3300000>; 200 }; 201 }; 202 }; 203 204 pcf85063: rtc@51 { 205 compatible = "nxp,pcf85063a"; 206 reg = <0x51>; 207 quartz-load-femtofarads = <7000>; 208 }; 209 210 eeprom1: eeprom@53 { 211 compatible = "nxp,se97b", "atmel,24c02"; 212 read-only; 213 reg = <0x53>; 214 pagesize = <16>; 215 vcc-supply = <®_vcc3v3>; 216 }; 217 218 eeprom0: eeprom@57 { 219 compatible = "atmel,24c64"; 220 reg = <0x57>; 221 pagesize = <32>; 222 vcc-supply = <®_vcc3v3>; 223 }; 224}; 225 226&mipi_dsi { 227 vddcore-supply = <&ldo4_reg>; 228 vddio-supply = <&ldo3_reg>; 229}; 230 231&usdhc3 { 232 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 233 pinctrl-0 = <&pinctrl_usdhc3>; 234 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 235 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 236 bus-width = <8>; 237 non-removable; 238 no-sd; 239 no-sdio; 240 vmmc-supply = <®_vcc3v3>; 241 vqmmc-supply = <®_vcc1v8>; 242 status = "okay"; 243}; 244 245/* 246 * Attention: 247 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR 248 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. 249 */ 250&wdog1 { 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_wdog>; 253 fsl,ext-reset-output; 254 status = "okay"; 255}; 256 257&iomuxc { 258 pinctrl_flexspi: flexspigrp { 259 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>, 260 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>, 261 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>, 262 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>, 263 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>, 264 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>; 265 }; 266 267 pinctrl_i2c1: i2c1grp { 268 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>, 269 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>; 270 }; 271 272 pinctrl_i2c1_gpio: i2c1gpiogrp { 273 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>, 274 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>; 275 }; 276 277 pinctrl_pmic: pmicgrp { 278 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; 279 }; 280 281 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 282 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; 283 }; 284 285 pinctrl_usdhc3: usdhc3grp { 286 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, 287 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 288 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 289 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 290 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 291 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 292 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 293 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 294 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 295 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 296 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 297 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 298 }; 299 300 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 301 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, 302 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 303 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 304 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 305 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 306 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 307 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 308 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 309 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 310 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 311 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 312 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 313 }; 314 315 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 316 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, 317 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 318 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 319 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 320 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 321 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 322 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 323 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 324 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 325 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 326 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 327 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 328 }; 329 330 pinctrl_wdog: wdoggrp { 331 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; 332 }; 333}; 334