xref: /linux/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi (revision 184e56e77c06a7eef68a021e9d4b11a11a8ab096) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6#include "imx8mn.dtsi"
7
8/ {
9	model = "TQ-Systems i.MX8MN TQMa8MxNL";
10	compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
11
12	memory@40000000 {
13		device_type = "memory";
14		/*  our minimum RAM config will be 1024 MiB */
15		reg = <0x00000000 0x40000000 0 0x40000000>;
16	};
17
18	/* e-MMC IO, needed for HS modes */
19	reg_vcc1v8: regulator-vcc1v8 {
20		compatible = "regulator-fixed";
21		regulator-name = "TQMA8MXNL_VCC1V8";
22		regulator-min-microvolt = <1800000>;
23		regulator-max-microvolt = <1800000>;
24	};
25
26	reg_vcc3v3: regulator-vcc3v3 {
27		compatible = "regulator-fixed";
28		regulator-name = "TQMA8MXNL_VCC3V3";
29		regulator-min-microvolt = <3300000>;
30		regulator-max-microvolt = <3300000>;
31	};
32
33	reserved-memory {
34		#address-cells = <2>;
35		#size-cells = <2>;
36		ranges;
37
38		/* global autoconfigured region for contiguous allocations */
39		linux,cma {
40			compatible = "shared-dma-pool";
41			reusable;
42			/* 640 MiB */
43			size = <0 0x28000000>;
44			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
45			alloc-ranges = <0 0x40000000 0 0x78000000>;
46			linux,cma-default;
47		};
48	};
49};
50
51&A53_0 {
52	cpu-supply = <&buck2_reg>;
53};
54
55&flexspi {
56	pinctrl-names = "default";
57	pinctrl-0 = <&pinctrl_flexspi>;
58	status = "okay";
59
60	flash0: flash@0 {
61		compatible = "jedec,spi-nor";
62		reg = <0>;
63		spi-max-frequency = <84000000>;
64		spi-tx-bus-width = <1>;
65		spi-rx-bus-width = <4>;
66		vcc-supply = <&buck5_reg>;
67
68		partitions {
69			compatible = "fixed-partitions";
70			#address-cells = <1>;
71			#size-cells = <1>;
72		};
73	};
74};
75
76&i2c1 {
77	clock-frequency = <100000>;
78	pinctrl-names = "default", "gpio";
79	pinctrl-0 = <&pinctrl_i2c1>;
80	pinctrl-1 = <&pinctrl_i2c1_gpio>;
81	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
82	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
83	status = "okay";
84
85	sensor0: temperature-sensor@1b {
86		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
87		reg = <0x1b>;
88	};
89
90	pca9450: pmic@25 {
91		compatible = "nxp,pca9450a";
92		reg = <0x25>;
93
94		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
95		pinctrl-0 = <&pinctrl_pmic>;
96		pinctrl-names = "default";
97		interrupt-parent = <&gpio1>;
98		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
99
100		regulators {
101			/* V_0V85_SOC: 0.85 .. 0.95 */
102			buck1_reg: BUCK1 {
103				regulator-name = "BUCK1";
104				regulator-min-microvolt = <850000>;
105				regulator-max-microvolt = <950000>;
106				regulator-boot-on;
107				regulator-always-on;
108				regulator-ramp-delay = <3125>;
109			};
110
111			/* VDD_ARM */
112			buck2_reg: BUCK2 {
113				regulator-name = "BUCK2";
114				regulator-min-microvolt = <850000>;
115				regulator-max-microvolt = <1000000>;
116				regulator-boot-on;
117				regulator-always-on;
118				nxp,dvs-run-voltage = <950000>;
119				nxp,dvs-standby-voltage = <850000>;
120				regulator-ramp-delay = <3125>;
121			};
122
123			/* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */
124			buck3_reg: BUCK3 {
125				regulator-name = "BUCK3";
126				regulator-min-microvolt = <850000>;
127				regulator-max-microvolt = <950000>;
128				regulator-boot-on;
129				regulator-always-on;
130				regulator-ramp-delay = <3125>;
131			};
132
133			/* VCC3V3 -> VMMC, ... must not be changed */
134			buck4_reg: BUCK4 {
135				regulator-name = "BUCK4";
136				regulator-min-microvolt = <3300000>;
137				regulator-max-microvolt = <3300000>;
138				regulator-boot-on;
139				regulator-always-on;
140			};
141
142			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
143			buck5_reg: BUCK5 {
144				regulator-name = "BUCK5";
145				regulator-min-microvolt = <1800000>;
146				regulator-max-microvolt = <1800000>;
147				regulator-boot-on;
148				regulator-always-on;
149			};
150
151			/* V_1V1 -> RAM, ... must not be changed */
152			buck6_reg: BUCK6 {
153				regulator-name = "BUCK6";
154				regulator-min-microvolt = <1100000>;
155				regulator-max-microvolt = <1100000>;
156				regulator-boot-on;
157				regulator-always-on;
158			};
159
160			/* V_1V8_SNVS */
161			ldo1_reg: LDO1 {
162				regulator-name = "LDO1";
163				regulator-min-microvolt = <1800000>;
164				regulator-max-microvolt = <1800000>;
165				regulator-boot-on;
166				regulator-always-on;
167			};
168
169			/* V_0V8_SNVS */
170			ldo2_reg: LDO2 {
171				regulator-name = "LDO2";
172				regulator-min-microvolt = <800000>;
173				regulator-max-microvolt = <850000>;
174				regulator-boot-on;
175				regulator-always-on;
176			};
177
178			/* V_1V8_ANA */
179			ldo3_reg: LDO3 {
180				regulator-name = "LDO3";
181				regulator-min-microvolt = <1800000>;
182				regulator-max-microvolt = <1800000>;
183				regulator-boot-on;
184				regulator-always-on;
185			};
186
187			/* V_0V9_MIPI */
188			ldo4_reg: LDO4 {
189				regulator-name = "LDO4";
190				regulator-min-microvolt = <900000>;
191				regulator-max-microvolt = <900000>;
192				regulator-boot-on;
193				regulator-always-on;
194			};
195
196			/* VCC SD IO - switched using SD2 VSELECT */
197			ldo5_reg: LDO5 {
198				regulator-name = "LDO5";
199				regulator-min-microvolt = <1800000>;
200				regulator-max-microvolt = <3300000>;
201			};
202		};
203	};
204
205	pcf85063: rtc@51 {
206		compatible = "nxp,pcf85063a";
207		reg = <0x51>;
208		quartz-load-femtofarads = <7000>;
209	};
210
211	eeprom1: eeprom@53 {
212		compatible = "nxp,se97b", "atmel,24c02";
213		read-only;
214		reg = <0x53>;
215		pagesize = <16>;
216		vcc-supply = <&reg_vcc3v3>;
217	};
218
219	eeprom0: eeprom@57 {
220		compatible = "atmel,24c64";
221		reg = <0x57>;
222		pagesize = <32>;
223		vcc-supply = <&reg_vcc3v3>;
224	};
225};
226
227&mipi_dsi {
228	vddcore-supply = <&ldo4_reg>;
229	vddio-supply = <&ldo3_reg>;
230};
231
232&usdhc3 {
233	pinctrl-names = "default", "state_100mhz", "state_200mhz";
234	pinctrl-0 = <&pinctrl_usdhc3>;
235	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
236	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
237	bus-width = <8>;
238	non-removable;
239	no-sd;
240	no-sdio;
241	vmmc-supply = <&reg_vcc3v3>;
242	vqmmc-supply = <&reg_vcc1v8>;
243	status = "okay";
244};
245
246/*
247 * Attention:
248 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
249 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
250 */
251&wdog1 {
252	pinctrl-names = "default";
253	pinctrl-0 = <&pinctrl_wdog>;
254	fsl,ext-reset-output;
255	status = "okay";
256};
257
258&iomuxc {
259	pinctrl_flexspi: flexspigrp {
260		fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x84>,
261			   <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x84>,
262			   <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x84>,
263			   <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x84>,
264			   <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x84>,
265			   <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x84>;
266	};
267
268	pinctrl_i2c1: i2c1grp {
269		fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c4>,
270			   <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c4>;
271	};
272
273	pinctrl_i2c1_gpio: i2c1gpiogrp {
274		fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14	0x400001c4>,
275			   <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15	0x400001c4>;
276	};
277
278	pinctrl_pmic: pmicgrp {
279		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x84>;
280	};
281
282	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
283		fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x84>;
284	};
285
286	pinctrl_usdhc3: usdhc3grp {
287		fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d4>,
288			   <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2>,
289			   <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4>,
290			   <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4>,
291			   <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4>,
292			   <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4>,
293			   <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4>,
294			   <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4>,
295			   <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4>,
296			   <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4>,
297			   <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84>,
298			   <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x84>;
299	};
300
301	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
302		fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d2>,
303			   <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2>,
304			   <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4>,
305			   <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4>,
306			   <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4>,
307			   <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4>,
308			   <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4>,
309			   <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4>,
310			   <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4>,
311			   <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4>,
312			   <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84>,
313			   <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x84>;
314	};
315
316	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
317		fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x1d6>,
318			   <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d2>,
319			   <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4>,
320			   <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4>,
321			   <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4>,
322			   <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4>,
323			   <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4>,
324			   <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4>,
325			   <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4>,
326			   <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4>,
327			   <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x84>,
328			   <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B	0x84>;
329	};
330
331	pinctrl_wdog: wdoggrp {
332		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x84>;
333	};
334};
335