xref: /linux/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts (revision 2b0cfa6e49566c8fa6759734cf821aa6e8271a9e) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mn-tqma8mqnl.dtsi"
9#include "mba8mx.dtsi"
10
11/ {
12	model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
13	compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
14	chassis-type = "embedded";
15
16	aliases {
17		eeprom0 = &eeprom3;
18		mmc0 = &usdhc3;
19		mmc1 = &usdhc2;
20		mmc2 = &usdhc1;
21		rtc0 = &pcf85063;
22		rtc1 = &snvs_rtc;
23	};
24
25	reg_usdhc2_vmmc: regulator-vmmc {
26		compatible = "regulator-fixed";
27		pinctrl-names = "default";
28		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
29		regulator-name = "VSD_3V3";
30		regulator-min-microvolt = <3300000>;
31		regulator-max-microvolt = <3300000>;
32		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
33		enable-active-high;
34		startup-delay-us = <100>;
35		off-on-delay-us = <12000>;
36	};
37};
38
39/* Located on TQMa8MxML-ADAP */
40&gpio2 {
41	pinctrl-names = "default";
42	pinctrl-0 = <&pinctrl_usb0hub_sel>;
43
44	sel-usb-hub-hog {
45		gpio-hog;
46		gpios = <1 GPIO_ACTIVE_HIGH>;
47		output-high;
48	};
49};
50
51&i2c1 {
52	expander2: gpio@27 {
53		compatible = "nxp,pca9555";
54		reg = <0x27>;
55		gpio-controller;
56		#gpio-cells = <2>;
57		vcc-supply = <&reg_vcc_3v3>;
58		pinctrl-names = "default";
59		pinctrl-0 = <&pinctrl_expander2>;
60		interrupt-parent = <&gpio1>;
61		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
62		interrupt-controller;
63		#interrupt-cells = <2>;
64	};
65};
66
67&sai3 {
68	assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
69	assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
70	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
71	clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,
72		 <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
73		 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
74		 <&clk IMX8MN_AUDIO_PLL2_OUT>;
75};
76
77&tlv320aic3x04 {
78	clock-names = "mclk";
79	clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
80};
81
82&usbotg1 {
83	dr_mode = "host";
84	disable-over-current;
85	power-active-high;
86	status = "okay";
87};
88
89&iomuxc {
90	pinctrl_ecspi1: ecspi1grp {
91		fsl,pins = <MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000146>,
92			   <MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000146>,
93			   <MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000146>,
94			   <MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000146>;
95	};
96
97	pinctrl_ecspi2: ecspi2grp {
98		fsl,pins = <MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000146>,
99			   <MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000146>,
100			   <MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000146>,
101			   <MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000146>;
102	};
103
104	pinctrl_expander2: expander2grp {
105		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94>;
106	};
107
108	pinctrl_fec1: fec1grp {
109		fsl,pins = <MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002>,
110			   <MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002>,
111			   <MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14>,
112			   <MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14>,
113			   <MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14>,
114			   <MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14>,
115			   <MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90>,
116			   <MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90>,
117			   <MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90>,
118			   <MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90>,
119			   <MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14>,
120			   <MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90>,
121			   <MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90>,
122			   <MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14>;
123	};
124
125	pinctrl_gpiobutton: gpiobuttongrp {
126		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84>,
127			   <MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84>,
128			   <MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0		0x84>;
129	};
130
131	pinctrl_gpioled: gpioledgrp {
132		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84>,
133			   <MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14		0x84>;
134	};
135
136	pinctrl_i2c2: i2c2grp {
137		fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001C4>,
138			   <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001C4>;
139	};
140
141	pinctrl_i2c2_gpio: i2c2gpiogrp {
142		fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16		0x400001C4>,
143			   <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17		0x400001C4>;
144	};
145
146	pinctrl_i2c3: i2c3grp {
147		fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001C4>,
148			   <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001C4>;
149	};
150
151	pinctrl_i2c3_gpio: i2c3gpiogrp {
152		fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18		0x400001C4>,
153			   <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19		0x400001C4>;
154	};
155
156	pinctrl_pwm3: pwm3grp {
157		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14>;
158	};
159
160	pinctrl_pwm4: pwm4grp {
161		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14>;
162	};
163
164	pinctrl_sai3: sai3grp {
165		fsl,pins = <MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94>,
166			   <MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94>,
167			   <MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94>,
168			   <MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94>,
169			   <MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94>,
170			   <MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94>,
171			   <MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94>;
172	};
173
174	pinctrl_uart1: uart1grp {
175		fsl,pins = <MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16>,
176			   <MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16>;
177	};
178
179	pinctrl_uart2: uart2grp {
180		fsl,pins = <MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16>,
181			   <MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16>;
182	};
183
184	pinctrl_uart3: uart3grp {
185		fsl,pins = <MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16>,
186			   <MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16>;
187	};
188
189	pinctrl_uart4: uart4grp {
190		fsl,pins = <MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16>,
191			   <MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16>;
192	};
193
194	pinctrl_usb0hub_sel: usb0hub-selgrp {
195		/* SEL_USB_HUB_B */
196		fsl,pins = <MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1		0x84>;
197	};
198
199	pinctrl_usbotg: usbotggrp {
200		fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84>,
201			   <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84>,
202			   <MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID		0x1C4>;
203	};
204
205	pinctrl_usdhc2: usdhc2grp {
206		fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
207			   <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
208			   <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
209			   <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
210			   <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
211			   <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
212			   <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
213	};
214
215	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
216		fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
217			   <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
218			   <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
219			   <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
220			   <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
221			   <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
222			   <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
223	};
224
225	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
226		fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
227			   <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
228			   <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
229			   <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
230			   <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
231			   <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
232			   <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
233	};
234
235	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
236		fsl,pins = <MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84>;
237	};
238};
239