1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/usb/pd.h> 7#include "imx8mn.dtsi" 8 9/ { 10 chosen { 11 stdout-path = &uart2; 12 }; 13 14 gpio-leds { 15 compatible = "gpio-leds"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_led>; 18 19 status { 20 label = "yellow:status"; 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 22 default-state = "on"; 23 }; 24 }; 25 26 hdmi-connector { 27 compatible = "hdmi-connector"; 28 label = "hdmi"; 29 type = "a"; 30 31 port { 32 hdmi_connector_in: endpoint { 33 remote-endpoint = <&adv7535_out>; 34 }; 35 }; 36 }; 37 38 memory@40000000 { 39 device_type = "memory"; 40 reg = <0x0 0x40000000 0 0x80000000>; 41 }; 42 43 reg_usdhc2_vmmc: regulator-usdhc2 { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 47 regulator-name = "VSD_3V3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 51 off-on-delay-us = <12000>; 52 enable-active-high; 53 }; 54 55 reg_1v5: regulator-1v5 { 56 compatible = "regulator-fixed"; 57 regulator-name = "VDD_1V5"; 58 regulator-min-microvolt = <1500000>; 59 regulator-max-microvolt = <1500000>; 60 }; 61 62 reg_1v8: regulator-1v8 { 63 compatible = "regulator-fixed"; 64 regulator-name = "VDD_1V8"; 65 regulator-min-microvolt = <1800000>; 66 regulator-max-microvolt = <1800000>; 67 }; 68 69 reg_vddext_3v3: regulator-vddext-3v3 { 70 compatible = "regulator-fixed"; 71 regulator-name = "VDDEXT_3V3"; 72 regulator-min-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>; 74 }; 75 76 ir-receiver { 77 compatible = "gpio-ir-receiver"; 78 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_ir>; 81 linux,autosuspend-period = <125>; 82 }; 83 84 audio_codec_bt_sco: audio-codec-bt-sco { 85 compatible = "linux,bt-sco"; 86 #sound-dai-cells = <1>; 87 }; 88 89 wm8524: audio-codec { 90 #sound-dai-cells = <0>; 91 compatible = "wlf,wm8524"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_gpio_wlf>; 94 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 95 }; 96 97 sound-bt-sco { 98 compatible = "simple-audio-card"; 99 simple-audio-card,name = "bt-sco-audio"; 100 simple-audio-card,format = "dsp_a"; 101 simple-audio-card,bitclock-inversion; 102 simple-audio-card,frame-master = <&btcpu>; 103 simple-audio-card,bitclock-master = <&btcpu>; 104 105 btcpu: simple-audio-card,cpu { 106 sound-dai = <&sai2>; 107 dai-tdm-slot-num = <2>; 108 dai-tdm-slot-width = <16>; 109 }; 110 111 simple-audio-card,codec { 112 sound-dai = <&audio_codec_bt_sco 1>; 113 }; 114 }; 115 116 sound-wm8524 { 117 compatible = "fsl,imx-audio-wm8524"; 118 model = "wm8524-audio"; 119 audio-cpu = <&sai3>; 120 audio-codec = <&wm8524>; 121 audio-asrc = <&easrc>; 122 audio-routing = 123 "Line Out Jack", "LINEVOUTL", 124 "Line Out Jack", "LINEVOUTR"; 125 }; 126 127 spdif_out: spdif-out { 128 compatible = "linux,spdif-dit"; 129 #sound-dai-cells = <0>; 130 }; 131 132 spdif_in: spdif-in { 133 compatible = "linux,spdif-dir"; 134 #sound-dai-cells = <0>; 135 }; 136 137 sound-spdif { 138 compatible = "fsl,imx-audio-spdif"; 139 model = "imx-spdif"; 140 audio-cpu = <&spdif1>; 141 audio-codec = <&spdif_out>, <&spdif_in>; 142 }; 143 144 sound-micfil { 145 compatible = "fsl,imx-audio-card"; 146 model = "micfil-audio"; 147 148 pri-dai-link { 149 link-name = "micfil hifi"; 150 format = "i2s"; 151 152 cpu { 153 sound-dai = <&micfil>; 154 }; 155 }; 156 }; 157}; 158 159&easrc { 160 fsl,asrc-rate = <48000>; 161 status = "okay"; 162}; 163 164&fec1 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_fec1>; 167 phy-mode = "rgmii-id"; 168 phy-handle = <ðphy0>; 169 fsl,magic-packet; 170 status = "okay"; 171 172 mdio { 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 ethphy0: ethernet-phy@0 { 177 compatible = "ethernet-phy-ieee802.3-c22"; 178 reg = <0>; 179 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 180 reset-assert-us = <10000>; 181 qca,disable-smarteee; 182 vddio-supply = <&vddio>; 183 184 vddio: vddio-regulator { 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <1800000>; 187 }; 188 }; 189 }; 190}; 191 192&flexspi { 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_flexspi>; 195 status = "okay"; 196 197 flash0: flash@0 { 198 compatible = "jedec,spi-nor"; 199 reg = <0>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 spi-max-frequency = <166000000>; 203 spi-tx-bus-width = <4>; 204 spi-rx-bus-width = <4>; 205 }; 206}; 207 208&i2c1 { 209 clock-frequency = <400000>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_i2c1>; 212 status = "okay"; 213}; 214 215&i2c2 { 216 clock-frequency = <400000>; 217 pinctrl-names = "default", "gpio"; 218 pinctrl-0 = <&pinctrl_i2c2>; 219 pinctrl-1 = <&pinctrl_i2c2_gpio>; 220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 222 status = "okay"; 223 224 hdmi@3d { 225 compatible = "adi,adv7535"; 226 reg = <0x3d>; 227 interrupt-parent = <&gpio1>; 228 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 229 adi,dsi-lanes = <4>; 230 v3p3-supply = <®_vddext_3v3>; 231 232 ports { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 236 port@0 { 237 reg = <0>; 238 239 adv7535_in: endpoint { 240 remote-endpoint = <&dsi_out>; 241 }; 242 }; 243 244 port@1 { 245 reg = <1>; 246 247 adv7535_out: endpoint { 248 remote-endpoint = <&hdmi_connector_in>; 249 }; 250 }; 251 252 }; 253 }; 254 255 ptn5110: tcpc@50 { 256 compatible = "nxp,ptn5110", "tcpci"; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_typec1>; 259 reg = <0x50>; 260 interrupt-parent = <&gpio2>; 261 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 262 status = "okay"; 263 264 typec1_con: connector { 265 compatible = "usb-c-connector"; 266 label = "USB-C"; 267 power-role = "dual"; 268 data-role = "dual"; 269 try-power-role = "sink"; 270 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 271 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 272 PDO_VAR(5000, 20000, 3000)>; 273 op-sink-microwatt = <15000000>; 274 self-powered; 275 276 port { 277 typec1_dr_sw: endpoint { 278 remote-endpoint = <&usb1_drd_sw>; 279 }; 280 }; 281 }; 282 }; 283}; 284 285&i2c3 { 286 clock-frequency = <400000>; 287 pinctrl-names = "default", "gpio"; 288 pinctrl-0 = <&pinctrl_i2c3>; 289 pinctrl-1 = <&pinctrl_i2c3_gpio>; 290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 292 status = "okay"; 293 294 pca6416: gpio@20 { 295 compatible = "ti,tca6416"; 296 reg = <0x20>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 }; 300 301 camera@3c { 302 compatible = "ovti,ov5640"; 303 reg = <0x3c>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_camera>; 306 clocks = <&clk IMX8MN_CLK_CLKO1>; 307 clock-names = "xclk"; 308 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; 309 assigned-clock-parents = <&clk IMX8MN_CLK_24M>; 310 assigned-clock-rates = <24000000>; 311 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 312 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 313 AVDD-supply = <®_1v8>; 314 DVDD-supply = <®_1v5>; 315 316 port { 317 ov5640_to_mipi_csi2: endpoint { 318 remote-endpoint = <&imx8mn_mipi_csi_in>; 319 clock-lanes = <0>; 320 data-lanes = <1 2>; 321 }; 322 }; 323 }; 324}; 325 326&isi { 327 status = "okay"; 328}; 329 330&micfil { 331 #sound-dai-cells = <0>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_pdm>; 334 assigned-clocks = <&clk IMX8MN_CLK_PDM>; 335 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 336 assigned-clock-rates = <196608000>; 337 status = "okay"; 338}; 339 340&mipi_csi { 341 status = "okay"; 342 343 ports { 344 port@0 { 345 imx8mn_mipi_csi_in: endpoint { 346 remote-endpoint = <&ov5640_to_mipi_csi2>; 347 data-lanes = <1 2>; 348 }; 349 }; 350 }; 351}; 352 353&lcdif { 354 status = "okay"; 355}; 356 357&mipi_dsi { 358 samsung,esc-clock-frequency = <10000000>; 359 status = "okay"; 360 361 ports { 362 port@1 { 363 reg = <1>; 364 365 dsi_out: endpoint { 366 remote-endpoint = <&adv7535_in>; 367 data-lanes = <1 2 3 4>; 368 }; 369 }; 370 }; 371}; 372 373&sai2 { 374 #sound-dai-cells = <0>; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_sai2>; 377 assigned-clocks = <&clk IMX8MN_CLK_SAI2>; 378 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 379 assigned-clock-rates = <24576000>; 380 status = "okay"; 381}; 382 383&sai3 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_sai3>; 386 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 387 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 388 assigned-clock-rates = <24576000>; 389 fsl,sai-mclk-direction-output; 390 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, 391 <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, 392 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, 393 <&clk IMX8MN_AUDIO_PLL2_OUT>; 394 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 395 status = "okay"; 396}; 397 398&snvs_pwrkey { 399 status = "okay"; 400}; 401 402&spdif1 { 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_spdif1>; 405 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; 406 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 407 assigned-clock-rates = <24576000>; 408 status = "okay"; 409}; 410 411&uart1 { /* BT */ 412 pinctrl-names = "default"; 413 pinctrl-0 = <&pinctrl_uart1>; 414 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 415 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 416 uart-has-rtscts; 417 status = "okay"; 418}; 419 420&uart2 { /* console */ 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_uart2>; 423 status = "okay"; 424}; 425 426&uart3 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_uart3>; 429 assigned-clocks = <&clk IMX8MN_CLK_UART3>; 430 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 431 uart-has-rtscts; 432 status = "okay"; 433}; 434 435&usbphynop1 { 436 wakeup-source; 437}; 438 439&usbotg1 { 440 dr_mode = "otg"; 441 hnp-disable; 442 srp-disable; 443 adp-disable; 444 usb-role-switch; 445 disable-over-current; 446 samsung,picophy-pre-emp-curr-control = <3>; 447 samsung,picophy-dc-vol-level-adjust = <7>; 448 status = "okay"; 449 450 port { 451 usb1_drd_sw: endpoint { 452 remote-endpoint = <&typec1_dr_sw>; 453 }; 454 }; 455}; 456 457&usdhc2 { 458 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; 459 assigned-clock-rates = <200000000>; 460 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 461 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 462 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 463 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 464 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 465 bus-width = <4>; 466 vmmc-supply = <®_usdhc2_vmmc>; 467 status = "okay"; 468}; 469 470&usdhc3 { 471 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 472 assigned-clock-rates = <400000000>; 473 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 474 pinctrl-0 = <&pinctrl_usdhc3>; 475 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 476 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 477 bus-width = <8>; 478 non-removable; 479 status = "okay"; 480}; 481 482&wdog1 { 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pinctrl_wdog>; 485 fsl,ext-reset-output; 486 status = "okay"; 487}; 488 489&iomuxc { 490 pinctrl_camera: cameragrp { 491 fsl,pins = < 492 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 493 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 494 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 495 >; 496 }; 497 498 pinctrl_fec1: fec1grp { 499 fsl,pins = < 500 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 501 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 502 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 503 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 504 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 505 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 506 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 507 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 508 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 509 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 510 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 511 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 512 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 513 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 514 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 515 >; 516 }; 517 518 pinctrl_flexspi: flexspigrp { 519 fsl,pins = < 520 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 521 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 522 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 523 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 524 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 525 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 526 >; 527 }; 528 529 pinctrl_gpio_led: gpioledgrp { 530 fsl,pins = < 531 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 532 >; 533 }; 534 535 pinctrl_gpio_wlf: gpiowlfgrp { 536 fsl,pins = < 537 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 538 >; 539 }; 540 541 pinctrl_ir: irgrp { 542 fsl,pins = < 543 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 544 >; 545 }; 546 547 pinctrl_i2c1: i2c1grp { 548 fsl,pins = < 549 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 550 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 551 >; 552 }; 553 554 pinctrl_i2c2: i2c2grp { 555 fsl,pins = < 556 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 557 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 558 >; 559 }; 560 561 pinctrl_i2c2_gpio: i2c2gpiogrp { 562 fsl,pins = < 563 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 564 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 565 >; 566 }; 567 568 pinctrl_i2c3: i2c3grp { 569 fsl,pins = < 570 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 571 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 572 >; 573 }; 574 575 pinctrl_i2c3_gpio: i2c3gpiogrp { 576 fsl,pins = < 577 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 578 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 579 >; 580 }; 581 582 pinctrl_pdm: pdmgrp { 583 fsl,pins = < 584 MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 585 MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 586 MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 587 MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 588 MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 589 MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 590 MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 591 >; 592 }; 593 594 pinctrl_pmic: pmicirqgrp { 595 fsl,pins = < 596 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 597 >; 598 }; 599 600 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 601 fsl,pins = < 602 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 603 >; 604 }; 605 606 pinctrl_sai2: sai2grp { 607 fsl,pins = < 608 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 609 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 610 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 611 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 612 >; 613 }; 614 615 pinctrl_sai3: sai3grp { 616 fsl,pins = < 617 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 618 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 619 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 620 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 621 >; 622 }; 623 624 pinctrl_spdif1: spdif1grp { 625 fsl,pins = < 626 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 627 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 628 >; 629 }; 630 631 pinctrl_typec1: typec1grp { 632 fsl,pins = < 633 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 634 >; 635 }; 636 637 pinctrl_uart1: uart1grp { 638 fsl,pins = < 639 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 640 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 641 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 642 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 643 >; 644 }; 645 646 pinctrl_uart2: uart2grp { 647 fsl,pins = < 648 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 649 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 650 >; 651 }; 652 653 pinctrl_uart3: uart3grp { 654 fsl,pins = < 655 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 656 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 657 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 658 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 659 >; 660 }; 661 662 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 663 fsl,pins = < 664 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 665 >; 666 }; 667 668 pinctrl_usdhc2: usdhc2grp { 669 fsl,pins = < 670 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 671 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 672 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 673 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 674 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 675 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 676 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 677 >; 678 }; 679 680 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 681 fsl,pins = < 682 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 683 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 684 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 685 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 686 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 687 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 688 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 689 >; 690 }; 691 692 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 693 fsl,pins = < 694 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 695 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 696 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 697 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 698 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 699 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 700 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 701 >; 702 }; 703 704 pinctrl_usdhc3: usdhc3grp { 705 fsl,pins = < 706 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 707 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 708 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 709 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 710 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 711 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 712 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 713 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 714 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 715 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 716 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 717 >; 718 }; 719 720 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 721 fsl,pins = < 722 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 723 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 724 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 725 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 726 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 727 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 728 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 729 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 730 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 731 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 732 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 733 >; 734 }; 735 736 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 737 fsl,pins = < 738 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 739 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 740 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 741 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 742 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 743 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 744 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 745 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 746 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 747 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 748 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 749 >; 750 }; 751 752 pinctrl_wdog: wdoggrp { 753 fsl,pins = < 754 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 755 >; 756 }; 757}; 758