1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/usb/pd.h> 7#include "imx8mn.dtsi" 8 9/ { 10 chosen { 11 stdout-path = &uart2; 12 }; 13 14 gpio-leds { 15 compatible = "gpio-leds"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_led>; 18 19 status { 20 label = "yellow:status"; 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 22 default-state = "on"; 23 }; 24 }; 25 26 hdmi-connector { 27 compatible = "hdmi-connector"; 28 label = "hdmi"; 29 type = "a"; 30 31 port { 32 hdmi_connector_in: endpoint { 33 remote-endpoint = <&adv7533_out>; 34 }; 35 }; 36 }; 37 38 memory@40000000 { 39 device_type = "memory"; 40 reg = <0x0 0x40000000 0 0x80000000>; 41 }; 42 43 reg_usdhc2_vmmc: regulator-usdhc2 { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 47 regulator-name = "VSD_3V3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 51 off-on-delay-us = <12000>; 52 enable-active-high; 53 }; 54 55 ir-receiver { 56 compatible = "gpio-ir-receiver"; 57 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_ir>; 60 linux,autosuspend-period = <125>; 61 }; 62 63 audio_codec_bt_sco: audio-codec-bt-sco { 64 compatible = "linux,bt-sco"; 65 #sound-dai-cells = <1>; 66 }; 67 68 wm8524: audio-codec { 69 #sound-dai-cells = <0>; 70 compatible = "wlf,wm8524"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_gpio_wlf>; 73 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 74 }; 75 76 sound-bt-sco { 77 compatible = "simple-audio-card"; 78 simple-audio-card,name = "bt-sco-audio"; 79 simple-audio-card,format = "dsp_a"; 80 simple-audio-card,bitclock-inversion; 81 simple-audio-card,frame-master = <&btcpu>; 82 simple-audio-card,bitclock-master = <&btcpu>; 83 84 btcpu: simple-audio-card,cpu { 85 sound-dai = <&sai2>; 86 dai-tdm-slot-num = <2>; 87 dai-tdm-slot-width = <16>; 88 }; 89 90 simple-audio-card,codec { 91 sound-dai = <&audio_codec_bt_sco 1>; 92 }; 93 }; 94 95 sound-wm8524 { 96 compatible = "fsl,imx-audio-wm8524"; 97 model = "wm8524-audio"; 98 audio-cpu = <&sai3>; 99 audio-codec = <&wm8524>; 100 audio-asrc = <&easrc>; 101 audio-routing = 102 "Line Out Jack", "LINEVOUTL", 103 "Line Out Jack", "LINEVOUTR"; 104 }; 105 106 sound-spdif { 107 compatible = "fsl,imx-audio-spdif"; 108 model = "imx-spdif"; 109 spdif-controller = <&spdif1>; 110 spdif-out; 111 spdif-in; 112 }; 113 114 sound-micfil { 115 compatible = "fsl,imx-audio-card"; 116 model = "micfil-audio"; 117 118 pri-dai-link { 119 link-name = "micfil hifi"; 120 format = "i2s"; 121 122 cpu { 123 sound-dai = <&micfil>; 124 }; 125 }; 126 }; 127}; 128 129&easrc { 130 fsl,asrc-rate = <48000>; 131 status = "okay"; 132}; 133 134&fec1 { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_fec1>; 137 phy-mode = "rgmii-id"; 138 phy-handle = <ðphy0>; 139 fsl,magic-packet; 140 status = "okay"; 141 142 mdio { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 ethphy0: ethernet-phy@0 { 147 compatible = "ethernet-phy-ieee802.3-c22"; 148 reg = <0>; 149 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 150 reset-assert-us = <10000>; 151 qca,disable-smarteee; 152 vddio-supply = <&vddio>; 153 154 vddio: vddio-regulator { 155 regulator-min-microvolt = <1800000>; 156 regulator-max-microvolt = <1800000>; 157 }; 158 }; 159 }; 160}; 161 162&flexspi { 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_flexspi>; 165 status = "okay"; 166 167 flash0: flash@0 { 168 compatible = "jedec,spi-nor"; 169 reg = <0>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 spi-max-frequency = <166000000>; 173 spi-tx-bus-width = <4>; 174 spi-rx-bus-width = <4>; 175 }; 176}; 177 178&i2c1 { 179 clock-frequency = <400000>; 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_i2c1>; 182 status = "okay"; 183}; 184 185&i2c2 { 186 clock-frequency = <400000>; 187 pinctrl-names = "default", "gpio"; 188 pinctrl-0 = <&pinctrl_i2c2>; 189 pinctrl-1 = <&pinctrl_i2c2_gpio>; 190 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 191 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 192 status = "okay"; 193 194 hdmi@3d { 195 compatible = "adi,adv7535"; 196 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 197 reg-names = "main", "cec", "edid", "packet"; 198 adi,dsi-lanes = <4>; 199 200 adi,input-depth = <8>; 201 adi,input-colorspace = "rgb"; 202 adi,input-clock = "1x"; 203 adi,input-style = <1>; 204 adi,input-justification = "evenly"; 205 206 ports { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 210 port@0 { 211 reg = <0>; 212 213 adv7533_in: endpoint { 214 remote-endpoint = <&dsi_out>; 215 }; 216 }; 217 218 port@1 { 219 reg = <1>; 220 221 adv7533_out: endpoint { 222 remote-endpoint = <&hdmi_connector_in>; 223 }; 224 }; 225 226 }; 227 }; 228 229 ptn5110: tcpc@50 { 230 compatible = "nxp,ptn5110"; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_typec1>; 233 reg = <0x50>; 234 interrupt-parent = <&gpio2>; 235 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 236 status = "okay"; 237 238 typec1_con: connector { 239 compatible = "usb-c-connector"; 240 label = "USB-C"; 241 power-role = "dual"; 242 data-role = "dual"; 243 try-power-role = "sink"; 244 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 245 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 246 PDO_VAR(5000, 20000, 3000)>; 247 op-sink-microwatt = <15000000>; 248 self-powered; 249 250 port { 251 typec1_dr_sw: endpoint { 252 remote-endpoint = <&usb1_drd_sw>; 253 }; 254 }; 255 }; 256 }; 257}; 258 259&i2c3 { 260 clock-frequency = <400000>; 261 pinctrl-names = "default", "gpio"; 262 pinctrl-0 = <&pinctrl_i2c3>; 263 pinctrl-1 = <&pinctrl_i2c3_gpio>; 264 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 265 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 266 status = "okay"; 267 268 pca6416: gpio@20 { 269 compatible = "ti,tca6416"; 270 reg = <0x20>; 271 gpio-controller; 272 #gpio-cells = <2>; 273 }; 274 275 camera@3c { 276 compatible = "ovti,ov5640"; 277 reg = <0x3c>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_camera>; 280 clocks = <&clk IMX8MN_CLK_CLKO1>; 281 clock-names = "xclk"; 282 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; 283 assigned-clock-parents = <&clk IMX8MN_CLK_24M>; 284 assigned-clock-rates = <24000000>; 285 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 286 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 287 288 port { 289 ov5640_to_mipi_csi2: endpoint { 290 remote-endpoint = <&imx8mn_mipi_csi_in>; 291 clock-lanes = <0>; 292 data-lanes = <1 2>; 293 }; 294 }; 295 }; 296}; 297 298&isi { 299 status = "okay"; 300}; 301 302&micfil { 303 #sound-dai-cells = <0>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_pdm>; 306 assigned-clocks = <&clk IMX8MN_CLK_PDM>; 307 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 308 assigned-clock-rates = <196608000>; 309 status = "okay"; 310}; 311 312&mipi_csi { 313 status = "okay"; 314 315 ports { 316 port@0 { 317 imx8mn_mipi_csi_in: endpoint { 318 remote-endpoint = <&ov5640_to_mipi_csi2>; 319 data-lanes = <1 2>; 320 }; 321 }; 322 }; 323}; 324 325&lcdif { 326 status = "okay"; 327}; 328 329&mipi_dsi { 330 samsung,esc-clock-frequency = <10000000>; 331 status = "okay"; 332 333 ports { 334 port@1 { 335 reg = <1>; 336 337 dsi_out: endpoint { 338 remote-endpoint = <&adv7533_in>; 339 data-lanes = <1 2 3 4>; 340 }; 341 }; 342 }; 343}; 344 345&sai2 { 346 #sound-dai-cells = <0>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_sai2>; 349 assigned-clocks = <&clk IMX8MN_CLK_SAI2>; 350 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 351 assigned-clock-rates = <24576000>; 352 status = "okay"; 353}; 354 355&sai3 { 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_sai3>; 358 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 359 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 360 assigned-clock-rates = <24576000>; 361 fsl,sai-mclk-direction-output; 362 status = "okay"; 363}; 364 365&snvs_pwrkey { 366 status = "okay"; 367}; 368 369&spdif1 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_spdif1>; 372 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; 373 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 374 assigned-clock-rates = <24576000>; 375 status = "okay"; 376}; 377 378&uart1 { /* BT */ 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_uart1>; 381 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 382 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 383 uart-has-rtscts; 384 status = "okay"; 385}; 386 387&uart2 { /* console */ 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_uart2>; 390 status = "okay"; 391}; 392 393&uart3 { 394 pinctrl-names = "default"; 395 pinctrl-0 = <&pinctrl_uart3>; 396 assigned-clocks = <&clk IMX8MN_CLK_UART3>; 397 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 398 uart-has-rtscts; 399 status = "okay"; 400}; 401 402&usbphynop1 { 403 wakeup-source; 404}; 405 406&usbotg1 { 407 dr_mode = "otg"; 408 hnp-disable; 409 srp-disable; 410 adp-disable; 411 usb-role-switch; 412 disable-over-current; 413 samsung,picophy-pre-emp-curr-control = <3>; 414 samsung,picophy-dc-vol-level-adjust = <7>; 415 status = "okay"; 416 417 port { 418 usb1_drd_sw: endpoint { 419 remote-endpoint = <&typec1_dr_sw>; 420 }; 421 }; 422}; 423 424&usdhc2 { 425 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; 426 assigned-clock-rates = <200000000>; 427 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 428 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 429 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 430 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 431 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 432 bus-width = <4>; 433 vmmc-supply = <®_usdhc2_vmmc>; 434 status = "okay"; 435}; 436 437&usdhc3 { 438 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 439 assigned-clock-rates = <400000000>; 440 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 441 pinctrl-0 = <&pinctrl_usdhc3>; 442 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 443 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 444 bus-width = <8>; 445 non-removable; 446 status = "okay"; 447}; 448 449&wdog1 { 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_wdog>; 452 fsl,ext-reset-output; 453 status = "okay"; 454}; 455 456&iomuxc { 457 pinctrl_camera: cameragrp { 458 fsl,pins = < 459 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 460 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 461 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 462 >; 463 }; 464 465 pinctrl_fec1: fec1grp { 466 fsl,pins = < 467 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 468 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 469 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 470 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 471 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 472 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 473 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 474 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 475 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 476 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 477 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 478 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 479 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 480 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 481 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 482 >; 483 }; 484 485 pinctrl_flexspi: flexspigrp { 486 fsl,pins = < 487 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 488 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 489 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 490 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 491 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 492 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 493 >; 494 }; 495 496 pinctrl_gpio_led: gpioledgrp { 497 fsl,pins = < 498 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 499 >; 500 }; 501 502 pinctrl_gpio_wlf: gpiowlfgrp { 503 fsl,pins = < 504 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 505 >; 506 }; 507 508 pinctrl_ir: irgrp { 509 fsl,pins = < 510 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 511 >; 512 }; 513 514 pinctrl_i2c1: i2c1grp { 515 fsl,pins = < 516 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 517 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 518 >; 519 }; 520 521 pinctrl_i2c2: i2c2grp { 522 fsl,pins = < 523 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 524 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 525 >; 526 }; 527 528 pinctrl_i2c2_gpio: i2c2gpiogrp { 529 fsl,pins = < 530 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 531 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 532 >; 533 }; 534 535 pinctrl_i2c3: i2c3grp { 536 fsl,pins = < 537 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 538 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 539 >; 540 }; 541 542 pinctrl_i2c3_gpio: i2c3gpiogrp { 543 fsl,pins = < 544 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 545 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 546 >; 547 }; 548 549 pinctrl_pdm: pdmgrp { 550 fsl,pins = < 551 MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 552 MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 553 MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 554 MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 555 MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 556 MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 557 MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 558 >; 559 }; 560 561 pinctrl_pmic: pmicirqgrp { 562 fsl,pins = < 563 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 564 >; 565 }; 566 567 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 568 fsl,pins = < 569 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 570 >; 571 }; 572 573 pinctrl_sai2: sai2grp { 574 fsl,pins = < 575 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 576 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 577 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 578 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 579 >; 580 }; 581 582 pinctrl_sai3: sai3grp { 583 fsl,pins = < 584 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 585 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 586 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 587 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 588 >; 589 }; 590 591 pinctrl_spdif1: spdif1grp { 592 fsl,pins = < 593 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 594 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 595 >; 596 }; 597 598 pinctrl_typec1: typec1grp { 599 fsl,pins = < 600 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 601 >; 602 }; 603 604 pinctrl_uart1: uart1grp { 605 fsl,pins = < 606 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 607 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 608 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 609 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 610 >; 611 }; 612 613 pinctrl_uart2: uart2grp { 614 fsl,pins = < 615 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 616 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 617 >; 618 }; 619 620 pinctrl_uart3: uart3grp { 621 fsl,pins = < 622 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 623 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 624 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 625 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 626 >; 627 }; 628 629 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 630 fsl,pins = < 631 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 632 >; 633 }; 634 635 pinctrl_usdhc2: usdhc2grp { 636 fsl,pins = < 637 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 638 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 639 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 640 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 641 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 642 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 643 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 644 >; 645 }; 646 647 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 648 fsl,pins = < 649 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 650 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 651 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 652 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 653 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 654 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 655 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 656 >; 657 }; 658 659 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 660 fsl,pins = < 661 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 662 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 663 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 664 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 665 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 666 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 667 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 668 >; 669 }; 670 671 pinctrl_usdhc3: usdhc3grp { 672 fsl,pins = < 673 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 674 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 675 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 676 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 677 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 678 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 679 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 680 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 681 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 682 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 683 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 684 >; 685 }; 686 687 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 688 fsl,pins = < 689 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 690 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 691 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 692 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 693 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 694 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 695 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 696 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 697 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 698 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 699 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 700 >; 701 }; 702 703 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 704 fsl,pins = < 705 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 706 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 707 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 708 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 709 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 710 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 711 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 712 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 713 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 714 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 715 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 716 >; 717 }; 718 719 pinctrl_wdog: wdoggrp { 720 fsl,pins = < 721 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 722 >; 723 }; 724}; 725