1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/usb/pd.h> 7#include "imx8mn.dtsi" 8 9/ { 10 chosen { 11 stdout-path = &uart2; 12 }; 13 14 gpio-leds { 15 compatible = "gpio-leds"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_led>; 18 19 status { 20 label = "yellow:status"; 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 22 default-state = "on"; 23 }; 24 }; 25 26 hdmi-connector { 27 compatible = "hdmi-connector"; 28 label = "hdmi"; 29 type = "a"; 30 31 port { 32 hdmi_connector_in: endpoint { 33 remote-endpoint = <&adv7535_out>; 34 }; 35 }; 36 }; 37 38 memory@40000000 { 39 device_type = "memory"; 40 reg = <0x0 0x40000000 0 0x80000000>; 41 }; 42 43 reg_usdhc2_vmmc: regulator-usdhc2 { 44 compatible = "regulator-fixed"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 47 regulator-name = "VSD_3V3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 51 off-on-delay-us = <12000>; 52 enable-active-high; 53 }; 54 55 reg_1v5: regulator-1v5 { 56 compatible = "regulator-fixed"; 57 regulator-name = "VDD_1V5"; 58 regulator-min-microvolt = <1500000>; 59 regulator-max-microvolt = <1500000>; 60 }; 61 62 reg_1v8: regulator-1v8 { 63 compatible = "regulator-fixed"; 64 regulator-name = "VDD_1V8"; 65 regulator-min-microvolt = <1800000>; 66 regulator-max-microvolt = <1800000>; 67 }; 68 69 reg_vddext_3v3: regulator-vddext-3v3 { 70 compatible = "regulator-fixed"; 71 regulator-name = "VDDEXT_3V3"; 72 regulator-min-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>; 74 }; 75 76 ir-receiver { 77 compatible = "gpio-ir-receiver"; 78 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_ir>; 81 linux,autosuspend-period = <125>; 82 }; 83 84 audio_codec_bt_sco: audio-codec-bt-sco { 85 compatible = "linux,bt-sco"; 86 #sound-dai-cells = <1>; 87 }; 88 89 wm8524: audio-codec { 90 #sound-dai-cells = <0>; 91 compatible = "wlf,wm8524"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_gpio_wlf>; 94 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 95 }; 96 97 sound-bt-sco { 98 compatible = "simple-audio-card"; 99 simple-audio-card,name = "bt-sco-audio"; 100 simple-audio-card,format = "dsp_a"; 101 simple-audio-card,bitclock-inversion; 102 simple-audio-card,frame-master = <&btcpu>; 103 simple-audio-card,bitclock-master = <&btcpu>; 104 105 btcpu: simple-audio-card,cpu { 106 sound-dai = <&sai2>; 107 dai-tdm-slot-num = <2>; 108 dai-tdm-slot-width = <16>; 109 }; 110 111 simple-audio-card,codec { 112 sound-dai = <&audio_codec_bt_sco 1>; 113 }; 114 }; 115 116 sound-wm8524 { 117 compatible = "fsl,imx-audio-wm8524"; 118 model = "wm8524-audio"; 119 audio-cpu = <&sai3>; 120 audio-codec = <&wm8524>; 121 audio-asrc = <&easrc>; 122 audio-routing = 123 "Line Out Jack", "LINEVOUTL", 124 "Line Out Jack", "LINEVOUTR"; 125 }; 126 127 sound-spdif { 128 compatible = "fsl,imx-audio-spdif"; 129 model = "imx-spdif"; 130 spdif-controller = <&spdif1>; 131 spdif-out; 132 spdif-in; 133 }; 134 135 sound-micfil { 136 compatible = "fsl,imx-audio-card"; 137 model = "micfil-audio"; 138 139 pri-dai-link { 140 link-name = "micfil hifi"; 141 format = "i2s"; 142 143 cpu { 144 sound-dai = <&micfil>; 145 }; 146 }; 147 }; 148}; 149 150&easrc { 151 fsl,asrc-rate = <48000>; 152 status = "okay"; 153}; 154 155&fec1 { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_fec1>; 158 phy-mode = "rgmii-id"; 159 phy-handle = <ðphy0>; 160 fsl,magic-packet; 161 status = "okay"; 162 163 mdio { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 ethphy0: ethernet-phy@0 { 168 compatible = "ethernet-phy-ieee802.3-c22"; 169 reg = <0>; 170 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 171 reset-assert-us = <10000>; 172 qca,disable-smarteee; 173 vddio-supply = <&vddio>; 174 175 vddio: vddio-regulator { 176 regulator-min-microvolt = <1800000>; 177 regulator-max-microvolt = <1800000>; 178 }; 179 }; 180 }; 181}; 182 183&flexspi { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_flexspi>; 186 status = "okay"; 187 188 flash0: flash@0 { 189 compatible = "jedec,spi-nor"; 190 reg = <0>; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 spi-max-frequency = <166000000>; 194 spi-tx-bus-width = <4>; 195 spi-rx-bus-width = <4>; 196 }; 197}; 198 199&i2c1 { 200 clock-frequency = <400000>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_i2c1>; 203 status = "okay"; 204}; 205 206&i2c2 { 207 clock-frequency = <400000>; 208 pinctrl-names = "default", "gpio"; 209 pinctrl-0 = <&pinctrl_i2c2>; 210 pinctrl-1 = <&pinctrl_i2c2_gpio>; 211 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 212 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 213 status = "okay"; 214 215 hdmi@3d { 216 compatible = "adi,adv7535"; 217 reg = <0x3d>; 218 interrupt-parent = <&gpio1>; 219 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 220 adi,dsi-lanes = <4>; 221 v3p3-supply = <®_vddext_3v3>; 222 223 ports { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 port@0 { 228 reg = <0>; 229 230 adv7535_in: endpoint { 231 remote-endpoint = <&dsi_out>; 232 }; 233 }; 234 235 port@1 { 236 reg = <1>; 237 238 adv7535_out: endpoint { 239 remote-endpoint = <&hdmi_connector_in>; 240 }; 241 }; 242 243 }; 244 }; 245 246 ptn5110: tcpc@50 { 247 compatible = "nxp,ptn5110", "tcpci"; 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_typec1>; 250 reg = <0x50>; 251 interrupt-parent = <&gpio2>; 252 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 253 status = "okay"; 254 255 typec1_con: connector { 256 compatible = "usb-c-connector"; 257 label = "USB-C"; 258 power-role = "dual"; 259 data-role = "dual"; 260 try-power-role = "sink"; 261 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 262 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 263 PDO_VAR(5000, 20000, 3000)>; 264 op-sink-microwatt = <15000000>; 265 self-powered; 266 267 port { 268 typec1_dr_sw: endpoint { 269 remote-endpoint = <&usb1_drd_sw>; 270 }; 271 }; 272 }; 273 }; 274}; 275 276&i2c3 { 277 clock-frequency = <400000>; 278 pinctrl-names = "default", "gpio"; 279 pinctrl-0 = <&pinctrl_i2c3>; 280 pinctrl-1 = <&pinctrl_i2c3_gpio>; 281 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 282 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; 283 status = "okay"; 284 285 pca6416: gpio@20 { 286 compatible = "ti,tca6416"; 287 reg = <0x20>; 288 gpio-controller; 289 #gpio-cells = <2>; 290 }; 291 292 camera@3c { 293 compatible = "ovti,ov5640"; 294 reg = <0x3c>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_camera>; 297 clocks = <&clk IMX8MN_CLK_CLKO1>; 298 clock-names = "xclk"; 299 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; 300 assigned-clock-parents = <&clk IMX8MN_CLK_24M>; 301 assigned-clock-rates = <24000000>; 302 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 303 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 304 AVDD-supply = <®_1v8>; 305 DVDD-supply = <®_1v5>; 306 307 port { 308 ov5640_to_mipi_csi2: endpoint { 309 remote-endpoint = <&imx8mn_mipi_csi_in>; 310 clock-lanes = <0>; 311 data-lanes = <1 2>; 312 }; 313 }; 314 }; 315}; 316 317&isi { 318 status = "okay"; 319}; 320 321&micfil { 322 #sound-dai-cells = <0>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_pdm>; 325 assigned-clocks = <&clk IMX8MN_CLK_PDM>; 326 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 327 assigned-clock-rates = <196608000>; 328 status = "okay"; 329}; 330 331&mipi_csi { 332 status = "okay"; 333 334 ports { 335 port@0 { 336 imx8mn_mipi_csi_in: endpoint { 337 remote-endpoint = <&ov5640_to_mipi_csi2>; 338 data-lanes = <1 2>; 339 }; 340 }; 341 }; 342}; 343 344&lcdif { 345 status = "okay"; 346}; 347 348&mipi_dsi { 349 samsung,esc-clock-frequency = <10000000>; 350 status = "okay"; 351 352 ports { 353 port@1 { 354 reg = <1>; 355 356 dsi_out: endpoint { 357 remote-endpoint = <&adv7535_in>; 358 data-lanes = <1 2 3 4>; 359 }; 360 }; 361 }; 362}; 363 364&sai2 { 365 #sound-dai-cells = <0>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&pinctrl_sai2>; 368 assigned-clocks = <&clk IMX8MN_CLK_SAI2>; 369 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 370 assigned-clock-rates = <24576000>; 371 status = "okay"; 372}; 373 374&sai3 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_sai3>; 377 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 378 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 379 assigned-clock-rates = <24576000>; 380 fsl,sai-mclk-direction-output; 381 status = "okay"; 382}; 383 384&snvs_pwrkey { 385 status = "okay"; 386}; 387 388&spdif1 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_spdif1>; 391 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; 392 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 393 assigned-clock-rates = <24576000>; 394 status = "okay"; 395}; 396 397&uart1 { /* BT */ 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_uart1>; 400 assigned-clocks = <&clk IMX8MN_CLK_UART1>; 401 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 402 uart-has-rtscts; 403 status = "okay"; 404}; 405 406&uart2 { /* console */ 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_uart2>; 409 status = "okay"; 410}; 411 412&uart3 { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_uart3>; 415 assigned-clocks = <&clk IMX8MN_CLK_UART3>; 416 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 417 uart-has-rtscts; 418 status = "okay"; 419}; 420 421&usbphynop1 { 422 wakeup-source; 423}; 424 425&usbotg1 { 426 dr_mode = "otg"; 427 hnp-disable; 428 srp-disable; 429 adp-disable; 430 usb-role-switch; 431 disable-over-current; 432 samsung,picophy-pre-emp-curr-control = <3>; 433 samsung,picophy-dc-vol-level-adjust = <7>; 434 status = "okay"; 435 436 port { 437 usb1_drd_sw: endpoint { 438 remote-endpoint = <&typec1_dr_sw>; 439 }; 440 }; 441}; 442 443&usdhc2 { 444 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; 445 assigned-clock-rates = <200000000>; 446 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 447 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 448 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 449 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 450 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 451 bus-width = <4>; 452 vmmc-supply = <®_usdhc2_vmmc>; 453 status = "okay"; 454}; 455 456&usdhc3 { 457 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 458 assigned-clock-rates = <400000000>; 459 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 460 pinctrl-0 = <&pinctrl_usdhc3>; 461 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 462 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 463 bus-width = <8>; 464 non-removable; 465 status = "okay"; 466}; 467 468&wdog1 { 469 pinctrl-names = "default"; 470 pinctrl-0 = <&pinctrl_wdog>; 471 fsl,ext-reset-output; 472 status = "okay"; 473}; 474 475&iomuxc { 476 pinctrl_camera: cameragrp { 477 fsl,pins = < 478 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 479 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 480 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 481 >; 482 }; 483 484 pinctrl_fec1: fec1grp { 485 fsl,pins = < 486 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 487 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 488 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 489 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 490 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 491 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 492 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 493 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 494 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 495 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 496 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 497 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 498 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 499 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 500 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 501 >; 502 }; 503 504 pinctrl_flexspi: flexspigrp { 505 fsl,pins = < 506 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 507 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 508 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 509 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 510 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 511 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 512 >; 513 }; 514 515 pinctrl_gpio_led: gpioledgrp { 516 fsl,pins = < 517 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 518 >; 519 }; 520 521 pinctrl_gpio_wlf: gpiowlfgrp { 522 fsl,pins = < 523 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 524 >; 525 }; 526 527 pinctrl_ir: irgrp { 528 fsl,pins = < 529 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 530 >; 531 }; 532 533 pinctrl_i2c1: i2c1grp { 534 fsl,pins = < 535 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 536 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 537 >; 538 }; 539 540 pinctrl_i2c2: i2c2grp { 541 fsl,pins = < 542 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 543 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 544 >; 545 }; 546 547 pinctrl_i2c2_gpio: i2c2gpiogrp { 548 fsl,pins = < 549 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 550 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 551 >; 552 }; 553 554 pinctrl_i2c3: i2c3grp { 555 fsl,pins = < 556 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 557 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 558 >; 559 }; 560 561 pinctrl_i2c3_gpio: i2c3gpiogrp { 562 fsl,pins = < 563 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 564 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 565 >; 566 }; 567 568 pinctrl_pdm: pdmgrp { 569 fsl,pins = < 570 MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 571 MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 572 MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 573 MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 574 MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6 575 MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6 576 MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6 577 >; 578 }; 579 580 pinctrl_pmic: pmicirqgrp { 581 fsl,pins = < 582 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 583 >; 584 }; 585 586 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 587 fsl,pins = < 588 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 589 >; 590 }; 591 592 pinctrl_sai2: sai2grp { 593 fsl,pins = < 594 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 595 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 596 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 597 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 598 >; 599 }; 600 601 pinctrl_sai3: sai3grp { 602 fsl,pins = < 603 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 604 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 605 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 606 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 607 >; 608 }; 609 610 pinctrl_spdif1: spdif1grp { 611 fsl,pins = < 612 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 613 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 614 >; 615 }; 616 617 pinctrl_typec1: typec1grp { 618 fsl,pins = < 619 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 620 >; 621 }; 622 623 pinctrl_uart1: uart1grp { 624 fsl,pins = < 625 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 626 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 627 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 628 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 629 >; 630 }; 631 632 pinctrl_uart2: uart2grp { 633 fsl,pins = < 634 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 635 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 636 >; 637 }; 638 639 pinctrl_uart3: uart3grp { 640 fsl,pins = < 641 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 642 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 643 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 644 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 645 >; 646 }; 647 648 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 649 fsl,pins = < 650 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 651 >; 652 }; 653 654 pinctrl_usdhc2: usdhc2grp { 655 fsl,pins = < 656 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 657 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 658 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 659 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 660 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 661 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 662 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 663 >; 664 }; 665 666 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 667 fsl,pins = < 668 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 669 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 670 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 671 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 672 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 673 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 674 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 675 >; 676 }; 677 678 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 679 fsl,pins = < 680 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 681 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 682 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 683 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 684 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 685 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 686 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 687 >; 688 }; 689 690 pinctrl_usdhc3: usdhc3grp { 691 fsl,pins = < 692 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 693 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 694 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 695 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 696 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 697 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 698 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 699 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 700 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 701 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 702 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 703 >; 704 }; 705 706 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 707 fsl,pins = < 708 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 709 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 710 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 711 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 712 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 713 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 714 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 715 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 716 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 717 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 718 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 719 >; 720 }; 721 722 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 723 fsl,pins = < 724 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 725 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 726 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 727 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 728 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 729 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 730 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 731 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 732 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 733 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 734 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 735 >; 736 }; 737 738 pinctrl_wdog: wdoggrp { 739 fsl,pins = < 740 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 741 >; 742 }; 743}; 744