1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mm-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mm-pinfunc.h" 13 14/ { 15 compatible = "fsl,imx8mm"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet0 = &fec1; 22 i2c0 = &i2c1; 23 i2c1 = &i2c2; 24 i2c2 = &i2c3; 25 i2c3 = &i2c4; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 spi0 = &ecspi1; 31 spi1 = &ecspi2; 32 spi2 = &ecspi3; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 mmc2 = &usdhc3; 36 gpio0 = &gpio1; 37 gpio1 = &gpio2; 38 gpio2 = &gpio3; 39 gpio3 = &gpio4; 40 gpio4 = &gpio5; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 A53_0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x0>; 51 clock-latency = <61036>; /* two CLK32 periods */ 52 clocks = <&clk IMX8MM_CLK_ARM>; 53 enable-method = "psci"; 54 next-level-cache = <&A53_L2>; 55 operating-points-v2 = <&a53_opp_table>; 56 }; 57 58 A53_1: cpu@1 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x1>; 62 clock-latency = <61036>; /* two CLK32 periods */ 63 clocks = <&clk IMX8MM_CLK_ARM>; 64 enable-method = "psci"; 65 next-level-cache = <&A53_L2>; 66 operating-points-v2 = <&a53_opp_table>; 67 }; 68 69 A53_2: cpu@2 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x2>; 73 clock-latency = <61036>; /* two CLK32 periods */ 74 clocks = <&clk IMX8MM_CLK_ARM>; 75 enable-method = "psci"; 76 next-level-cache = <&A53_L2>; 77 operating-points-v2 = <&a53_opp_table>; 78 }; 79 80 A53_3: cpu@3 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x3>; 84 clock-latency = <61036>; /* two CLK32 periods */ 85 clocks = <&clk IMX8MM_CLK_ARM>; 86 enable-method = "psci"; 87 next-level-cache = <&A53_L2>; 88 operating-points-v2 = <&a53_opp_table>; 89 }; 90 91 A53_L2: l2-cache0 { 92 compatible = "cache"; 93 }; 94 }; 95 96 a53_opp_table: opp-table { 97 compatible = "operating-points-v2"; 98 opp-shared; 99 100 opp-1200000000 { 101 opp-hz = /bits/ 64 <1200000000>; 102 opp-microvolt = <850000>; 103 clock-latency-ns = <150000>; 104 }; 105 106 opp-1600000000 { 107 opp-hz = /bits/ 64 <1600000000>; 108 opp-microvolt = <900000>; 109 clock-latency-ns = <150000>; 110 opp-suspend; 111 }; 112 }; 113 114 memory@40000000 { 115 device_type = "memory"; 116 reg = <0x0 0x40000000 0 0x80000000>; 117 }; 118 119 osc_32k: clock-osc-32k { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <32768>; 123 clock-output-names = "osc_32k"; 124 }; 125 126 osc_24m: clock-osc-24m { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <24000000>; 130 clock-output-names = "osc_24m"; 131 }; 132 133 clk_ext1: clock-ext1 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <133000000>; 137 clock-output-names = "clk_ext1"; 138 }; 139 140 clk_ext2: clock-ext2 { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <133000000>; 144 clock-output-names = "clk_ext2"; 145 }; 146 147 clk_ext3: clock-ext3 { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 clock-frequency = <133000000>; 151 clock-output-names = "clk_ext3"; 152 }; 153 154 clk_ext4: clock-ext4 { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 clock-frequency= <133000000>; 158 clock-output-names = "clk_ext4"; 159 }; 160 161 gic: interrupt-controller@38800000 { 162 compatible = "arm,gic-v3"; 163 reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ 164 <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 165 #interrupt-cells = <3>; 166 interrupt-controller; 167 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 168 }; 169 170 psci { 171 compatible = "arm,psci-1.0"; 172 method = "smc"; 173 }; 174 175 pmu { 176 compatible = "arm,armv8-pmuv3"; 177 interrupts = <GIC_PPI 7 178 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 179 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 180 }; 181 182 timer { 183 compatible = "arm,armv8-timer"; 184 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 185 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 186 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 187 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 188 clock-frequency = <8000000>; 189 arm,no-tick-in-suspend; 190 }; 191 192 soc { 193 compatible = "simple-bus"; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges = <0x0 0x0 0x0 0x3e000000>; 197 198 aips1: bus@30000000 { 199 compatible = "fsl,aips-bus", "simple-bus"; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 ranges; 203 204 gpio1: gpio@30200000 { 205 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 206 reg = <0x30200000 0x10000>; 207 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 209 gpio-controller; 210 #gpio-cells = <2>; 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 }; 214 215 gpio2: gpio@30210000 { 216 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 217 reg = <0x30210000 0x10000>; 218 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 }; 225 226 gpio3: gpio@30220000 { 227 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 228 reg = <0x30220000 0x10000>; 229 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 231 gpio-controller; 232 #gpio-cells = <2>; 233 interrupt-controller; 234 #interrupt-cells = <2>; 235 }; 236 237 gpio4: gpio@30230000 { 238 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 239 reg = <0x30230000 0x10000>; 240 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 242 gpio-controller; 243 #gpio-cells = <2>; 244 interrupt-controller; 245 #interrupt-cells = <2>; 246 }; 247 248 gpio5: gpio@30240000 { 249 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 250 reg = <0x30240000 0x10000>; 251 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 }; 258 259 wdog1: watchdog@30280000 { 260 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 261 reg = <0x30280000 0x10000>; 262 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 264 status = "disabled"; 265 }; 266 267 wdog2: watchdog@30290000 { 268 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 269 reg = <0x30290000 0x10000>; 270 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 272 status = "disabled"; 273 }; 274 275 wdog3: watchdog@302a0000 { 276 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 277 reg = <0x302a0000 0x10000>; 278 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 280 status = "disabled"; 281 }; 282 283 sdma2: dma-controller@302c0000 { 284 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 285 reg = <0x302c0000 0x10000>; 286 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 288 <&clk IMX8MM_CLK_SDMA2_ROOT>; 289 clock-names = "ipg", "ahb"; 290 #dma-cells = <3>; 291 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 292 }; 293 294 sdma3: dma-controller@302b0000 { 295 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 296 reg = <0x302b0000 0x10000>; 297 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 299 <&clk IMX8MM_CLK_SDMA3_ROOT>; 300 clock-names = "ipg", "ahb"; 301 #dma-cells = <3>; 302 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 303 }; 304 305 iomuxc: pinctrl@30330000 { 306 compatible = "fsl,imx8mm-iomuxc"; 307 reg = <0x30330000 0x10000>; 308 }; 309 310 gpr: iomuxc-gpr@30340000 { 311 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; 312 reg = <0x30340000 0x10000>; 313 }; 314 315 ocotp: ocotp-ctrl@30350000 { 316 compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon"; 317 reg = <0x30350000 0x10000>; 318 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 319 /* For nvmem subnodes */ 320 #address-cells = <1>; 321 #size-cells = <1>; 322 }; 323 324 anatop: anatop@30360000 { 325 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; 326 reg = <0x30360000 0x10000>; 327 }; 328 329 snvs: snvs@30370000 { 330 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 331 reg = <0x30370000 0x10000>; 332 333 snvs_rtc: snvs-rtc-lp { 334 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 335 regmap = <&snvs>; 336 offset = <0x34>; 337 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 339 }; 340 341 snvs_pwrkey: snvs-powerkey { 342 compatible = "fsl,sec-v4.0-pwrkey"; 343 regmap = <&snvs>; 344 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 345 linux,keycode = <KEY_POWER>; 346 wakeup-source; 347 }; 348 }; 349 350 clk: clock-controller@30380000 { 351 compatible = "fsl,imx8mm-ccm"; 352 reg = <0x30380000 0x10000>; 353 #clock-cells = <1>; 354 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 355 <&clk_ext3>, <&clk_ext4>; 356 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 357 "clk_ext3", "clk_ext4"; 358 }; 359 360 src: reset-controller@30390000 { 361 compatible = "fsl,imx8mm-src", "syscon"; 362 reg = <0x30390000 0x10000>; 363 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 364 #reset-cells = <1>; 365 }; 366 }; 367 368 aips2: bus@30400000 { 369 compatible = "fsl,aips-bus", "simple-bus"; 370 #address-cells = <1>; 371 #size-cells = <1>; 372 ranges; 373 374 pwm1: pwm@30660000 { 375 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 376 reg = <0x30660000 0x10000>; 377 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 379 <&clk IMX8MM_CLK_PWM1_ROOT>; 380 clock-names = "ipg", "per"; 381 #pwm-cells = <2>; 382 status = "disabled"; 383 }; 384 385 pwm2: pwm@30670000 { 386 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 387 reg = <0x30670000 0x10000>; 388 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 390 <&clk IMX8MM_CLK_PWM2_ROOT>; 391 clock-names = "ipg", "per"; 392 #pwm-cells = <2>; 393 status = "disabled"; 394 }; 395 396 pwm3: pwm@30680000 { 397 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 398 reg = <0x30680000 0x10000>; 399 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 401 <&clk IMX8MM_CLK_PWM3_ROOT>; 402 clock-names = "ipg", "per"; 403 #pwm-cells = <2>; 404 status = "disabled"; 405 }; 406 407 pwm4: pwm@30690000 { 408 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 409 reg = <0x30690000 0x10000>; 410 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 412 <&clk IMX8MM_CLK_PWM4_ROOT>; 413 clock-names = "ipg", "per"; 414 #pwm-cells = <2>; 415 status = "disabled"; 416 }; 417 }; 418 419 aips3: bus@30800000 { 420 compatible = "fsl,aips-bus", "simple-bus"; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 ranges; 424 425 ecspi1: spi@30820000 { 426 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <0x30820000 0x10000>; 430 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 432 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 433 clock-names = "ipg", "per"; 434 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 ecspi2: spi@30830000 { 440 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 reg = <0x30830000 0x10000>; 444 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 446 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 447 clock-names = "ipg", "per"; 448 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 449 dma-names = "rx", "tx"; 450 status = "disabled"; 451 }; 452 453 ecspi3: spi@30840000 { 454 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <0x30840000 0x10000>; 458 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 460 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 461 clock-names = "ipg", "per"; 462 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 463 dma-names = "rx", "tx"; 464 status = "disabled"; 465 }; 466 467 uart1: serial@30860000 { 468 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 469 reg = <0x30860000 0x10000>; 470 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 472 <&clk IMX8MM_CLK_UART1_ROOT>; 473 clock-names = "ipg", "per"; 474 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 uart3: serial@30880000 { 480 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 481 reg = <0x30880000 0x10000>; 482 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 484 <&clk IMX8MM_CLK_UART3_ROOT>; 485 clock-names = "ipg", "per"; 486 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 487 dma-names = "rx", "tx"; 488 status = "disabled"; 489 }; 490 491 uart2: serial@30890000 { 492 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 493 reg = <0x30890000 0x10000>; 494 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 496 <&clk IMX8MM_CLK_UART2_ROOT>; 497 clock-names = "ipg", "per"; 498 status = "disabled"; 499 }; 500 501 i2c1: i2c@30a20000 { 502 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 reg = <0x30a20000 0x10000>; 506 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 508 status = "disabled"; 509 }; 510 511 i2c2: i2c@30a30000 { 512 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0x30a30000 0x10000>; 516 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 518 status = "disabled"; 519 }; 520 521 i2c3: i2c@30a40000 { 522 #address-cells = <1>; 523 #size-cells = <0>; 524 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 525 reg = <0x30a40000 0x10000>; 526 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 528 status = "disabled"; 529 }; 530 531 i2c4: i2c@30a50000 { 532 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0x30a50000 0x10000>; 536 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 538 status = "disabled"; 539 }; 540 541 uart4: serial@30a60000 { 542 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 543 reg = <0x30a60000 0x10000>; 544 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 546 <&clk IMX8MM_CLK_UART4_ROOT>; 547 clock-names = "ipg", "per"; 548 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 549 dma-names = "rx", "tx"; 550 status = "disabled"; 551 }; 552 553 usdhc1: mmc@30b40000 { 554 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 555 reg = <0x30b40000 0x10000>; 556 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&clk IMX8MM_CLK_DUMMY>, 558 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 559 <&clk IMX8MM_CLK_USDHC1_ROOT>; 560 clock-names = "ipg", "ahb", "per"; 561 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 562 assigned-clock-rates = <400000000>; 563 fsl,tuning-start-tap = <20>; 564 fsl,tuning-step= <2>; 565 bus-width = <4>; 566 status = "disabled"; 567 }; 568 569 usdhc2: mmc@30b50000 { 570 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 571 reg = <0x30b50000 0x10000>; 572 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&clk IMX8MM_CLK_DUMMY>, 574 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 575 <&clk IMX8MM_CLK_USDHC2_ROOT>; 576 clock-names = "ipg", "ahb", "per"; 577 fsl,tuning-start-tap = <20>; 578 fsl,tuning-step= <2>; 579 bus-width = <4>; 580 status = "disabled"; 581 }; 582 583 usdhc3: mmc@30b60000 { 584 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 585 reg = <0x30b60000 0x10000>; 586 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&clk IMX8MM_CLK_DUMMY>, 588 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 589 <&clk IMX8MM_CLK_USDHC3_ROOT>; 590 clock-names = "ipg", "ahb", "per"; 591 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 592 assigned-clock-rates = <400000000>; 593 fsl,tuning-start-tap = <20>; 594 fsl,tuning-step= <2>; 595 bus-width = <4>; 596 status = "disabled"; 597 }; 598 599 sdma1: dma-controller@30bd0000 { 600 compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; 601 reg = <0x30bd0000 0x10000>; 602 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 604 <&clk IMX8MM_CLK_SDMA1_ROOT>; 605 clock-names = "ipg", "ahb"; 606 #dma-cells = <3>; 607 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 608 }; 609 610 fec1: ethernet@30be0000 { 611 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; 612 reg = <0x30be0000 0x10000>; 613 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 617 <&clk IMX8MM_CLK_ENET1_ROOT>, 618 <&clk IMX8MM_CLK_ENET_TIMER>, 619 <&clk IMX8MM_CLK_ENET_REF>, 620 <&clk IMX8MM_CLK_ENET_PHY_REF>; 621 clock-names = "ipg", "ahb", "ptp", 622 "enet_clk_ref", "enet_out"; 623 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 624 <&clk IMX8MM_CLK_ENET_TIMER>, 625 <&clk IMX8MM_CLK_ENET_REF>, 626 <&clk IMX8MM_CLK_ENET_TIMER>; 627 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 628 <&clk IMX8MM_SYS_PLL2_100M>, 629 <&clk IMX8MM_SYS_PLL2_125M>; 630 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 631 fsl,num-tx-queues = <3>; 632 fsl,num-rx-queues = <3>; 633 status = "disabled"; 634 }; 635 636 }; 637 638 aips4: bus@32c00000 { 639 compatible = "fsl,aips-bus", "simple-bus"; 640 #address-cells = <1>; 641 #size-cells = <1>; 642 ranges; 643 644 usbotg1: usb@32e40000 { 645 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 646 reg = <0x32e40000 0x200>; 647 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 649 clock-names = "usb1_ctrl_root_clk"; 650 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, 651 <&clk IMX8MM_CLK_USB_CORE_REF>; 652 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, 653 <&clk IMX8MM_SYS_PLL1_100M>; 654 fsl,usbphy = <&usbphynop1>; 655 fsl,usbmisc = <&usbmisc1 0>; 656 status = "disabled"; 657 }; 658 659 usbphynop1: usbphynop1 { 660 compatible = "usb-nop-xceiv"; 661 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 662 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 663 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 664 clock-names = "main_clk"; 665 }; 666 667 usbmisc1: usbmisc@32e40200 { 668 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 669 #index-cells = <1>; 670 reg = <0x32e40200 0x200>; 671 }; 672 673 usbotg2: usb@32e50000 { 674 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 675 reg = <0x32e50000 0x200>; 676 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 678 clock-names = "usb1_ctrl_root_clk"; 679 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, 680 <&clk IMX8MM_CLK_USB_CORE_REF>; 681 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, 682 <&clk IMX8MM_SYS_PLL1_100M>; 683 fsl,usbphy = <&usbphynop2>; 684 fsl,usbmisc = <&usbmisc2 0>; 685 status = "disabled"; 686 }; 687 688 usbphynop2: usbphynop2 { 689 compatible = "usb-nop-xceiv"; 690 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 691 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 692 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 693 clock-names = "main_clk"; 694 }; 695 696 usbmisc2: usbmisc@32e50200 { 697 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 698 #index-cells = <1>; 699 reg = <0x32e50200 0x200>; 700 }; 701 702 }; 703 704 dma_apbh: dma-controller@33000000 { 705 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 706 reg = <0x33000000 0x2000>; 707 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 711 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 712 #dma-cells = <1>; 713 dma-channels = <4>; 714 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 715 }; 716 717 gpmi: nand-controller@33002000{ 718 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 719 #address-cells = <1>; 720 #size-cells = <1>; 721 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 722 reg-names = "gpmi-nand", "bch"; 723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-names = "bch"; 725 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 726 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 727 clock-names = "gpmi_io", "gpmi_bch_apb"; 728 dmas = <&dma_apbh 0>; 729 dma-names = "rx-tx"; 730 status = "disabled"; 731 }; 732 }; 733}; 734