1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9#include "imx8mm-overdrive.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 aliases { 17 rtc0 = &rtc_i2c; 18 rtc1 = &snvs_rtc; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 brightness-levels = <0 45 63 88 119 158 203 255>; 24 default-brightness-level = <4>; 25 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 26 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 29 power-supply = <®_3p3v>; 30 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 31 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 32 status = "disabled"; 33 }; 34 35 /* Fixed clock dedicated to SPI CAN controller */ 36 clk40m: oscillator { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <40000000>; 40 }; 41 42 gpio-keys { 43 compatible = "gpio-keys"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_gpio_keys>; 46 47 key-wakeup { 48 debounce-interval = <10>; 49 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 50 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 51 label = "Wake-Up"; 52 linux,code = <KEY_WAKEUP>; 53 wakeup-source; 54 }; 55 }; 56 57 hdmi_connector: hdmi-connector { 58 compatible = "hdmi-connector"; 59 ddc-i2c-bus = <&i2c2>; 60 /* Verdin PWM_3_DSI (SODIMM 19) */ 61 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 62 label = "hdmi"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 65 type = "a"; 66 status = "disabled"; 67 }; 68 69 panel_lvds: panel-lvds { 70 compatible = "panel-lvds"; 71 backlight = <&backlight>; 72 data-mapping = "vesa-24"; 73 status = "disabled"; 74 }; 75 76 /* Carrier Board Supplies */ 77 reg_1p8v: regulator-1p8v { 78 compatible = "regulator-fixed"; 79 regulator-max-microvolt = <1800000>; 80 regulator-min-microvolt = <1800000>; 81 regulator-name = "+V1.8_SW"; 82 }; 83 84 reg_3p3v: regulator-3p3v { 85 compatible = "regulator-fixed"; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "+V3.3_SW"; 89 }; 90 91 reg_5p0v: regulator-5p0v { 92 compatible = "regulator-fixed"; 93 regulator-max-microvolt = <5000000>; 94 regulator-min-microvolt = <5000000>; 95 regulator-name = "+V5_SW"; 96 }; 97 98 /* Non PMIC On-module Supplies */ 99 reg_ethphy: regulator-ethphy { 100 compatible = "regulator-fixed"; 101 enable-active-high; 102 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 103 off-on-delay-us = <500000>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_reg_eth>; 106 regulator-always-on; 107 regulator-boot-on; 108 regulator-max-microvolt = <3300000>; 109 regulator-min-microvolt = <3300000>; 110 regulator-name = "On-module +V3.3_ETH"; 111 startup-delay-us = <200000>; 112 }; 113 114 /* 115 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 116 * peripherals on the carrier board powered. 117 * If more granularity or power saving is required this can be disabled 118 * in the carrier board device tree files. 119 */ 120 reg_force_sleep_moci: regulator-force-sleep-moci { 121 compatible = "regulator-fixed"; 122 enable-active-high; 123 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 124 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 125 regulator-always-on; 126 regulator-boot-on; 127 regulator-name = "CTRL_SLEEP_MOCI#"; 128 }; 129 130 reg_usb_otg1_vbus: regulator-usb-otg1 { 131 compatible = "regulator-fixed"; 132 enable-active-high; 133 /* Verdin USB_1_EN (SODIMM 155) */ 134 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_reg_usb1_en>; 137 regulator-max-microvolt = <5000000>; 138 regulator-min-microvolt = <5000000>; 139 regulator-name = "USB_1_EN"; 140 }; 141 142 reg_usb_otg2_vbus: regulator-usb-otg2 { 143 compatible = "regulator-fixed"; 144 enable-active-high; 145 /* Verdin USB_2_EN (SODIMM 185) */ 146 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_reg_usb2_en>; 149 regulator-max-microvolt = <5000000>; 150 regulator-min-microvolt = <5000000>; 151 regulator-name = "USB_2_EN"; 152 }; 153 154 reg_usdhc2_vmmc: regulator-usdhc2 { 155 compatible = "regulator-fixed"; 156 enable-active-high; 157 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 158 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 159 off-on-delay-us = <100000>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 162 regulator-max-microvolt = <3300000>; 163 regulator-min-microvolt = <3300000>; 164 regulator-name = "+V3.3_SD"; 165 startup-delay-us = <2000>; 166 }; 167 168 reserved-memory { 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 /* Use the kernel configuration settings instead */ 174 /delete-node/ linux,cma; 175 }; 176}; 177 178&A53_0 { 179 cpu-supply = <®_vdd_arm>; 180}; 181 182&A53_1 { 183 cpu-supply = <®_vdd_arm>; 184}; 185 186&A53_2 { 187 cpu-supply = <®_vdd_arm>; 188}; 189 190&A53_3 { 191 cpu-supply = <®_vdd_arm>; 192}; 193 194&cpu_alert0 { 195 temperature = <95000>; 196}; 197 198&cpu_crit0 { 199 temperature = <105000>; 200}; 201 202&ddrc { 203 operating-points-v2 = <&ddrc_opp_table>; 204 205 ddrc_opp_table: opp-table { 206 compatible = "operating-points-v2"; 207 208 opp-25000000 { 209 opp-hz = /bits/ 64 <25000000>; 210 }; 211 212 opp-100000000 { 213 opp-hz = /bits/ 64 <100000000>; 214 }; 215 216 opp-750000000 { 217 opp-hz = /bits/ 64 <750000000>; 218 }; 219 }; 220}; 221 222/* Verdin SPI_1 */ 223&ecspi2 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_ecspi2>; 229}; 230 231/* Verdin CAN_1 (On-module) */ 232&ecspi3 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_ecspi3>; 238 status = "okay"; 239 240 can1: can@0 { 241 compatible = "microchip,mcp251xfd"; 242 clocks = <&clk40m>; 243 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_can1_int>; 246 reg = <0>; 247 spi-max-frequency = <8500000>; 248 }; 249}; 250 251/* Verdin ETH_1 (On-module PHY) */ 252&fec1 { 253 fsl,magic-packet; 254 phy-handle = <ðphy0>; 255 phy-mode = "rgmii-id"; 256 phy-supply = <®_ethphy>; 257 pinctrl-names = "default", "sleep"; 258 pinctrl-0 = <&pinctrl_fec1>; 259 pinctrl-1 = <&pinctrl_fec1_sleep>; 260 261 mdio { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 ethphy0: ethernet-phy@7 { 266 compatible = "ethernet-phy-ieee802.3-c22"; 267 interrupt-parent = <&gpio1>; 268 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 269 micrel,led-mode = <0>; 270 reg = <7>; 271 }; 272 }; 273}; 274 275/* Verdin QSPI_1 */ 276&flexspi { 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pinctrl_flexspi0>; 279}; 280 281&gpio1 { 282 gpio-line-names = "SODIMM_216", 283 "SODIMM_19", 284 "", 285 "", 286 "", 287 "", 288 "", 289 "", 290 "SODIMM_220", 291 "SODIMM_222", 292 "", 293 "SODIMM_218", 294 "SODIMM_155", 295 "SODIMM_157", 296 "SODIMM_185", 297 "SODIMM_187"; 298}; 299 300&gpio2 { 301 gpio-line-names = "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "", 310 "", 311 "", 312 "", 313 "SODIMM_84", 314 "SODIMM_78", 315 "SODIMM_74", 316 "SODIMM_80", 317 "SODIMM_82", 318 "SODIMM_70", 319 "SODIMM_72"; 320}; 321 322&gpio5 { 323 gpio-line-names = "SODIMM_131", 324 "", 325 "SODIMM_91", 326 "SODIMM_16", 327 "SODIMM_15", 328 "SODIMM_208", 329 "SODIMM_137", 330 "SODIMM_139", 331 "SODIMM_141", 332 "SODIMM_143", 333 "SODIMM_196", 334 "SODIMM_200", 335 "SODIMM_198", 336 "SODIMM_202", 337 "", 338 "", 339 "SODIMM_55", 340 "SODIMM_53", 341 "SODIMM_95", 342 "SODIMM_93", 343 "SODIMM_14", 344 "SODIMM_12", 345 "", 346 "", 347 "", 348 "", 349 "SODIMM_210", 350 "SODIMM_212", 351 "SODIMM_151", 352 "SODIMM_153"; 353}; 354 355/* On-module I2C */ 356&i2c1 { 357 clock-frequency = <400000>; 358 pinctrl-names = "default", "gpio"; 359 pinctrl-0 = <&pinctrl_i2c1>; 360 pinctrl-1 = <&pinctrl_i2c1_gpio>; 361 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 362 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 363 status = "okay"; 364 365 pca9450: pmic@25 { 366 compatible = "nxp,pca9450a"; 367 interrupt-parent = <&gpio1>; 368 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 369 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_pmic>; 372 reg = <0x25>; 373 374 /* 375 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 376 * behind this PMIC. 377 */ 378 379 regulators { 380 reg_vdd_soc: BUCK1 { 381 nxp,dvs-run-voltage = <850000>; 382 nxp,dvs-standby-voltage = <800000>; 383 regulator-always-on; 384 regulator-boot-on; 385 regulator-max-microvolt = <850000>; 386 regulator-min-microvolt = <800000>; 387 regulator-name = "On-module +VDD_SOC (BUCK1)"; 388 regulator-ramp-delay = <3125>; 389 }; 390 391 reg_vdd_arm: BUCK2 { 392 nxp,dvs-run-voltage = <950000>; 393 nxp,dvs-standby-voltage = <850000>; 394 regulator-always-on; 395 regulator-boot-on; 396 regulator-max-microvolt = <1050000>; 397 regulator-min-microvolt = <805000>; 398 regulator-name = "On-module +VDD_ARM (BUCK2)"; 399 regulator-ramp-delay = <3125>; 400 }; 401 402 reg_vdd_dram: BUCK3 { 403 regulator-always-on; 404 regulator-boot-on; 405 regulator-max-microvolt = <1000000>; 406 regulator-min-microvolt = <805000>; 407 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 408 }; 409 410 reg_vdd_3v3: BUCK4 { 411 regulator-always-on; 412 regulator-boot-on; 413 regulator-max-microvolt = <3300000>; 414 regulator-min-microvolt = <3300000>; 415 regulator-name = "On-module +V3.3 (BUCK4)"; 416 }; 417 418 reg_vdd_1v8: BUCK5 { 419 regulator-always-on; 420 regulator-boot-on; 421 regulator-max-microvolt = <1800000>; 422 regulator-min-microvolt = <1800000>; 423 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 424 }; 425 426 reg_nvcc_dram: BUCK6 { 427 regulator-always-on; 428 regulator-boot-on; 429 regulator-max-microvolt = <1100000>; 430 regulator-min-microvolt = <1100000>; 431 regulator-name = "On-module +VDD_DDR (BUCK6)"; 432 }; 433 434 reg_nvcc_snvs: LDO1 { 435 regulator-always-on; 436 regulator-boot-on; 437 regulator-max-microvolt = <1800000>; 438 regulator-min-microvolt = <1800000>; 439 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 440 }; 441 442 reg_vdd_snvs: LDO2 { 443 regulator-always-on; 444 regulator-boot-on; 445 regulator-max-microvolt = <800000>; 446 regulator-min-microvolt = <800000>; 447 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 448 }; 449 450 reg_vdda: LDO3 { 451 regulator-always-on; 452 regulator-boot-on; 453 regulator-max-microvolt = <1800000>; 454 regulator-min-microvolt = <1800000>; 455 regulator-name = "On-module +V1.8A (LDO3)"; 456 }; 457 458 reg_vdd_phy: LDO4 { 459 regulator-always-on; 460 regulator-boot-on; 461 regulator-max-microvolt = <900000>; 462 regulator-min-microvolt = <900000>; 463 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 464 }; 465 466 reg_nvcc_sd: LDO5 { 467 regulator-max-microvolt = <3300000>; 468 regulator-min-microvolt = <1800000>; 469 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 470 }; 471 }; 472 }; 473 474 rtc_i2c: rtc@32 { 475 compatible = "epson,rx8130"; 476 reg = <0x32>; 477 }; 478 479 adc@49 { 480 compatible = "ti,ads1015"; 481 reg = <0x49>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 485 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 486 channel@0 { 487 reg = <0>; 488 ti,datarate = <4>; 489 ti,gain = <2>; 490 }; 491 492 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 493 channel@1 { 494 reg = <1>; 495 ti,datarate = <4>; 496 ti,gain = <2>; 497 }; 498 499 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 500 channel@2 { 501 reg = <2>; 502 ti,datarate = <4>; 503 ti,gain = <2>; 504 }; 505 506 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 507 channel@3 { 508 reg = <3>; 509 ti,datarate = <4>; 510 ti,gain = <2>; 511 }; 512 513 /* Verdin I2C_1 ADC_4 */ 514 channel@4 { 515 reg = <4>; 516 ti,datarate = <4>; 517 ti,gain = <2>; 518 }; 519 520 /* Verdin I2C_1 ADC_3 */ 521 channel@5 { 522 reg = <5>; 523 ti,datarate = <4>; 524 ti,gain = <2>; 525 }; 526 527 /* Verdin I2C_1 ADC_2 */ 528 channel@6 { 529 reg = <6>; 530 ti,datarate = <4>; 531 ti,gain = <2>; 532 }; 533 534 /* Verdin I2C_1 ADC_1 */ 535 channel@7 { 536 reg = <7>; 537 ti,datarate = <4>; 538 ti,gain = <2>; 539 }; 540 }; 541 542 eeprom@50 { 543 compatible = "st,24c02"; 544 pagesize = <16>; 545 reg = <0x50>; 546 }; 547}; 548 549/* Verdin I2C_2_DSI */ 550&i2c2 { 551 clock-frequency = <10000>; 552 pinctrl-names = "default", "gpio"; 553 pinctrl-0 = <&pinctrl_i2c2>; 554 pinctrl-1 = <&pinctrl_i2c2_gpio>; 555 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 556 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 557 status = "disabled"; 558}; 559 560/* Verdin I2C_3_HDMI N/A */ 561 562/* Verdin I2C_4_CSI */ 563&i2c3 { 564 clock-frequency = <400000>; 565 pinctrl-names = "default", "gpio"; 566 pinctrl-0 = <&pinctrl_i2c3>; 567 pinctrl-1 = <&pinctrl_i2c3_gpio>; 568 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 570}; 571 572/* Verdin I2C_1 */ 573&i2c4 { 574 clock-frequency = <400000>; 575 pinctrl-names = "default", "gpio"; 576 pinctrl-0 = <&pinctrl_i2c4>; 577 pinctrl-1 = <&pinctrl_i2c4_gpio>; 578 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 579 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 580 581 gpio_expander_21: gpio-expander@21 { 582 compatible = "nxp,pcal6416"; 583 #gpio-cells = <2>; 584 gpio-controller; 585 reg = <0x21>; 586 vcc-supply = <®_3p3v>; 587 status = "disabled"; 588 }; 589 590 lvds_ti_sn65dsi84: bridge@2c { 591 compatible = "ti,sn65dsi84"; 592 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 593 /* Verdin GPIO_10_DSI (SODIMM 21) */ 594 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 597 reg = <0x2c>; 598 status = "disabled"; 599 }; 600 601 /* Current measurement into module VCC */ 602 hwmon: hwmon@40 { 603 compatible = "ti,ina219"; 604 reg = <0x40>; 605 shunt-resistor = <10000>; 606 status = "disabled"; 607 }; 608 609 hdmi_lontium_lt8912: hdmi@48 { 610 compatible = "lontium,lt8912b"; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 613 reg = <0x48>; 614 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 615 /* Verdin GPIO_10_DSI (SODIMM 21) */ 616 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 617 status = "disabled"; 618 }; 619 620 atmel_mxt_ts: touch@4a { 621 compatible = "atmel,maxtouch"; 622 /* 623 * Verdin GPIO_9_DSI 624 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 625 */ 626 interrupt-parent = <&gpio3>; 627 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 630 reg = <0x4a>; 631 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 632 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 633 status = "disabled"; 634 }; 635 636 /* Temperature sensor on carrier board */ 637 hwmon_temp: sensor@4f { 638 compatible = "ti,tmp75c"; 639 reg = <0x4f>; 640 status = "disabled"; 641 }; 642 643 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 644 eeprom_display_adapter: eeprom@50 { 645 compatible = "st,24c02"; 646 pagesize = <16>; 647 reg = <0x50>; 648 status = "disabled"; 649 }; 650 651 /* EEPROM on carrier board */ 652 eeprom_carrier_board: eeprom@57 { 653 compatible = "st,24c02"; 654 pagesize = <16>; 655 reg = <0x57>; 656 status = "disabled"; 657 }; 658}; 659 660/* Verdin PCIE_1 */ 661&pcie0 { 662 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 663 <&clk IMX8MM_CLK_PCIE1_CTRL>; 664 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 665 <&clk IMX8MM_SYS_PLL2_250M>; 666 assigned-clock-rates = <10000000>, <250000000>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_pcie0>; 669 /* PCIE_1_RESET# (SODIMM 244) */ 670 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 671}; 672 673&pcie_phy { 674 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 675 clock-names = "ref"; 676 fsl,clkreq-unsupported; 677 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 678 fsl,tx-deemph-gen1 = <0x2d>; 679 fsl,tx-deemph-gen2 = <0xf>; 680}; 681 682/* Verdin PWM_3_DSI */ 683&pwm1 { 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pinctrl_pwm_1>; 686 #pwm-cells = <3>; 687}; 688 689/* Verdin PWM_1 */ 690&pwm2 { 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_pwm_2>; 693 #pwm-cells = <3>; 694}; 695 696/* Verdin PWM_2 */ 697&pwm3 { 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pinctrl_pwm_3>; 700 #pwm-cells = <3>; 701}; 702 703/* Verdin I2S_1 */ 704&sai2 { 705 #sound-dai-cells = <0>; 706 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 707 assigned-clock-rates = <24576000>; 708 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pinctrl_sai2>; 711}; 712 713&snvs_pwrkey { 714 status = "okay"; 715}; 716 717/* Verdin UART_3, used as the Linux console */ 718&uart1 { 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_uart1>; 721}; 722 723/* Verdin UART_1 */ 724&uart2 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&pinctrl_uart2>; 727 uart-has-rtscts; 728}; 729 730/* Verdin UART_2 */ 731&uart3 { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_uart3>; 734 uart-has-rtscts; 735}; 736 737/* 738 * Verdin UART_4 739 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 740 */ 741&uart4 { 742 pinctrl-names = "default"; 743 pinctrl-0 = <&pinctrl_uart4>; 744}; 745 746/* Verdin USB_1 */ 747&usbotg1 { 748 adp-disable; 749 dr_mode = "otg"; 750 hnp-disable; 751 samsung,picophy-dc-vol-level-adjust = <7>; 752 samsung,picophy-pre-emp-curr-control = <3>; 753 srp-disable; 754 vbus-supply = <®_usb_otg1_vbus>; 755}; 756 757/* Verdin USB_2 */ 758&usbotg2 { 759 dr_mode = "host"; 760 samsung,picophy-dc-vol-level-adjust = <7>; 761 samsung,picophy-pre-emp-curr-control = <3>; 762 vbus-supply = <®_usb_otg2_vbus>; 763}; 764 765&usbphynop1 { 766 vcc-supply = <®_vdd_3v3>; 767}; 768 769&usbphynop2 { 770 power-domains = <&pgc_otg2>; 771 vcc-supply = <®_vdd_3v3>; 772}; 773 774/* On-module eMMC */ 775&usdhc1 { 776 bus-width = <8>; 777 keep-power-in-suspend; 778 non-removable; 779 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 780 pinctrl-0 = <&pinctrl_usdhc1>; 781 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 782 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 783 status = "okay"; 784}; 785 786/* Verdin SD_1 */ 787&usdhc2 { 788 bus-width = <4>; 789 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 790 disable-wp; 791 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 792 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 793 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 794 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 795 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 796 vmmc-supply = <®_usdhc2_vmmc>; 797}; 798 799&wdog1 { 800 fsl,ext-reset-output; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&pinctrl_wdog>; 803 status = "okay"; 804}; 805 806&iomuxc { 807 pinctrl-names = "default"; 808 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 809 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 810 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 811 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 812 <&pinctrl_pmic_tpm_ena>; 813 814 pinctrl_can1_int: can1intgrp { 815 fsl,pins = 816 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 817 }; 818 819 pinctrl_can2_int: can2intgrp { 820 fsl,pins = 821 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 822 }; 823 824 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 825 fsl,pins = 826 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 827 }; 828 829 pinctrl_ecspi2: ecspi2grp { 830 fsl,pins = 831 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 832 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 833 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 834 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 835 }; 836 837 pinctrl_ecspi3: ecspi3grp { 838 fsl,pins = 839 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 840 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 841 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 842 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 843 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 844 }; 845 846 pinctrl_fec1: fec1grp { 847 fsl,pins = 848 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 849 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 850 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 851 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 852 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 853 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 854 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 855 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 856 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 857 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 858 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 859 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 860 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 861 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 862 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 863 }; 864 865 pinctrl_fec1_sleep: fec1-sleepgrp { 866 fsl,pins = 867 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 868 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 869 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 870 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 871 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 872 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 873 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 874 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 875 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 876 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 877 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 878 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 879 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 880 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 881 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 882 }; 883 884 pinctrl_flexspi0: flexspi0grp { 885 fsl,pins = 886 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 887 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 888 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 889 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 890 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 891 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 892 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 893 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 894 }; 895 896 pinctrl_gpio1: gpio1grp { 897 fsl,pins = 898 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 899 }; 900 901 pinctrl_gpio2: gpio2grp { 902 fsl,pins = 903 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 904 }; 905 906 pinctrl_gpio3: gpio3grp { 907 fsl,pins = 908 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 909 }; 910 911 pinctrl_gpio4: gpio4grp { 912 fsl,pins = 913 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 914 }; 915 916 pinctrl_gpio5: gpio5grp { 917 fsl,pins = 918 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 919 }; 920 921 pinctrl_gpio6: gpio6grp { 922 fsl,pins = 923 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 924 }; 925 926 pinctrl_gpio7: gpio7grp { 927 fsl,pins = 928 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 929 }; 930 931 pinctrl_gpio8: gpio8grp { 932 fsl,pins = 933 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 934 }; 935 936 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 937 pinctrl_gpio_9_dsi: gpio9dsigrp { 938 fsl,pins = 939 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */ 940 }; 941 942 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 943 pinctrl_gpio_10_dsi: gpio10dsigrp { 944 fsl,pins = 945 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 946 }; 947 948 pinctrl_gpio_hog1: gpiohog1grp { 949 fsl,pins = 950 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 951 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 952 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 953 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 954 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 955 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 956 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 957 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 958 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 959 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 960 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 961 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 962 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 963 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 964 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 965 }; 966 967 pinctrl_gpio_hog2: gpiohog2grp { 968 fsl,pins = 969 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 970 }; 971 972 pinctrl_gpio_hog3: gpiohog3grp { 973 fsl,pins = 974 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 975 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 976 }; 977 978 pinctrl_gpio_keys: gpiokeysgrp { 979 fsl,pins = 980 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 981 }; 982 983 /* On-module I2C */ 984 pinctrl_i2c1: i2c1grp { 985 fsl,pins = 986 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 987 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 988 }; 989 990 pinctrl_i2c1_gpio: i2c1gpiogrp { 991 fsl,pins = 992 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 993 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 994 }; 995 996 /* Verdin I2C_4_CSI */ 997 pinctrl_i2c2: i2c2grp { 998 fsl,pins = 999 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 1000 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 1001 }; 1002 1003 pinctrl_i2c2_gpio: i2c2gpiogrp { 1004 fsl,pins = 1005 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1006 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1007 }; 1008 1009 /* Verdin I2C_2_DSI */ 1010 pinctrl_i2c3: i2c3grp { 1011 fsl,pins = 1012 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1013 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1014 }; 1015 1016 pinctrl_i2c3_gpio: i2c3gpiogrp { 1017 fsl,pins = 1018 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1019 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1020 }; 1021 1022 /* Verdin I2C_1 */ 1023 pinctrl_i2c4: i2c4grp { 1024 fsl,pins = 1025 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1026 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1027 }; 1028 1029 pinctrl_i2c4_gpio: i2c4gpiogrp { 1030 fsl,pins = 1031 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1032 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1033 }; 1034 1035 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1036 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1037 fsl,pins = 1038 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1039 }; 1040 1041 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1042 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1043 fsl,pins = 1044 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1045 }; 1046 1047 pinctrl_pcie0: pcie0grp { 1048 fsl,pins = 1049 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1050 /* PMIC_EN_PCIe_CLK, unused */ 1051 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1052 }; 1053 1054 pinctrl_pmic: pmicirqgrp { 1055 fsl,pins = 1056 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1057 }; 1058 1059 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1060 pinctrl_pwm_1: pwm1grp { 1061 fsl,pins = 1062 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1063 }; 1064 1065 pinctrl_pwm_2: pwm2grp { 1066 fsl,pins = 1067 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1068 }; 1069 1070 pinctrl_pwm_3: pwm3grp { 1071 fsl,pins = 1072 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1073 }; 1074 1075 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1076 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1077 fsl,pins = 1078 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1079 }; 1080 1081 pinctrl_reg_eth: regethgrp { 1082 fsl,pins = 1083 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1084 }; 1085 1086 pinctrl_reg_usb1_en: regusb1engrp { 1087 fsl,pins = 1088 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1089 }; 1090 1091 pinctrl_reg_usb2_en: regusb2engrp { 1092 fsl,pins = 1093 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1094 }; 1095 1096 pinctrl_sai2: sai2grp { 1097 fsl,pins = 1098 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1099 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1100 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1101 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1102 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1103 }; 1104 1105 pinctrl_sai5: sai5grp { 1106 fsl,pins = 1107 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1108 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1109 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1110 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1111 }; 1112 1113 /* control signal for optional ATTPM20P or SE050 */ 1114 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1115 fsl,pins = 1116 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1117 }; 1118 1119 pinctrl_tsp: tspgrp { 1120 fsl,pins = 1121 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1122 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1123 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1124 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1125 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1126 }; 1127 1128 pinctrl_uart1: uart1grp { 1129 fsl,pins = 1130 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1131 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1132 }; 1133 1134 pinctrl_uart2: uart2grp { 1135 fsl,pins = 1136 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1137 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1138 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1139 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1140 }; 1141 1142 pinctrl_uart3: uart3grp { 1143 fsl,pins = 1144 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1145 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1146 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1147 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1148 }; 1149 1150 pinctrl_uart4: uart4grp { 1151 fsl,pins = 1152 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1153 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1154 }; 1155 1156 pinctrl_usdhc1: usdhc1grp { 1157 fsl,pins = 1158 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1159 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1160 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1161 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1162 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1163 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1164 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1165 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1166 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1167 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1168 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1169 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1170 }; 1171 1172 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1173 fsl,pins = 1174 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1175 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1176 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1177 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1178 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1179 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1180 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1181 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1182 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1183 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1184 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1185 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1186 }; 1187 1188 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1189 fsl,pins = 1190 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1191 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1192 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1193 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1194 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1195 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1196 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1197 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1198 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1199 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1200 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1201 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1202 }; 1203 1204 pinctrl_usdhc2_cd: usdhc2cdgrp { 1205 fsl,pins = 1206 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1207 }; 1208 1209 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1210 fsl,pins = 1211 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1212 }; 1213 1214 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1215 fsl,pins = 1216 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1217 }; 1218 1219 /* 1220 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1221 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1222 */ 1223 pinctrl_usdhc2: usdhc2grp { 1224 fsl,pins = 1225 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1226 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1227 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1228 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1229 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1230 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1231 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1232 }; 1233 1234 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1235 fsl,pins = 1236 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1237 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1238 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1239 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1240 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1241 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1242 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1243 }; 1244 1245 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1246 fsl,pins = 1247 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1248 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1249 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1250 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1251 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1252 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1253 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1254 }; 1255 1256 /* Avoid backfeeding with removed card power */ 1257 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1258 fsl,pins = 1259 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1260 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1261 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1262 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1263 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1264 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1265 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1266 }; 1267 1268 /* 1269 * On-module Wi-Fi/BT or type specific SDHC interface 1270 * (e.g. on X52 extension slot of Verdin Development Board) 1271 */ 1272 pinctrl_usdhc3: usdhc3grp { 1273 fsl,pins = 1274 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1275 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1276 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1277 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1278 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1279 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1280 }; 1281 1282 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1283 fsl,pins = 1284 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1285 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1286 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1287 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1288 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1289 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1290 }; 1291 1292 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1293 fsl,pins = 1294 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1295 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1296 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1297 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1298 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1299 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1300 }; 1301 1302 pinctrl_wdog: wdoggrp { 1303 fsl,pins = 1304 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1305 }; 1306 1307 pinctrl_wifi_ctrl: wifictrlgrp { 1308 fsl,pins = 1309 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1310 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1311 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1312 }; 1313 1314 pinctrl_wifi_i2s: bti2sgrp { 1315 fsl,pins = 1316 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1317 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1318 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1319 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1320 }; 1321 1322 pinctrl_wifi_pwr_en: wifipwrengrp { 1323 fsl,pins = 1324 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1325 }; 1326}; 1327