1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9#include "imx8mm-overdrive.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 aliases { 17 rtc0 = &rtc_i2c; 18 rtc1 = &snvs_rtc; 19 }; 20 21 /* Fixed clock dedicated to SPI CAN controller */ 22 clk40m: oscillator { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <40000000>; 26 }; 27 28 gpio-keys { 29 compatible = "gpio-keys"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pinctrl_gpio_keys>; 32 33 key-wakeup { 34 debounce-interval = <10>; 35 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 36 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 37 label = "Wake-Up"; 38 linux,code = <KEY_WAKEUP>; 39 wakeup-source; 40 }; 41 }; 42 43 hdmi_connector: hdmi-connector { 44 compatible = "hdmi-connector"; 45 ddc-i2c-bus = <&i2c2>; 46 /* Verdin PWM_3_DSI (SODIMM 19) */ 47 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 48 label = "hdmi"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 51 type = "a"; 52 status = "disabled"; 53 }; 54 55 /* Carrier Board Supplies */ 56 reg_1p8v: regulator-1p8v { 57 compatible = "regulator-fixed"; 58 regulator-max-microvolt = <1800000>; 59 regulator-min-microvolt = <1800000>; 60 regulator-name = "+V1.8_SW"; 61 }; 62 63 reg_3p3v: regulator-3p3v { 64 compatible = "regulator-fixed"; 65 regulator-max-microvolt = <3300000>; 66 regulator-min-microvolt = <3300000>; 67 regulator-name = "+V3.3_SW"; 68 }; 69 70 reg_5p0v: regulator-5p0v { 71 compatible = "regulator-fixed"; 72 regulator-max-microvolt = <5000000>; 73 regulator-min-microvolt = <5000000>; 74 regulator-name = "+V5_SW"; 75 }; 76 77 /* Non PMIC On-module Supplies */ 78 reg_ethphy: regulator-ethphy { 79 compatible = "regulator-fixed"; 80 enable-active-high; 81 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 82 off-on-delay-us = <500000>; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_reg_eth>; 85 regulator-always-on; 86 regulator-boot-on; 87 regulator-max-microvolt = <3300000>; 88 regulator-min-microvolt = <3300000>; 89 regulator-name = "On-module +V3.3_ETH"; 90 startup-delay-us = <200000>; 91 }; 92 93 /* 94 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 95 * peripherals on the carrier board powered. 96 * If more granularity or power saving is required this can be disabled 97 * in the carrier board device tree files. 98 */ 99 reg_force_sleep_moci: regulator-force-sleep-moci { 100 compatible = "regulator-fixed"; 101 enable-active-high; 102 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 103 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 104 regulator-always-on; 105 regulator-boot-on; 106 regulator-name = "CTRL_SLEEP_MOCI#"; 107 }; 108 109 reg_usb_otg1_vbus: regulator-usb-otg1 { 110 compatible = "regulator-fixed"; 111 enable-active-high; 112 /* Verdin USB_1_EN (SODIMM 155) */ 113 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_reg_usb1_en>; 116 regulator-max-microvolt = <5000000>; 117 regulator-min-microvolt = <5000000>; 118 regulator-name = "USB_1_EN"; 119 }; 120 121 reg_usb_otg2_vbus: regulator-usb-otg2 { 122 compatible = "regulator-fixed"; 123 enable-active-high; 124 /* Verdin USB_2_EN (SODIMM 185) */ 125 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_reg_usb2_en>; 128 regulator-max-microvolt = <5000000>; 129 regulator-min-microvolt = <5000000>; 130 regulator-name = "USB_2_EN"; 131 }; 132 133 reg_usdhc2_vmmc: regulator-usdhc2 { 134 compatible = "regulator-fixed"; 135 enable-active-high; 136 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 137 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 138 off-on-delay-us = <100000>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 141 regulator-max-microvolt = <3300000>; 142 regulator-min-microvolt = <3300000>; 143 regulator-name = "+V3.3_SD"; 144 startup-delay-us = <20000>; 145 }; 146 147 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 148 compatible = "regulator-gpio"; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 151 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 152 regulator-max-microvolt = <3300000>; 153 regulator-min-microvolt = <1800000>; 154 states = <1800000 0x1>, 155 <3300000 0x0>; 156 regulator-name = "PMIC_USDHC_VSELECT"; 157 vin-supply = <®_nvcc_sd>; 158 }; 159 160 reserved-memory { 161 #address-cells = <2>; 162 #size-cells = <2>; 163 ranges; 164 165 /* Use the kernel configuration settings instead */ 166 /delete-node/ linux,cma; 167 }; 168}; 169 170&A53_0 { 171 cpu-supply = <®_vdd_arm>; 172}; 173 174&A53_1 { 175 cpu-supply = <®_vdd_arm>; 176}; 177 178&A53_2 { 179 cpu-supply = <®_vdd_arm>; 180}; 181 182&A53_3 { 183 cpu-supply = <®_vdd_arm>; 184}; 185 186&cpu_alert0 { 187 temperature = <95000>; 188}; 189 190&cpu_crit0 { 191 temperature = <105000>; 192}; 193 194&ddrc { 195 operating-points-v2 = <&ddrc_opp_table>; 196 197 ddrc_opp_table: opp-table { 198 compatible = "operating-points-v2"; 199 200 opp-25000000 { 201 opp-hz = /bits/ 64 <25000000>; 202 }; 203 204 opp-100000000 { 205 opp-hz = /bits/ 64 <100000000>; 206 }; 207 208 opp-750000000 { 209 opp-hz = /bits/ 64 <750000000>; 210 }; 211 }; 212}; 213 214/* Verdin SPI_1 */ 215&ecspi2 { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_ecspi2>; 221}; 222 223/* On-module SPI */ 224&ecspi3 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>; 230 status = "okay"; 231 232 /* Verdin CAN_1 */ 233 can1: can@0 { 234 compatible = "microchip,mcp251xfd"; 235 clocks = <&clk40m>; 236 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_can1_int>; 239 reg = <0>; 240 spi-max-frequency = <8500000>; 241 }; 242 243 verdin_som_tpm: tpm@1 { 244 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 245 reg = <0x1>; 246 spi-max-frequency = <36000000>; 247 }; 248}; 249 250/* Verdin ETH_1 (On-module PHY) */ 251&fec1 { 252 fsl,magic-packet; 253 phy-handle = <ðphy0>; 254 phy-mode = "rgmii-id"; 255 phy-supply = <®_ethphy>; 256 pinctrl-names = "default", "sleep"; 257 pinctrl-0 = <&pinctrl_fec1>; 258 pinctrl-1 = <&pinctrl_fec1_sleep>; 259 260 mdio { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 ethphy0: ethernet-phy@7 { 265 compatible = "ethernet-phy-ieee802.3-c22"; 266 interrupt-parent = <&gpio1>; 267 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 268 micrel,led-mode = <0>; 269 reg = <7>; 270 }; 271 }; 272}; 273 274/* Verdin QSPI_1 */ 275&flexspi { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_flexspi0>; 278}; 279 280&gpio1 { 281 gpio-line-names = "SODIMM_216", 282 "SODIMM_19", 283 "", 284 "", 285 "PMIC_USDHC_VSELECT", 286 "", 287 "", 288 "", 289 "SODIMM_220", 290 "SODIMM_222", 291 "", 292 "SODIMM_218", 293 "SODIMM_155", 294 "SODIMM_157", 295 "SODIMM_185", 296 "SODIMM_187"; 297}; 298 299&gpio2 { 300 gpio-line-names = "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "", 310 "", 311 "", 312 "SODIMM_84", 313 "SODIMM_78", 314 "SODIMM_74", 315 "SODIMM_80", 316 "SODIMM_82", 317 "SODIMM_70", 318 "SODIMM_72"; 319}; 320 321&gpio5 { 322 gpio-line-names = "SODIMM_131", 323 "", 324 "SODIMM_91", 325 "SODIMM_16", 326 "SODIMM_15", 327 "SODIMM_208", 328 "SODIMM_137", 329 "SODIMM_139", 330 "SODIMM_141", 331 "SODIMM_143", 332 "SODIMM_196", 333 "SODIMM_200", 334 "SODIMM_198", 335 "SODIMM_202", 336 "", 337 "", 338 "SODIMM_55", 339 "SODIMM_53", 340 "SODIMM_95", 341 "SODIMM_93", 342 "SODIMM_14", 343 "SODIMM_12", 344 "", 345 "", 346 "", 347 "", 348 "SODIMM_210", 349 "SODIMM_212", 350 "SODIMM_151", 351 "SODIMM_153"; 352}; 353 354/* On-module I2C */ 355&i2c1 { 356 clock-frequency = <400000>; 357 pinctrl-names = "default", "gpio"; 358 pinctrl-0 = <&pinctrl_i2c1>; 359 pinctrl-1 = <&pinctrl_i2c1_gpio>; 360 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 361 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 362 single-master; 363 status = "okay"; 364 365 pca9450: pmic@25 { 366 compatible = "nxp,pca9450a"; 367 interrupt-parent = <&gpio1>; 368 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 369 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_pmic>; 372 reg = <0x25>; 373 374 /* 375 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 376 * behind this PMIC. 377 */ 378 379 regulators { 380 reg_vdd_soc: BUCK1 { 381 nxp,dvs-run-voltage = <850000>; 382 nxp,dvs-standby-voltage = <800000>; 383 regulator-always-on; 384 regulator-boot-on; 385 regulator-max-microvolt = <850000>; 386 regulator-min-microvolt = <800000>; 387 regulator-name = "On-module +VDD_SOC (BUCK1)"; 388 regulator-ramp-delay = <3125>; 389 }; 390 391 reg_vdd_arm: BUCK2 { 392 nxp,dvs-run-voltage = <950000>; 393 nxp,dvs-standby-voltage = <850000>; 394 regulator-always-on; 395 regulator-boot-on; 396 regulator-max-microvolt = <1050000>; 397 regulator-min-microvolt = <805000>; 398 regulator-name = "On-module +VDD_ARM (BUCK2)"; 399 regulator-ramp-delay = <3125>; 400 }; 401 402 reg_vdd_dram: BUCK3 { 403 regulator-always-on; 404 regulator-boot-on; 405 regulator-max-microvolt = <1000000>; 406 regulator-min-microvolt = <805000>; 407 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 408 }; 409 410 reg_vdd_3v3: BUCK4 { 411 regulator-always-on; 412 regulator-boot-on; 413 regulator-max-microvolt = <3300000>; 414 regulator-min-microvolt = <3300000>; 415 regulator-name = "On-module +V3.3 (BUCK4)"; 416 }; 417 418 reg_vdd_1v8: BUCK5 { 419 regulator-always-on; 420 regulator-boot-on; 421 regulator-max-microvolt = <1800000>; 422 regulator-min-microvolt = <1800000>; 423 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 424 }; 425 426 reg_nvcc_dram: BUCK6 { 427 regulator-always-on; 428 regulator-boot-on; 429 regulator-max-microvolt = <1100000>; 430 regulator-min-microvolt = <1100000>; 431 regulator-name = "On-module +VDD_DDR (BUCK6)"; 432 }; 433 434 reg_nvcc_snvs: LDO1 { 435 regulator-always-on; 436 regulator-boot-on; 437 regulator-max-microvolt = <1800000>; 438 regulator-min-microvolt = <1800000>; 439 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 440 }; 441 442 reg_vdd_snvs: LDO2 { 443 regulator-always-on; 444 regulator-boot-on; 445 regulator-max-microvolt = <800000>; 446 regulator-min-microvolt = <800000>; 447 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 448 }; 449 450 reg_vdda: LDO3 { 451 regulator-always-on; 452 regulator-boot-on; 453 regulator-max-microvolt = <1800000>; 454 regulator-min-microvolt = <1800000>; 455 regulator-name = "On-module +V1.8A (LDO3)"; 456 }; 457 458 reg_vdd_phy: LDO4 { 459 regulator-always-on; 460 regulator-boot-on; 461 regulator-max-microvolt = <900000>; 462 regulator-min-microvolt = <900000>; 463 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 464 }; 465 466 reg_nvcc_sd: LDO5 { 467 regulator-always-on; 468 regulator-max-microvolt = <3300000>; 469 regulator-min-microvolt = <1800000>; 470 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 471 }; 472 }; 473 }; 474 475 rtc_i2c: rtc@32 { 476 compatible = "epson,rx8130"; 477 reg = <0x32>; 478 }; 479 480 verdin_som_adc: adc@49 { 481 compatible = "ti,ads1015"; 482 reg = <0x49>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 #io-channel-cells = <1>; 486 487 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 488 channel@0 { 489 reg = <0>; 490 ti,datarate = <4>; 491 ti,gain = <2>; 492 }; 493 494 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 495 channel@1 { 496 reg = <1>; 497 ti,datarate = <4>; 498 ti,gain = <2>; 499 }; 500 501 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 502 channel@2 { 503 reg = <2>; 504 ti,datarate = <4>; 505 ti,gain = <2>; 506 }; 507 508 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 509 channel@3 { 510 reg = <3>; 511 ti,datarate = <4>; 512 ti,gain = <2>; 513 }; 514 515 /* Verdin I2C_1 ADC_4 */ 516 channel@4 { 517 reg = <4>; 518 ti,datarate = <4>; 519 ti,gain = <2>; 520 }; 521 522 /* Verdin I2C_1 ADC_3 */ 523 channel@5 { 524 reg = <5>; 525 ti,datarate = <4>; 526 ti,gain = <2>; 527 }; 528 529 /* Verdin I2C_1 ADC_2 */ 530 channel@6 { 531 reg = <6>; 532 ti,datarate = <4>; 533 ti,gain = <2>; 534 }; 535 536 /* Verdin I2C_1 ADC_1 */ 537 channel@7 { 538 reg = <7>; 539 ti,datarate = <4>; 540 ti,gain = <2>; 541 }; 542 }; 543 544 eeprom@50 { 545 compatible = "st,24c02", "atmel,24c02"; 546 pagesize = <16>; 547 reg = <0x50>; 548 }; 549}; 550 551/* Verdin I2C_2_DSI */ 552&i2c2 { 553 clock-frequency = <400000>; 554 pinctrl-names = "default", "gpio"; 555 pinctrl-0 = <&pinctrl_i2c2>; 556 pinctrl-1 = <&pinctrl_i2c2_gpio>; 557 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 558 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 559 single-master; 560 status = "disabled"; 561}; 562 563/* Verdin I2C_3_HDMI N/A */ 564 565/* Verdin I2C_4_CSI */ 566&i2c3 { 567 clock-frequency = <400000>; 568 pinctrl-names = "default", "gpio"; 569 pinctrl-0 = <&pinctrl_i2c3>; 570 pinctrl-1 = <&pinctrl_i2c3_gpio>; 571 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 572 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 573 single-master; 574}; 575 576/* Verdin I2C_1 */ 577&i2c4 { 578 clock-frequency = <400000>; 579 pinctrl-names = "default", "gpio"; 580 pinctrl-0 = <&pinctrl_i2c4>; 581 pinctrl-1 = <&pinctrl_i2c4_gpio>; 582 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 583 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 584 single-master; 585 586 gpio_expander_21: gpio-expander@21 { 587 compatible = "nxp,pcal6416"; 588 #gpio-cells = <2>; 589 gpio-controller; 590 reg = <0x21>; 591 vcc-supply = <®_3p3v>; 592 status = "disabled"; 593 }; 594 595 lvds_ti_sn65dsi84: bridge@2c { 596 compatible = "ti,sn65dsi84"; 597 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 598 /* Verdin GPIO_10_DSI (SODIMM 21) */ 599 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 602 reg = <0x2c>; 603 status = "disabled"; 604 }; 605 606 /* Current measurement into module VCC */ 607 hwmon: hwmon@40 { 608 compatible = "ti,ina219"; 609 reg = <0x40>; 610 shunt-resistor = <10000>; 611 status = "disabled"; 612 }; 613 614 hdmi_lontium_lt8912: hdmi@48 { 615 compatible = "lontium,lt8912b"; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 618 reg = <0x48>; 619 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 620 /* Verdin GPIO_10_DSI (SODIMM 21) */ 621 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 622 status = "disabled"; 623 }; 624 625 atmel_mxt_ts: touch@4a { 626 compatible = "atmel,maxtouch"; 627 /* 628 * Verdin GPIO_9_DSI 629 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 630 */ 631 interrupt-parent = <&gpio3>; 632 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 635 reg = <0x4a>; 636 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 637 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 638 status = "disabled"; 639 }; 640 641 /* Temperature sensor on carrier board */ 642 hwmon_temp: sensor@4f { 643 compatible = "ti,tmp75c"; 644 reg = <0x4f>; 645 status = "disabled"; 646 }; 647 648 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 649 eeprom_display_adapter: eeprom@50 { 650 compatible = "st,24c02", "atmel,24c02"; 651 pagesize = <16>; 652 reg = <0x50>; 653 status = "disabled"; 654 }; 655 656 /* EEPROM on carrier board */ 657 eeprom_carrier_board: eeprom@57 { 658 compatible = "st,24c02", "atmel,24c02"; 659 pagesize = <16>; 660 reg = <0x57>; 661 status = "disabled"; 662 }; 663}; 664 665/* Verdin PCIE_1 */ 666&pcie0 { 667 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 668 <&clk IMX8MM_CLK_PCIE1_CTRL>; 669 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 670 <&clk IMX8MM_SYS_PLL2_250M>; 671 assigned-clock-rates = <10000000>, <250000000>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_pcie0>; 674 /* PCIE_1_RESET# (SODIMM 244) */ 675 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 676}; 677 678&pcie_phy { 679 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 680 clock-names = "ref"; 681 fsl,clkreq-unsupported; 682 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 683 fsl,tx-deemph-gen1 = <0x2d>; 684 fsl,tx-deemph-gen2 = <0xf>; 685}; 686 687/* Verdin PWM_3_DSI */ 688&pwm1 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_pwm_1>; 691 #pwm-cells = <3>; 692}; 693 694/* Verdin PWM_1 */ 695&pwm2 { 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_pwm_2>; 698 #pwm-cells = <3>; 699}; 700 701/* Verdin PWM_2 */ 702&pwm3 { 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_pwm_3>; 705 #pwm-cells = <3>; 706}; 707 708/* Verdin I2S_1 */ 709&sai2 { 710 #sound-dai-cells = <0>; 711 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 712 assigned-clock-rates = <24576000>; 713 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&pinctrl_sai2>; 716}; 717 718&snvs_pwrkey { 719 status = "okay"; 720}; 721 722/* Verdin UART_3, used as the Linux console */ 723&uart1 { 724 pinctrl-names = "default"; 725 pinctrl-0 = <&pinctrl_uart1>; 726}; 727 728/* Verdin UART_1 */ 729&uart2 { 730 pinctrl-names = "default"; 731 pinctrl-0 = <&pinctrl_uart2>; 732 uart-has-rtscts; 733}; 734 735/* Verdin UART_2 */ 736&uart3 { 737 pinctrl-names = "default"; 738 pinctrl-0 = <&pinctrl_uart3>; 739 uart-has-rtscts; 740}; 741 742/* 743 * Verdin UART_4 744 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 745 */ 746&uart4 { 747 pinctrl-names = "default"; 748 pinctrl-0 = <&pinctrl_uart4>; 749}; 750 751/* Verdin USB_1 */ 752&usbotg1 { 753 adp-disable; 754 dr_mode = "otg"; 755 hnp-disable; 756 samsung,picophy-dc-vol-level-adjust = <7>; 757 samsung,picophy-pre-emp-curr-control = <3>; 758 srp-disable; 759 vbus-supply = <®_usb_otg1_vbus>; 760}; 761 762/* Verdin USB_2 */ 763&usbotg2 { 764 dr_mode = "host"; 765 samsung,picophy-dc-vol-level-adjust = <7>; 766 samsung,picophy-pre-emp-curr-control = <3>; 767 vbus-supply = <®_usb_otg2_vbus>; 768}; 769 770&usbphynop1 { 771 vcc-supply = <®_vdd_3v3>; 772}; 773 774&usbphynop2 { 775 power-domains = <&pgc_otg2>; 776 vcc-supply = <®_vdd_3v3>; 777}; 778 779/* On-module eMMC */ 780&usdhc1 { 781 bus-width = <8>; 782 keep-power-in-suspend; 783 non-removable; 784 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 785 pinctrl-0 = <&pinctrl_usdhc1>; 786 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 787 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 788 status = "okay"; 789}; 790 791/* Verdin SD_1 */ 792&usdhc2 { 793 bus-width = <4>; 794 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 795 disable-wp; 796 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 797 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 798 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 799 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 800 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 801 vmmc-supply = <®_usdhc2_vmmc>; 802 vqmmc-supply = <®_usdhc2_vqmmc>; 803}; 804 805&wdog1 { 806 fsl,ext-reset-output; 807 pinctrl-names = "default"; 808 pinctrl-0 = <&pinctrl_wdog>; 809 status = "okay"; 810}; 811 812&iomuxc { 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 815 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 816 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 817 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; 818 819 pinctrl_can1_int: can1intgrp { 820 fsl,pins = 821 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 822 }; 823 824 pinctrl_can2_int: can2intgrp { 825 fsl,pins = 826 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 827 }; 828 829 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 830 fsl,pins = 831 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 832 }; 833 834 pinctrl_ecspi2: ecspi2grp { 835 fsl,pins = 836 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 837 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 838 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 839 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 840 }; 841 842 pinctrl_ecspi3: ecspi3grp { 843 fsl,pins = 844 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 845 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 846 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 847 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 848 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 849 }; 850 851 pinctrl_fec1: fec1grp { 852 fsl,pins = 853 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 854 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 855 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 856 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 857 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 858 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 859 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 860 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 861 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 862 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 863 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 864 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 865 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 866 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 867 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 868 }; 869 870 pinctrl_fec1_sleep: fec1-sleepgrp { 871 fsl,pins = 872 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 873 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 874 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 875 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 876 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 877 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 878 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 879 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 880 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 881 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 882 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 883 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 884 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 885 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 886 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 887 }; 888 889 pinctrl_flexspi0: flexspi0grp { 890 fsl,pins = 891 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 892 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 893 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 894 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 895 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 896 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 897 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 898 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 899 }; 900 901 pinctrl_gpio1: gpio1grp { 902 fsl,pins = 903 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 904 }; 905 906 pinctrl_gpio2: gpio2grp { 907 fsl,pins = 908 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 909 }; 910 911 pinctrl_gpio3: gpio3grp { 912 fsl,pins = 913 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 914 }; 915 916 pinctrl_gpio4: gpio4grp { 917 fsl,pins = 918 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 919 }; 920 921 pinctrl_gpio5: gpio5grp { 922 fsl,pins = 923 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 924 }; 925 926 pinctrl_gpio6: gpio6grp { 927 fsl,pins = 928 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 929 }; 930 931 pinctrl_gpio7: gpio7grp { 932 fsl,pins = 933 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 934 }; 935 936 pinctrl_gpio8: gpio8grp { 937 fsl,pins = 938 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 939 }; 940 941 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 942 pinctrl_gpio_9_dsi: gpio9dsigrp { 943 fsl,pins = 944 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */ 945 }; 946 947 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 948 pinctrl_gpio_10_dsi: gpio10dsigrp { 949 fsl,pins = 950 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 951 }; 952 953 pinctrl_gpio_hog1: gpiohog1grp { 954 fsl,pins = 955 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 956 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 957 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 958 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 959 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 960 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 961 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 962 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 963 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 964 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 965 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 966 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 967 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 968 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 969 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 970 }; 971 972 pinctrl_gpio_hog2: gpiohog2grp { 973 fsl,pins = 974 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 975 }; 976 977 pinctrl_gpio_hog3: gpiohog3grp { 978 fsl,pins = 979 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 980 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 981 }; 982 983 pinctrl_gpio_keys: gpiokeysgrp { 984 fsl,pins = 985 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 986 }; 987 988 /* On-module I2C */ 989 pinctrl_i2c1: i2c1grp { 990 fsl,pins = 991 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 992 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 993 }; 994 995 pinctrl_i2c1_gpio: i2c1gpiogrp { 996 fsl,pins = 997 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 998 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 999 }; 1000 1001 /* Verdin I2C_4_CSI */ 1002 pinctrl_i2c2: i2c2grp { 1003 fsl,pins = 1004 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 1005 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 1006 }; 1007 1008 pinctrl_i2c2_gpio: i2c2gpiogrp { 1009 fsl,pins = 1010 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1011 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1012 }; 1013 1014 /* Verdin I2C_2_DSI */ 1015 pinctrl_i2c3: i2c3grp { 1016 fsl,pins = 1017 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1018 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1019 }; 1020 1021 pinctrl_i2c3_gpio: i2c3gpiogrp { 1022 fsl,pins = 1023 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1024 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1025 }; 1026 1027 /* Verdin I2C_1 */ 1028 pinctrl_i2c4: i2c4grp { 1029 fsl,pins = 1030 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1031 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1032 }; 1033 1034 pinctrl_i2c4_gpio: i2c4gpiogrp { 1035 fsl,pins = 1036 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1037 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1038 }; 1039 1040 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1041 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1042 fsl,pins = 1043 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1044 }; 1045 1046 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1047 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1048 fsl,pins = 1049 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1050 }; 1051 1052 pinctrl_pcie0: pcie0grp { 1053 fsl,pins = 1054 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1055 /* PMIC_EN_PCIe_CLK, unused */ 1056 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1057 }; 1058 1059 pinctrl_pmic: pmicirqgrp { 1060 fsl,pins = 1061 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1062 }; 1063 1064 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1065 pinctrl_pwm_1: pwm1grp { 1066 fsl,pins = 1067 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1068 }; 1069 1070 pinctrl_pwm_2: pwm2grp { 1071 fsl,pins = 1072 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1073 }; 1074 1075 pinctrl_pwm_3: pwm3grp { 1076 fsl,pins = 1077 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1078 }; 1079 1080 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1081 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1082 fsl,pins = 1083 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1084 }; 1085 1086 pinctrl_reg_eth: regethgrp { 1087 fsl,pins = 1088 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1089 }; 1090 1091 pinctrl_reg_usb1_en: regusb1engrp { 1092 fsl,pins = 1093 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1094 }; 1095 1096 pinctrl_reg_usb2_en: regusb2engrp { 1097 fsl,pins = 1098 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1099 }; 1100 1101 pinctrl_sai2: sai2grp { 1102 fsl,pins = 1103 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1104 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1105 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1106 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1107 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1108 }; 1109 1110 pinctrl_sai5: sai5grp { 1111 fsl,pins = 1112 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1113 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1114 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1115 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1116 }; 1117 1118 /* control signal for optional ATTPM20P or SE050 */ 1119 pinctrl_tpm_spi_cs: tpmspicsgrp { 1120 fsl,pins = 1121 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1122 }; 1123 1124 pinctrl_tsp: tspgrp { 1125 fsl,pins = 1126 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1127 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1128 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1129 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1130 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1131 }; 1132 1133 pinctrl_uart1: uart1grp { 1134 fsl,pins = 1135 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1136 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1137 }; 1138 1139 pinctrl_uart2: uart2grp { 1140 fsl,pins = 1141 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1142 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1143 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1144 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1145 }; 1146 1147 pinctrl_uart3: uart3grp { 1148 fsl,pins = 1149 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1150 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1151 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1152 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1153 }; 1154 1155 pinctrl_uart4: uart4grp { 1156 fsl,pins = 1157 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1158 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1159 }; 1160 1161 pinctrl_usdhc1: usdhc1grp { 1162 fsl,pins = 1163 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1164 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1165 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1166 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1167 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1168 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1169 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1170 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1171 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1172 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1173 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1174 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1175 }; 1176 1177 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1178 fsl,pins = 1179 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1180 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1181 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1182 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1183 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1184 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1185 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1186 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1187 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1188 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1189 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1190 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1191 }; 1192 1193 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1194 fsl,pins = 1195 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1196 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1197 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1198 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1199 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1200 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1201 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1202 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1203 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1204 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1205 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1206 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1207 }; 1208 1209 pinctrl_usdhc2_cd: usdhc2cdgrp { 1210 fsl,pins = 1211 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1212 }; 1213 1214 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1215 fsl,pins = 1216 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1217 }; 1218 1219 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1220 fsl,pins = 1221 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1222 }; 1223 1224 pinctrl_usdhc2_vsel: usdhc2vselgrp { 1225 fsl,pins = 1226 <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */ 1227 }; 1228 1229 /* 1230 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1231 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1232 */ 1233 pinctrl_usdhc2: usdhc2grp { 1234 fsl,pins = 1235 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1236 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1237 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1238 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1239 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1240 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1241 }; 1242 1243 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1244 fsl,pins = 1245 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1246 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1247 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1248 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1249 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1250 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1251 }; 1252 1253 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1254 fsl,pins = 1255 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1256 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1257 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1258 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1259 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1260 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1261 }; 1262 1263 /* Avoid backfeeding with removed card power */ 1264 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1265 fsl,pins = 1266 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1267 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1268 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1269 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1270 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1271 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1272 }; 1273 1274 /* 1275 * On-module Wi-Fi/BT or type specific SDHC interface 1276 * (e.g. on X52 extension slot of Verdin Development Board) 1277 */ 1278 pinctrl_usdhc3: usdhc3grp { 1279 fsl,pins = 1280 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1281 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1282 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1283 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1284 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1285 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1286 }; 1287 1288 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1289 fsl,pins = 1290 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1291 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1292 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1293 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1294 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1295 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1296 }; 1297 1298 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1299 fsl,pins = 1300 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1301 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1302 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1303 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1304 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1305 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1306 }; 1307 1308 pinctrl_wdog: wdoggrp { 1309 fsl,pins = 1310 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1311 }; 1312 1313 pinctrl_wifi_ctrl: wifictrlgrp { 1314 fsl,pins = 1315 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1316 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1317 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1318 }; 1319 1320 pinctrl_wifi_i2s: bti2sgrp { 1321 fsl,pins = 1322 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1323 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1324 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1325 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1326 }; 1327 1328 pinctrl_wifi_pwr_en: wifipwrengrp { 1329 fsl,pins = 1330 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1331 }; 1332}; 1333