1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9#include "imx8mm-overdrive.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 aliases { 17 rtc0 = &rtc_i2c; 18 rtc1 = &snvs_rtc; 19 }; 20 21 /* Fixed clock dedicated to SPI CAN controller */ 22 clk40m: oscillator { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <40000000>; 26 }; 27 28 gpio-keys { 29 compatible = "gpio-keys"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pinctrl_gpio_keys>; 32 33 key-wakeup { 34 debounce-interval = <10>; 35 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 36 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 37 label = "Wake-Up"; 38 linux,code = <KEY_WAKEUP>; 39 wakeup-source; 40 }; 41 }; 42 43 hdmi_connector: hdmi-connector { 44 compatible = "hdmi-connector"; 45 ddc-i2c-bus = <&i2c2>; 46 /* Verdin PWM_3_DSI (SODIMM 19) */ 47 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 48 label = "hdmi"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 51 type = "a"; 52 status = "disabled"; 53 }; 54 55 /* Carrier Board Supplies */ 56 reg_1p8v: regulator-1p8v { 57 compatible = "regulator-fixed"; 58 regulator-max-microvolt = <1800000>; 59 regulator-min-microvolt = <1800000>; 60 regulator-name = "+V1.8_SW"; 61 }; 62 63 reg_3p3v: regulator-3p3v { 64 compatible = "regulator-fixed"; 65 regulator-max-microvolt = <3300000>; 66 regulator-min-microvolt = <3300000>; 67 regulator-name = "+V3.3_SW"; 68 }; 69 70 reg_5p0v: regulator-5p0v { 71 compatible = "regulator-fixed"; 72 regulator-max-microvolt = <5000000>; 73 regulator-min-microvolt = <5000000>; 74 regulator-name = "+V5_SW"; 75 }; 76 77 /* Non PMIC On-module Supplies */ 78 reg_ethphy: regulator-ethphy { 79 compatible = "regulator-fixed"; 80 enable-active-high; 81 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 82 off-on-delay-us = <500000>; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_reg_eth>; 85 regulator-always-on; 86 regulator-boot-on; 87 regulator-max-microvolt = <3300000>; 88 regulator-min-microvolt = <3300000>; 89 regulator-name = "On-module +V3.3_ETH"; 90 startup-delay-us = <200000>; 91 }; 92 93 /* 94 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 95 * peripherals on the carrier board powered. 96 * If more granularity or power saving is required this can be disabled 97 * in the carrier board device tree files. 98 */ 99 reg_force_sleep_moci: regulator-force-sleep-moci { 100 compatible = "regulator-fixed"; 101 enable-active-high; 102 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 103 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 104 regulator-always-on; 105 regulator-boot-on; 106 regulator-name = "CTRL_SLEEP_MOCI#"; 107 }; 108 109 reg_usb_otg1_vbus: regulator-usb-otg1 { 110 compatible = "regulator-fixed"; 111 enable-active-high; 112 /* Verdin USB_1_EN (SODIMM 155) */ 113 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_reg_usb1_en>; 116 regulator-max-microvolt = <5000000>; 117 regulator-min-microvolt = <5000000>; 118 regulator-name = "USB_1_EN"; 119 }; 120 121 reg_usb_otg2_vbus: regulator-usb-otg2 { 122 compatible = "regulator-fixed"; 123 enable-active-high; 124 /* Verdin USB_2_EN (SODIMM 185) */ 125 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_reg_usb2_en>; 128 regulator-max-microvolt = <5000000>; 129 regulator-min-microvolt = <5000000>; 130 regulator-name = "USB_2_EN"; 131 }; 132 133 reg_usdhc2_vmmc: regulator-usdhc2 { 134 compatible = "regulator-fixed"; 135 enable-active-high; 136 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 137 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 138 off-on-delay-us = <100000>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 141 regulator-max-microvolt = <3300000>; 142 regulator-min-microvolt = <3300000>; 143 regulator-name = "+V3.3_SD"; 144 startup-delay-us = <20000>; 145 }; 146 147 reserved-memory { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 /* Use the kernel configuration settings instead */ 153 /delete-node/ linux,cma; 154 }; 155}; 156 157&A53_0 { 158 cpu-supply = <®_vdd_arm>; 159}; 160 161&A53_1 { 162 cpu-supply = <®_vdd_arm>; 163}; 164 165&A53_2 { 166 cpu-supply = <®_vdd_arm>; 167}; 168 169&A53_3 { 170 cpu-supply = <®_vdd_arm>; 171}; 172 173&cpu_alert0 { 174 temperature = <95000>; 175}; 176 177&cpu_crit0 { 178 temperature = <105000>; 179}; 180 181&ddrc { 182 operating-points-v2 = <&ddrc_opp_table>; 183 184 ddrc_opp_table: opp-table { 185 compatible = "operating-points-v2"; 186 187 opp-25000000 { 188 opp-hz = /bits/ 64 <25000000>; 189 }; 190 191 opp-100000000 { 192 opp-hz = /bits/ 64 <100000000>; 193 }; 194 195 opp-750000000 { 196 opp-hz = /bits/ 64 <750000000>; 197 }; 198 }; 199}; 200 201/* Verdin SPI_1 */ 202&ecspi2 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_ecspi2>; 208}; 209 210/* On-module SPI */ 211&ecspi3 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; 215 pinctrl-names = "default"; 216 pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>; 217 status = "okay"; 218 219 /* Verdin CAN_1 */ 220 can1: can@0 { 221 compatible = "microchip,mcp251xfd"; 222 clocks = <&clk40m>; 223 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_can1_int>; 226 reg = <0>; 227 spi-max-frequency = <8500000>; 228 }; 229 230 verdin_som_tpm: tpm@1 { 231 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 232 reg = <0x1>; 233 spi-max-frequency = <36000000>; 234 }; 235}; 236 237/* Verdin ETH_1 (On-module PHY) */ 238&fec1 { 239 fsl,magic-packet; 240 phy-handle = <ðphy0>; 241 phy-mode = "rgmii-id"; 242 phy-supply = <®_ethphy>; 243 pinctrl-names = "default", "sleep"; 244 pinctrl-0 = <&pinctrl_fec1>; 245 pinctrl-1 = <&pinctrl_fec1_sleep>; 246 247 mdio { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 ethphy0: ethernet-phy@7 { 252 compatible = "ethernet-phy-ieee802.3-c22"; 253 interrupt-parent = <&gpio1>; 254 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 255 micrel,led-mode = <0>; 256 reg = <7>; 257 }; 258 }; 259}; 260 261/* Verdin QSPI_1 */ 262&flexspi { 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_flexspi0>; 265}; 266 267&gpio1 { 268 gpio-line-names = "SODIMM_216", 269 "SODIMM_19", 270 "", 271 "", 272 "", 273 "", 274 "", 275 "", 276 "SODIMM_220", 277 "SODIMM_222", 278 "", 279 "SODIMM_218", 280 "SODIMM_155", 281 "SODIMM_157", 282 "SODIMM_185", 283 "SODIMM_187"; 284}; 285 286&gpio2 { 287 gpio-line-names = "", 288 "", 289 "", 290 "", 291 "", 292 "", 293 "", 294 "", 295 "", 296 "", 297 "", 298 "", 299 "SODIMM_84", 300 "SODIMM_78", 301 "SODIMM_74", 302 "SODIMM_80", 303 "SODIMM_82", 304 "SODIMM_70", 305 "SODIMM_72"; 306}; 307 308&gpio5 { 309 gpio-line-names = "SODIMM_131", 310 "", 311 "SODIMM_91", 312 "SODIMM_16", 313 "SODIMM_15", 314 "SODIMM_208", 315 "SODIMM_137", 316 "SODIMM_139", 317 "SODIMM_141", 318 "SODIMM_143", 319 "SODIMM_196", 320 "SODIMM_200", 321 "SODIMM_198", 322 "SODIMM_202", 323 "", 324 "", 325 "SODIMM_55", 326 "SODIMM_53", 327 "SODIMM_95", 328 "SODIMM_93", 329 "SODIMM_14", 330 "SODIMM_12", 331 "", 332 "", 333 "", 334 "", 335 "SODIMM_210", 336 "SODIMM_212", 337 "SODIMM_151", 338 "SODIMM_153"; 339}; 340 341/* On-module I2C */ 342&i2c1 { 343 clock-frequency = <400000>; 344 pinctrl-names = "default", "gpio"; 345 pinctrl-0 = <&pinctrl_i2c1>; 346 pinctrl-1 = <&pinctrl_i2c1_gpio>; 347 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 348 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 349 single-master; 350 status = "okay"; 351 352 pca9450: pmic@25 { 353 compatible = "nxp,pca9450a"; 354 interrupt-parent = <&gpio1>; 355 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 356 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_pmic>; 359 reg = <0x25>; 360 361 /* 362 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 363 * behind this PMIC. 364 */ 365 366 regulators { 367 reg_vdd_soc: BUCK1 { 368 nxp,dvs-run-voltage = <850000>; 369 nxp,dvs-standby-voltage = <800000>; 370 regulator-always-on; 371 regulator-boot-on; 372 regulator-max-microvolt = <850000>; 373 regulator-min-microvolt = <800000>; 374 regulator-name = "On-module +VDD_SOC (BUCK1)"; 375 regulator-ramp-delay = <3125>; 376 }; 377 378 reg_vdd_arm: BUCK2 { 379 nxp,dvs-run-voltage = <950000>; 380 nxp,dvs-standby-voltage = <850000>; 381 regulator-always-on; 382 regulator-boot-on; 383 regulator-max-microvolt = <1050000>; 384 regulator-min-microvolt = <805000>; 385 regulator-name = "On-module +VDD_ARM (BUCK2)"; 386 regulator-ramp-delay = <3125>; 387 }; 388 389 reg_vdd_dram: BUCK3 { 390 regulator-always-on; 391 regulator-boot-on; 392 regulator-max-microvolt = <1000000>; 393 regulator-min-microvolt = <805000>; 394 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 395 }; 396 397 reg_vdd_3v3: BUCK4 { 398 regulator-always-on; 399 regulator-boot-on; 400 regulator-max-microvolt = <3300000>; 401 regulator-min-microvolt = <3300000>; 402 regulator-name = "On-module +V3.3 (BUCK4)"; 403 }; 404 405 reg_vdd_1v8: BUCK5 { 406 regulator-always-on; 407 regulator-boot-on; 408 regulator-max-microvolt = <1800000>; 409 regulator-min-microvolt = <1800000>; 410 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 411 }; 412 413 reg_nvcc_dram: BUCK6 { 414 regulator-always-on; 415 regulator-boot-on; 416 regulator-max-microvolt = <1100000>; 417 regulator-min-microvolt = <1100000>; 418 regulator-name = "On-module +VDD_DDR (BUCK6)"; 419 }; 420 421 reg_nvcc_snvs: LDO1 { 422 regulator-always-on; 423 regulator-boot-on; 424 regulator-max-microvolt = <1800000>; 425 regulator-min-microvolt = <1800000>; 426 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 427 }; 428 429 reg_vdd_snvs: LDO2 { 430 regulator-always-on; 431 regulator-boot-on; 432 regulator-max-microvolt = <800000>; 433 regulator-min-microvolt = <800000>; 434 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 435 }; 436 437 reg_vdda: LDO3 { 438 regulator-always-on; 439 regulator-boot-on; 440 regulator-max-microvolt = <1800000>; 441 regulator-min-microvolt = <1800000>; 442 regulator-name = "On-module +V1.8A (LDO3)"; 443 }; 444 445 reg_vdd_phy: LDO4 { 446 regulator-always-on; 447 regulator-boot-on; 448 regulator-max-microvolt = <900000>; 449 regulator-min-microvolt = <900000>; 450 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 451 }; 452 453 reg_nvcc_sd: LDO5 { 454 regulator-max-microvolt = <3300000>; 455 regulator-min-microvolt = <1800000>; 456 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 457 }; 458 }; 459 }; 460 461 rtc_i2c: rtc@32 { 462 compatible = "epson,rx8130"; 463 reg = <0x32>; 464 }; 465 466 verdin_som_adc: adc@49 { 467 compatible = "ti,ads1015"; 468 reg = <0x49>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 #io-channel-cells = <1>; 472 473 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 474 channel@0 { 475 reg = <0>; 476 ti,datarate = <4>; 477 ti,gain = <2>; 478 }; 479 480 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 481 channel@1 { 482 reg = <1>; 483 ti,datarate = <4>; 484 ti,gain = <2>; 485 }; 486 487 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 488 channel@2 { 489 reg = <2>; 490 ti,datarate = <4>; 491 ti,gain = <2>; 492 }; 493 494 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 495 channel@3 { 496 reg = <3>; 497 ti,datarate = <4>; 498 ti,gain = <2>; 499 }; 500 501 /* Verdin I2C_1 ADC_4 */ 502 channel@4 { 503 reg = <4>; 504 ti,datarate = <4>; 505 ti,gain = <2>; 506 }; 507 508 /* Verdin I2C_1 ADC_3 */ 509 channel@5 { 510 reg = <5>; 511 ti,datarate = <4>; 512 ti,gain = <2>; 513 }; 514 515 /* Verdin I2C_1 ADC_2 */ 516 channel@6 { 517 reg = <6>; 518 ti,datarate = <4>; 519 ti,gain = <2>; 520 }; 521 522 /* Verdin I2C_1 ADC_1 */ 523 channel@7 { 524 reg = <7>; 525 ti,datarate = <4>; 526 ti,gain = <2>; 527 }; 528 }; 529 530 eeprom@50 { 531 compatible = "st,24c02"; 532 pagesize = <16>; 533 reg = <0x50>; 534 }; 535}; 536 537/* Verdin I2C_2_DSI */ 538&i2c2 { 539 clock-frequency = <400000>; 540 pinctrl-names = "default", "gpio"; 541 pinctrl-0 = <&pinctrl_i2c2>; 542 pinctrl-1 = <&pinctrl_i2c2_gpio>; 543 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 544 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 545 single-master; 546 status = "disabled"; 547}; 548 549/* Verdin I2C_3_HDMI N/A */ 550 551/* Verdin I2C_4_CSI */ 552&i2c3 { 553 clock-frequency = <400000>; 554 pinctrl-names = "default", "gpio"; 555 pinctrl-0 = <&pinctrl_i2c3>; 556 pinctrl-1 = <&pinctrl_i2c3_gpio>; 557 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 558 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 559 single-master; 560}; 561 562/* Verdin I2C_1 */ 563&i2c4 { 564 clock-frequency = <400000>; 565 pinctrl-names = "default", "gpio"; 566 pinctrl-0 = <&pinctrl_i2c4>; 567 pinctrl-1 = <&pinctrl_i2c4_gpio>; 568 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 570 single-master; 571 572 gpio_expander_21: gpio-expander@21 { 573 compatible = "nxp,pcal6416"; 574 #gpio-cells = <2>; 575 gpio-controller; 576 reg = <0x21>; 577 vcc-supply = <®_3p3v>; 578 status = "disabled"; 579 }; 580 581 lvds_ti_sn65dsi84: bridge@2c { 582 compatible = "ti,sn65dsi84"; 583 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 584 /* Verdin GPIO_10_DSI (SODIMM 21) */ 585 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 588 reg = <0x2c>; 589 status = "disabled"; 590 }; 591 592 /* Current measurement into module VCC */ 593 hwmon: hwmon@40 { 594 compatible = "ti,ina219"; 595 reg = <0x40>; 596 shunt-resistor = <10000>; 597 status = "disabled"; 598 }; 599 600 hdmi_lontium_lt8912: hdmi@48 { 601 compatible = "lontium,lt8912b"; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 604 reg = <0x48>; 605 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 606 /* Verdin GPIO_10_DSI (SODIMM 21) */ 607 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 608 status = "disabled"; 609 }; 610 611 atmel_mxt_ts: touch@4a { 612 compatible = "atmel,maxtouch"; 613 /* 614 * Verdin GPIO_9_DSI 615 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 616 */ 617 interrupt-parent = <&gpio3>; 618 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 621 reg = <0x4a>; 622 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 623 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 624 status = "disabled"; 625 }; 626 627 /* Temperature sensor on carrier board */ 628 hwmon_temp: sensor@4f { 629 compatible = "ti,tmp75c"; 630 reg = <0x4f>; 631 status = "disabled"; 632 }; 633 634 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 635 eeprom_display_adapter: eeprom@50 { 636 compatible = "st,24c02"; 637 pagesize = <16>; 638 reg = <0x50>; 639 status = "disabled"; 640 }; 641 642 /* EEPROM on carrier board */ 643 eeprom_carrier_board: eeprom@57 { 644 compatible = "st,24c02"; 645 pagesize = <16>; 646 reg = <0x57>; 647 status = "disabled"; 648 }; 649}; 650 651/* Verdin PCIE_1 */ 652&pcie0 { 653 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 654 <&clk IMX8MM_CLK_PCIE1_CTRL>; 655 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 656 <&clk IMX8MM_SYS_PLL2_250M>; 657 assigned-clock-rates = <10000000>, <250000000>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pinctrl_pcie0>; 660 /* PCIE_1_RESET# (SODIMM 244) */ 661 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 662}; 663 664&pcie_phy { 665 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 666 clock-names = "ref"; 667 fsl,clkreq-unsupported; 668 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 669 fsl,tx-deemph-gen1 = <0x2d>; 670 fsl,tx-deemph-gen2 = <0xf>; 671}; 672 673/* Verdin PWM_3_DSI */ 674&pwm1 { 675 pinctrl-names = "default"; 676 pinctrl-0 = <&pinctrl_pwm_1>; 677 #pwm-cells = <3>; 678}; 679 680/* Verdin PWM_1 */ 681&pwm2 { 682 pinctrl-names = "default"; 683 pinctrl-0 = <&pinctrl_pwm_2>; 684 #pwm-cells = <3>; 685}; 686 687/* Verdin PWM_2 */ 688&pwm3 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_pwm_3>; 691 #pwm-cells = <3>; 692}; 693 694/* Verdin I2S_1 */ 695&sai2 { 696 #sound-dai-cells = <0>; 697 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 698 assigned-clock-rates = <24576000>; 699 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_sai2>; 702}; 703 704&snvs_pwrkey { 705 status = "okay"; 706}; 707 708/* Verdin UART_3, used as the Linux console */ 709&uart1 { 710 pinctrl-names = "default"; 711 pinctrl-0 = <&pinctrl_uart1>; 712}; 713 714/* Verdin UART_1 */ 715&uart2 { 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pinctrl_uart2>; 718 uart-has-rtscts; 719}; 720 721/* Verdin UART_2 */ 722&uart3 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_uart3>; 725 uart-has-rtscts; 726}; 727 728/* 729 * Verdin UART_4 730 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 731 */ 732&uart4 { 733 pinctrl-names = "default"; 734 pinctrl-0 = <&pinctrl_uart4>; 735}; 736 737/* Verdin USB_1 */ 738&usbotg1 { 739 adp-disable; 740 dr_mode = "otg"; 741 hnp-disable; 742 samsung,picophy-dc-vol-level-adjust = <7>; 743 samsung,picophy-pre-emp-curr-control = <3>; 744 srp-disable; 745 vbus-supply = <®_usb_otg1_vbus>; 746}; 747 748/* Verdin USB_2 */ 749&usbotg2 { 750 dr_mode = "host"; 751 samsung,picophy-dc-vol-level-adjust = <7>; 752 samsung,picophy-pre-emp-curr-control = <3>; 753 vbus-supply = <®_usb_otg2_vbus>; 754}; 755 756&usbphynop1 { 757 vcc-supply = <®_vdd_3v3>; 758}; 759 760&usbphynop2 { 761 power-domains = <&pgc_otg2>; 762 vcc-supply = <®_vdd_3v3>; 763}; 764 765/* On-module eMMC */ 766&usdhc1 { 767 bus-width = <8>; 768 keep-power-in-suspend; 769 non-removable; 770 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 771 pinctrl-0 = <&pinctrl_usdhc1>; 772 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 773 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 774 status = "okay"; 775}; 776 777/* Verdin SD_1 */ 778&usdhc2 { 779 bus-width = <4>; 780 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 781 disable-wp; 782 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 783 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 784 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 785 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 786 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 787 vmmc-supply = <®_usdhc2_vmmc>; 788}; 789 790&wdog1 { 791 fsl,ext-reset-output; 792 pinctrl-names = "default"; 793 pinctrl-0 = <&pinctrl_wdog>; 794 status = "okay"; 795}; 796 797&iomuxc { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 800 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 801 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 802 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; 803 804 pinctrl_can1_int: can1intgrp { 805 fsl,pins = 806 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 807 }; 808 809 pinctrl_can2_int: can2intgrp { 810 fsl,pins = 811 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 812 }; 813 814 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 815 fsl,pins = 816 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 817 }; 818 819 pinctrl_ecspi2: ecspi2grp { 820 fsl,pins = 821 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 822 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 823 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 824 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 825 }; 826 827 pinctrl_ecspi3: ecspi3grp { 828 fsl,pins = 829 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 830 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 831 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 832 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 833 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 834 }; 835 836 pinctrl_fec1: fec1grp { 837 fsl,pins = 838 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 839 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 840 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 841 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 842 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 843 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 844 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 845 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 846 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 847 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 848 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 849 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 850 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 851 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 852 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 853 }; 854 855 pinctrl_fec1_sleep: fec1-sleepgrp { 856 fsl,pins = 857 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 858 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 859 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 860 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 861 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 862 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 863 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 864 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 865 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 866 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 867 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 868 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 869 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 870 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 871 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 872 }; 873 874 pinctrl_flexspi0: flexspi0grp { 875 fsl,pins = 876 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 877 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 878 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 879 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 880 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 881 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 882 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 883 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 884 }; 885 886 pinctrl_gpio1: gpio1grp { 887 fsl,pins = 888 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 889 }; 890 891 pinctrl_gpio2: gpio2grp { 892 fsl,pins = 893 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 894 }; 895 896 pinctrl_gpio3: gpio3grp { 897 fsl,pins = 898 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 899 }; 900 901 pinctrl_gpio4: gpio4grp { 902 fsl,pins = 903 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 904 }; 905 906 pinctrl_gpio5: gpio5grp { 907 fsl,pins = 908 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 909 }; 910 911 pinctrl_gpio6: gpio6grp { 912 fsl,pins = 913 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 914 }; 915 916 pinctrl_gpio7: gpio7grp { 917 fsl,pins = 918 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 919 }; 920 921 pinctrl_gpio8: gpio8grp { 922 fsl,pins = 923 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 924 }; 925 926 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 927 pinctrl_gpio_9_dsi: gpio9dsigrp { 928 fsl,pins = 929 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */ 930 }; 931 932 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 933 pinctrl_gpio_10_dsi: gpio10dsigrp { 934 fsl,pins = 935 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 936 }; 937 938 pinctrl_gpio_hog1: gpiohog1grp { 939 fsl,pins = 940 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 941 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 942 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 943 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 944 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 945 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 946 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 947 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 948 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 949 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 950 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 951 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 952 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 953 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 954 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 955 }; 956 957 pinctrl_gpio_hog2: gpiohog2grp { 958 fsl,pins = 959 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 960 }; 961 962 pinctrl_gpio_hog3: gpiohog3grp { 963 fsl,pins = 964 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 965 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 966 }; 967 968 pinctrl_gpio_keys: gpiokeysgrp { 969 fsl,pins = 970 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 971 }; 972 973 /* On-module I2C */ 974 pinctrl_i2c1: i2c1grp { 975 fsl,pins = 976 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 977 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 978 }; 979 980 pinctrl_i2c1_gpio: i2c1gpiogrp { 981 fsl,pins = 982 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 983 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 984 }; 985 986 /* Verdin I2C_4_CSI */ 987 pinctrl_i2c2: i2c2grp { 988 fsl,pins = 989 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 990 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 991 }; 992 993 pinctrl_i2c2_gpio: i2c2gpiogrp { 994 fsl,pins = 995 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 996 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 997 }; 998 999 /* Verdin I2C_2_DSI */ 1000 pinctrl_i2c3: i2c3grp { 1001 fsl,pins = 1002 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1003 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1004 }; 1005 1006 pinctrl_i2c3_gpio: i2c3gpiogrp { 1007 fsl,pins = 1008 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1009 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1010 }; 1011 1012 /* Verdin I2C_1 */ 1013 pinctrl_i2c4: i2c4grp { 1014 fsl,pins = 1015 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1016 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1017 }; 1018 1019 pinctrl_i2c4_gpio: i2c4gpiogrp { 1020 fsl,pins = 1021 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1022 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1023 }; 1024 1025 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1026 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1027 fsl,pins = 1028 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1029 }; 1030 1031 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1032 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1033 fsl,pins = 1034 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1035 }; 1036 1037 pinctrl_pcie0: pcie0grp { 1038 fsl,pins = 1039 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1040 /* PMIC_EN_PCIe_CLK, unused */ 1041 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1042 }; 1043 1044 pinctrl_pmic: pmicirqgrp { 1045 fsl,pins = 1046 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1047 }; 1048 1049 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1050 pinctrl_pwm_1: pwm1grp { 1051 fsl,pins = 1052 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1053 }; 1054 1055 pinctrl_pwm_2: pwm2grp { 1056 fsl,pins = 1057 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1058 }; 1059 1060 pinctrl_pwm_3: pwm3grp { 1061 fsl,pins = 1062 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1063 }; 1064 1065 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1066 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1067 fsl,pins = 1068 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1069 }; 1070 1071 pinctrl_reg_eth: regethgrp { 1072 fsl,pins = 1073 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1074 }; 1075 1076 pinctrl_reg_usb1_en: regusb1engrp { 1077 fsl,pins = 1078 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1079 }; 1080 1081 pinctrl_reg_usb2_en: regusb2engrp { 1082 fsl,pins = 1083 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1084 }; 1085 1086 pinctrl_sai2: sai2grp { 1087 fsl,pins = 1088 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1089 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1090 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1091 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1092 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1093 }; 1094 1095 pinctrl_sai5: sai5grp { 1096 fsl,pins = 1097 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1098 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1099 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1100 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1101 }; 1102 1103 /* control signal for optional ATTPM20P or SE050 */ 1104 pinctrl_tpm_spi_cs: tpmspicsgrp { 1105 fsl,pins = 1106 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1107 }; 1108 1109 pinctrl_tsp: tspgrp { 1110 fsl,pins = 1111 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1112 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1113 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1114 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1115 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1116 }; 1117 1118 pinctrl_uart1: uart1grp { 1119 fsl,pins = 1120 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1121 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1122 }; 1123 1124 pinctrl_uart2: uart2grp { 1125 fsl,pins = 1126 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1127 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1128 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1129 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1130 }; 1131 1132 pinctrl_uart3: uart3grp { 1133 fsl,pins = 1134 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1135 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1136 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1137 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1138 }; 1139 1140 pinctrl_uart4: uart4grp { 1141 fsl,pins = 1142 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1143 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1144 }; 1145 1146 pinctrl_usdhc1: usdhc1grp { 1147 fsl,pins = 1148 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1149 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1150 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1151 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1152 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1153 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1154 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1155 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1156 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1157 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1158 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1159 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1160 }; 1161 1162 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1163 fsl,pins = 1164 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1165 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1166 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1167 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1168 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1169 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1170 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1171 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1172 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1173 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1174 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1175 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1176 }; 1177 1178 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1179 fsl,pins = 1180 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1181 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1182 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1183 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1184 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1185 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1186 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1187 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1188 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1189 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1190 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1191 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1192 }; 1193 1194 pinctrl_usdhc2_cd: usdhc2cdgrp { 1195 fsl,pins = 1196 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1197 }; 1198 1199 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1200 fsl,pins = 1201 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1202 }; 1203 1204 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1205 fsl,pins = 1206 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1207 }; 1208 1209 /* 1210 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1211 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1212 */ 1213 pinctrl_usdhc2: usdhc2grp { 1214 fsl,pins = 1215 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1216 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1217 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1218 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1219 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1220 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1221 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1222 }; 1223 1224 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1225 fsl,pins = 1226 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1227 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1228 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1229 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1230 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1231 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1232 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1233 }; 1234 1235 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1236 fsl,pins = 1237 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1238 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1239 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1240 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1241 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1242 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1243 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1244 }; 1245 1246 /* Avoid backfeeding with removed card power */ 1247 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1248 fsl,pins = 1249 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1250 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1251 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1252 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1253 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1254 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1255 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1256 }; 1257 1258 /* 1259 * On-module Wi-Fi/BT or type specific SDHC interface 1260 * (e.g. on X52 extension slot of Verdin Development Board) 1261 */ 1262 pinctrl_usdhc3: usdhc3grp { 1263 fsl,pins = 1264 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1265 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1266 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1267 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1268 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1269 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1270 }; 1271 1272 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1273 fsl,pins = 1274 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1275 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1276 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1277 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1278 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1279 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1280 }; 1281 1282 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1283 fsl,pins = 1284 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1285 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1286 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1287 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1288 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1289 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1290 }; 1291 1292 pinctrl_wdog: wdoggrp { 1293 fsl,pins = 1294 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1295 }; 1296 1297 pinctrl_wifi_ctrl: wifictrlgrp { 1298 fsl,pins = 1299 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1300 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1301 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1302 }; 1303 1304 pinctrl_wifi_i2s: bti2sgrp { 1305 fsl,pins = 1306 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1307 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1308 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1309 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1310 }; 1311 1312 pinctrl_wifi_pwr_en: wifipwrengrp { 1313 fsl,pins = 1314 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1315 }; 1316}; 1317