1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk40m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <40000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 hdmi_connector: hdmi-connector { 57 compatible = "hdmi-connector"; 58 ddc-i2c-bus = <&i2c2>; 59 /* Verdin PWM_3_DSI (SODIMM 19) */ 60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 61 label = "hdmi"; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 64 type = "a"; 65 status = "disabled"; 66 }; 67 68 panel_lvds: panel-lvds { 69 compatible = "panel-lvds"; 70 backlight = <&backlight>; 71 data-mapping = "vesa-24"; 72 status = "disabled"; 73 }; 74 75 /* Carrier Board Supplies */ 76 reg_1p8v: regulator-1p8v { 77 compatible = "regulator-fixed"; 78 regulator-max-microvolt = <1800000>; 79 regulator-min-microvolt = <1800000>; 80 regulator-name = "+V1.8_SW"; 81 }; 82 83 reg_3p3v: regulator-3p3v { 84 compatible = "regulator-fixed"; 85 regulator-max-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>; 87 regulator-name = "+V3.3_SW"; 88 }; 89 90 reg_5p0v: regulator-5p0v { 91 compatible = "regulator-fixed"; 92 regulator-max-microvolt = <5000000>; 93 regulator-min-microvolt = <5000000>; 94 regulator-name = "+V5_SW"; 95 }; 96 97 /* Non PMIC On-module Supplies */ 98 reg_ethphy: regulator-ethphy { 99 compatible = "regulator-fixed"; 100 enable-active-high; 101 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 102 off-on-delay-us = <500000>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_reg_eth>; 105 regulator-always-on; 106 regulator-boot-on; 107 regulator-max-microvolt = <3300000>; 108 regulator-min-microvolt = <3300000>; 109 regulator-name = "On-module +V3.3_ETH"; 110 startup-delay-us = <200000>; 111 }; 112 113 /* 114 * By default we enable CTRL_SLEEP_MOCI#, this is required to have 115 * peripherals on the carrier board powered. 116 * If more granularity or power saving is required this can be disabled 117 * in the carrier board device tree files. 118 */ 119 reg_force_sleep_moci: regulator-force-sleep-moci { 120 compatible = "regulator-fixed"; 121 enable-active-high; 122 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 123 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 124 regulator-always-on; 125 regulator-boot-on; 126 regulator-name = "CTRL_SLEEP_MOCI#"; 127 }; 128 129 reg_usb_otg1_vbus: regulator-usb-otg1 { 130 compatible = "regulator-fixed"; 131 enable-active-high; 132 /* Verdin USB_1_EN (SODIMM 155) */ 133 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_reg_usb1_en>; 136 regulator-max-microvolt = <5000000>; 137 regulator-min-microvolt = <5000000>; 138 regulator-name = "USB_1_EN"; 139 }; 140 141 reg_usb_otg2_vbus: regulator-usb-otg2 { 142 compatible = "regulator-fixed"; 143 enable-active-high; 144 /* Verdin USB_2_EN (SODIMM 185) */ 145 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_reg_usb2_en>; 148 regulator-max-microvolt = <5000000>; 149 regulator-min-microvolt = <5000000>; 150 regulator-name = "USB_2_EN"; 151 }; 152 153 reg_usdhc2_vmmc: regulator-usdhc2 { 154 compatible = "regulator-fixed"; 155 enable-active-high; 156 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 157 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 158 off-on-delay-us = <100000>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 161 regulator-max-microvolt = <3300000>; 162 regulator-min-microvolt = <3300000>; 163 regulator-name = "+V3.3_SD"; 164 startup-delay-us = <2000>; 165 }; 166 167 reserved-memory { 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 /* Use the kernel configuration settings instead */ 173 /delete-node/ linux,cma; 174 }; 175}; 176 177&A53_0 { 178 cpu-supply = <®_vdd_arm>; 179}; 180 181&A53_1 { 182 cpu-supply = <®_vdd_arm>; 183}; 184 185&A53_2 { 186 cpu-supply = <®_vdd_arm>; 187}; 188 189&A53_3 { 190 cpu-supply = <®_vdd_arm>; 191}; 192 193&cpu_alert0 { 194 temperature = <95000>; 195}; 196 197&cpu_crit0 { 198 temperature = <105000>; 199}; 200 201&ddrc { 202 operating-points-v2 = <&ddrc_opp_table>; 203 204 ddrc_opp_table: opp-table { 205 compatible = "operating-points-v2"; 206 207 opp-25000000 { 208 opp-hz = /bits/ 64 <25000000>; 209 }; 210 211 opp-100000000 { 212 opp-hz = /bits/ 64 <100000000>; 213 }; 214 215 opp-750000000 { 216 opp-hz = /bits/ 64 <750000000>; 217 }; 218 }; 219}; 220 221/* Verdin SPI_1 */ 222&ecspi2 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_ecspi2>; 228}; 229 230/* Verdin CAN_1 (On-module) */ 231&ecspi3 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_ecspi3>; 237 status = "okay"; 238 239 can1: can@0 { 240 compatible = "microchip,mcp251xfd"; 241 clocks = <&clk40m>; 242 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_can1_int>; 245 reg = <0>; 246 spi-max-frequency = <8500000>; 247 }; 248}; 249 250/* Verdin ETH_1 (On-module PHY) */ 251&fec1 { 252 fsl,magic-packet; 253 phy-handle = <ðphy0>; 254 phy-mode = "rgmii-id"; 255 phy-supply = <®_ethphy>; 256 pinctrl-names = "default", "sleep"; 257 pinctrl-0 = <&pinctrl_fec1>; 258 pinctrl-1 = <&pinctrl_fec1_sleep>; 259 260 mdio { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 ethphy0: ethernet-phy@7 { 265 compatible = "ethernet-phy-ieee802.3-c22"; 266 interrupt-parent = <&gpio1>; 267 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 268 micrel,led-mode = <0>; 269 reg = <7>; 270 }; 271 }; 272}; 273 274/* Verdin QSPI_1 */ 275&flexspi { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_flexspi0>; 278}; 279 280&gpio1 { 281 gpio-line-names = "SODIMM_216", 282 "SODIMM_19", 283 "", 284 "", 285 "", 286 "", 287 "", 288 "", 289 "SODIMM_220", 290 "SODIMM_222", 291 "", 292 "SODIMM_218", 293 "SODIMM_155", 294 "SODIMM_157", 295 "SODIMM_185", 296 "SODIMM_187"; 297}; 298 299&gpio2 { 300 gpio-line-names = "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "", 310 "", 311 "", 312 "SODIMM_84", 313 "SODIMM_78", 314 "SODIMM_74", 315 "SODIMM_80", 316 "SODIMM_82", 317 "SODIMM_70", 318 "SODIMM_72"; 319}; 320 321&gpio5 { 322 gpio-line-names = "SODIMM_131", 323 "", 324 "SODIMM_91", 325 "SODIMM_16", 326 "SODIMM_15", 327 "SODIMM_208", 328 "SODIMM_137", 329 "SODIMM_139", 330 "SODIMM_141", 331 "SODIMM_143", 332 "SODIMM_196", 333 "SODIMM_200", 334 "SODIMM_198", 335 "SODIMM_202", 336 "", 337 "", 338 "SODIMM_55", 339 "SODIMM_53", 340 "SODIMM_95", 341 "SODIMM_93", 342 "SODIMM_14", 343 "SODIMM_12", 344 "", 345 "", 346 "", 347 "", 348 "SODIMM_210", 349 "SODIMM_212", 350 "SODIMM_151", 351 "SODIMM_153"; 352}; 353 354/* On-module I2C */ 355&i2c1 { 356 clock-frequency = <400000>; 357 pinctrl-names = "default", "gpio"; 358 pinctrl-0 = <&pinctrl_i2c1>; 359 pinctrl-1 = <&pinctrl_i2c1_gpio>; 360 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 361 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 362 status = "okay"; 363 364 pca9450: pmic@25 { 365 compatible = "nxp,pca9450a"; 366 interrupt-parent = <&gpio1>; 367 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 368 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_pmic>; 371 reg = <0x25>; 372 373 /* 374 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 375 * behind this PMIC. 376 */ 377 378 regulators { 379 reg_vdd_soc: BUCK1 { 380 nxp,dvs-run-voltage = <850000>; 381 nxp,dvs-standby-voltage = <800000>; 382 regulator-always-on; 383 regulator-boot-on; 384 regulator-max-microvolt = <850000>; 385 regulator-min-microvolt = <800000>; 386 regulator-name = "On-module +VDD_SOC (BUCK1)"; 387 regulator-ramp-delay = <3125>; 388 }; 389 390 reg_vdd_arm: BUCK2 { 391 nxp,dvs-run-voltage = <950000>; 392 nxp,dvs-standby-voltage = <850000>; 393 regulator-always-on; 394 regulator-boot-on; 395 regulator-max-microvolt = <1050000>; 396 regulator-min-microvolt = <805000>; 397 regulator-name = "On-module +VDD_ARM (BUCK2)"; 398 regulator-ramp-delay = <3125>; 399 }; 400 401 reg_vdd_dram: BUCK3 { 402 regulator-always-on; 403 regulator-boot-on; 404 regulator-max-microvolt = <1000000>; 405 regulator-min-microvolt = <805000>; 406 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 407 }; 408 409 reg_vdd_3v3: BUCK4 { 410 regulator-always-on; 411 regulator-boot-on; 412 regulator-max-microvolt = <3300000>; 413 regulator-min-microvolt = <3300000>; 414 regulator-name = "On-module +V3.3 (BUCK4)"; 415 }; 416 417 reg_vdd_1v8: BUCK5 { 418 regulator-always-on; 419 regulator-boot-on; 420 regulator-max-microvolt = <1800000>; 421 regulator-min-microvolt = <1800000>; 422 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 423 }; 424 425 reg_nvcc_dram: BUCK6 { 426 regulator-always-on; 427 regulator-boot-on; 428 regulator-max-microvolt = <1100000>; 429 regulator-min-microvolt = <1100000>; 430 regulator-name = "On-module +VDD_DDR (BUCK6)"; 431 }; 432 433 reg_nvcc_snvs: LDO1 { 434 regulator-always-on; 435 regulator-boot-on; 436 regulator-max-microvolt = <1800000>; 437 regulator-min-microvolt = <1800000>; 438 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 439 }; 440 441 reg_vdd_snvs: LDO2 { 442 regulator-always-on; 443 regulator-boot-on; 444 regulator-max-microvolt = <800000>; 445 regulator-min-microvolt = <800000>; 446 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 447 }; 448 449 reg_vdda: LDO3 { 450 regulator-always-on; 451 regulator-boot-on; 452 regulator-max-microvolt = <1800000>; 453 regulator-min-microvolt = <1800000>; 454 regulator-name = "On-module +V1.8A (LDO3)"; 455 }; 456 457 reg_vdd_phy: LDO4 { 458 regulator-always-on; 459 regulator-boot-on; 460 regulator-max-microvolt = <900000>; 461 regulator-min-microvolt = <900000>; 462 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 463 }; 464 465 reg_nvcc_sd: LDO5 { 466 regulator-max-microvolt = <3300000>; 467 regulator-min-microvolt = <1800000>; 468 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 469 }; 470 }; 471 }; 472 473 rtc_i2c: rtc@32 { 474 compatible = "epson,rx8130"; 475 reg = <0x32>; 476 }; 477 478 adc@49 { 479 compatible = "ti,ads1015"; 480 reg = <0x49>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 485 channel@0 { 486 reg = <0>; 487 ti,datarate = <4>; 488 ti,gain = <2>; 489 }; 490 491 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 492 channel@1 { 493 reg = <1>; 494 ti,datarate = <4>; 495 ti,gain = <2>; 496 }; 497 498 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 499 channel@2 { 500 reg = <2>; 501 ti,datarate = <4>; 502 ti,gain = <2>; 503 }; 504 505 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 506 channel@3 { 507 reg = <3>; 508 ti,datarate = <4>; 509 ti,gain = <2>; 510 }; 511 512 /* Verdin I2C_1 ADC_4 */ 513 channel@4 { 514 reg = <4>; 515 ti,datarate = <4>; 516 ti,gain = <2>; 517 }; 518 519 /* Verdin I2C_1 ADC_3 */ 520 channel@5 { 521 reg = <5>; 522 ti,datarate = <4>; 523 ti,gain = <2>; 524 }; 525 526 /* Verdin I2C_1 ADC_2 */ 527 channel@6 { 528 reg = <6>; 529 ti,datarate = <4>; 530 ti,gain = <2>; 531 }; 532 533 /* Verdin I2C_1 ADC_1 */ 534 channel@7 { 535 reg = <7>; 536 ti,datarate = <4>; 537 ti,gain = <2>; 538 }; 539 }; 540 541 eeprom@50 { 542 compatible = "st,24c02"; 543 pagesize = <16>; 544 reg = <0x50>; 545 }; 546}; 547 548/* Verdin I2C_2_DSI */ 549&i2c2 { 550 clock-frequency = <10000>; 551 pinctrl-names = "default", "gpio"; 552 pinctrl-0 = <&pinctrl_i2c2>; 553 pinctrl-1 = <&pinctrl_i2c2_gpio>; 554 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 555 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 556 status = "disabled"; 557}; 558 559/* Verdin I2C_3_HDMI N/A */ 560 561/* Verdin I2C_4_CSI */ 562&i2c3 { 563 clock-frequency = <400000>; 564 pinctrl-names = "default", "gpio"; 565 pinctrl-0 = <&pinctrl_i2c3>; 566 pinctrl-1 = <&pinctrl_i2c3_gpio>; 567 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 568 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569}; 570 571/* Verdin I2C_1 */ 572&i2c4 { 573 clock-frequency = <400000>; 574 pinctrl-names = "default", "gpio"; 575 pinctrl-0 = <&pinctrl_i2c4>; 576 pinctrl-1 = <&pinctrl_i2c4_gpio>; 577 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 578 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 579 580 gpio_expander_21: gpio-expander@21 { 581 compatible = "nxp,pcal6416"; 582 #gpio-cells = <2>; 583 gpio-controller; 584 reg = <0x21>; 585 vcc-supply = <®_3p3v>; 586 status = "disabled"; 587 }; 588 589 lvds_ti_sn65dsi84: bridge@2c { 590 compatible = "ti,sn65dsi84"; 591 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 592 /* Verdin GPIO_10_DSI (SODIMM 21) */ 593 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 596 reg = <0x2c>; 597 status = "disabled"; 598 }; 599 600 /* Current measurement into module VCC */ 601 hwmon: hwmon@40 { 602 compatible = "ti,ina219"; 603 reg = <0x40>; 604 shunt-resistor = <10000>; 605 status = "disabled"; 606 }; 607 608 hdmi_lontium_lt8912: hdmi@48 { 609 compatible = "lontium,lt8912b"; 610 pinctrl-names = "default"; 611 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 612 reg = <0x48>; 613 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 614 /* Verdin GPIO_10_DSI (SODIMM 21) */ 615 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 616 status = "disabled"; 617 }; 618 619 atmel_mxt_ts: touch@4a { 620 compatible = "atmel,maxtouch"; 621 /* 622 * Verdin GPIO_9_DSI 623 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 624 */ 625 interrupt-parent = <&gpio3>; 626 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 629 reg = <0x4a>; 630 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 631 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 632 status = "disabled"; 633 }; 634 635 /* Temperature sensor on carrier board */ 636 hwmon_temp: sensor@4f { 637 compatible = "ti,tmp75c"; 638 reg = <0x4f>; 639 status = "disabled"; 640 }; 641 642 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 643 eeprom_display_adapter: eeprom@50 { 644 compatible = "st,24c02"; 645 pagesize = <16>; 646 reg = <0x50>; 647 status = "disabled"; 648 }; 649 650 /* EEPROM on carrier board */ 651 eeprom_carrier_board: eeprom@57 { 652 compatible = "st,24c02"; 653 pagesize = <16>; 654 reg = <0x57>; 655 status = "disabled"; 656 }; 657}; 658 659/* Verdin PCIE_1 */ 660&pcie0 { 661 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 662 <&clk IMX8MM_CLK_PCIE1_CTRL>; 663 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 664 <&clk IMX8MM_SYS_PLL2_250M>; 665 assigned-clock-rates = <10000000>, <250000000>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pinctrl_pcie0>; 668 /* PCIE_1_RESET# (SODIMM 244) */ 669 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 670}; 671 672&pcie_phy { 673 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 674 clock-names = "ref"; 675 fsl,clkreq-unsupported; 676 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 677 fsl,tx-deemph-gen1 = <0x2d>; 678 fsl,tx-deemph-gen2 = <0xf>; 679}; 680 681/* Verdin PWM_3_DSI */ 682&pwm1 { 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pinctrl_pwm_1>; 685 #pwm-cells = <3>; 686}; 687 688/* Verdin PWM_1 */ 689&pwm2 { 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pinctrl_pwm_2>; 692 #pwm-cells = <3>; 693}; 694 695/* Verdin PWM_2 */ 696&pwm3 { 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pinctrl_pwm_3>; 699 #pwm-cells = <3>; 700}; 701 702/* Verdin I2S_1 */ 703&sai2 { 704 #sound-dai-cells = <0>; 705 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 706 assigned-clock-rates = <24576000>; 707 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&pinctrl_sai2>; 710}; 711 712&snvs_pwrkey { 713 status = "okay"; 714}; 715 716/* Verdin UART_3, used as the Linux console */ 717&uart1 { 718 pinctrl-names = "default"; 719 pinctrl-0 = <&pinctrl_uart1>; 720}; 721 722/* Verdin UART_1 */ 723&uart2 { 724 pinctrl-names = "default"; 725 pinctrl-0 = <&pinctrl_uart2>; 726 uart-has-rtscts; 727}; 728 729/* Verdin UART_2 */ 730&uart3 { 731 pinctrl-names = "default"; 732 pinctrl-0 = <&pinctrl_uart3>; 733 uart-has-rtscts; 734}; 735 736/* 737 * Verdin UART_4 738 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 739 */ 740&uart4 { 741 pinctrl-names = "default"; 742 pinctrl-0 = <&pinctrl_uart4>; 743}; 744 745/* Verdin USB_1 */ 746&usbotg1 { 747 adp-disable; 748 dr_mode = "otg"; 749 hnp-disable; 750 samsung,picophy-dc-vol-level-adjust = <7>; 751 samsung,picophy-pre-emp-curr-control = <3>; 752 srp-disable; 753 vbus-supply = <®_usb_otg1_vbus>; 754}; 755 756/* Verdin USB_2 */ 757&usbotg2 { 758 dr_mode = "host"; 759 samsung,picophy-dc-vol-level-adjust = <7>; 760 samsung,picophy-pre-emp-curr-control = <3>; 761 vbus-supply = <®_usb_otg2_vbus>; 762}; 763 764&usbphynop1 { 765 vcc-supply = <®_vdd_3v3>; 766}; 767 768&usbphynop2 { 769 power-domains = <&pgc_otg2>; 770 vcc-supply = <®_vdd_3v3>; 771}; 772 773/* On-module eMMC */ 774&usdhc1 { 775 bus-width = <8>; 776 keep-power-in-suspend; 777 non-removable; 778 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 779 pinctrl-0 = <&pinctrl_usdhc1>; 780 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 781 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 782 status = "okay"; 783}; 784 785/* Verdin SD_1 */ 786&usdhc2 { 787 bus-width = <4>; 788 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 789 disable-wp; 790 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 791 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 792 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 793 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 794 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 795 vmmc-supply = <®_usdhc2_vmmc>; 796}; 797 798&wdog1 { 799 fsl,ext-reset-output; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pinctrl_wdog>; 802 status = "okay"; 803}; 804 805&iomuxc { 806 pinctrl-names = "default"; 807 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 808 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 809 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 810 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 811 <&pinctrl_pmic_tpm_ena>; 812 813 pinctrl_can1_int: can1intgrp { 814 fsl,pins = 815 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 816 }; 817 818 pinctrl_can2_int: can2intgrp { 819 fsl,pins = 820 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 821 }; 822 823 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 824 fsl,pins = 825 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 826 }; 827 828 pinctrl_ecspi2: ecspi2grp { 829 fsl,pins = 830 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 831 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 832 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 833 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 834 }; 835 836 pinctrl_ecspi3: ecspi3grp { 837 fsl,pins = 838 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 839 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 840 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 841 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 842 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 843 }; 844 845 pinctrl_fec1: fec1grp { 846 fsl,pins = 847 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 848 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 849 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 850 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 851 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 852 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 853 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 854 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 855 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 856 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 857 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 858 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 859 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 860 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 861 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 862 }; 863 864 pinctrl_fec1_sleep: fec1-sleepgrp { 865 fsl,pins = 866 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 867 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 868 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 869 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 870 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 871 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 872 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 873 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 874 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 875 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 876 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 877 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 878 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 879 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 880 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 881 }; 882 883 pinctrl_flexspi0: flexspi0grp { 884 fsl,pins = 885 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 886 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 887 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 888 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 889 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 890 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 891 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 892 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 893 }; 894 895 pinctrl_gpio1: gpio1grp { 896 fsl,pins = 897 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 898 }; 899 900 pinctrl_gpio2: gpio2grp { 901 fsl,pins = 902 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 903 }; 904 905 pinctrl_gpio3: gpio3grp { 906 fsl,pins = 907 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 908 }; 909 910 pinctrl_gpio4: gpio4grp { 911 fsl,pins = 912 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 913 }; 914 915 pinctrl_gpio5: gpio5grp { 916 fsl,pins = 917 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 918 }; 919 920 pinctrl_gpio6: gpio6grp { 921 fsl,pins = 922 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 923 }; 924 925 pinctrl_gpio7: gpio7grp { 926 fsl,pins = 927 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 928 }; 929 930 pinctrl_gpio8: gpio8grp { 931 fsl,pins = 932 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 933 }; 934 935 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 936 pinctrl_gpio_9_dsi: gpio9dsigrp { 937 fsl,pins = 938 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ 939 }; 940 941 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 942 pinctrl_gpio_10_dsi: gpio10dsigrp { 943 fsl,pins = 944 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 945 }; 946 947 pinctrl_gpio_hog1: gpiohog1grp { 948 fsl,pins = 949 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 950 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 951 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 952 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 953 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 954 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 955 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 956 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 957 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 958 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 959 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 960 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 961 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 962 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 963 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 964 }; 965 966 pinctrl_gpio_hog2: gpiohog2grp { 967 fsl,pins = 968 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 969 }; 970 971 pinctrl_gpio_hog3: gpiohog3grp { 972 fsl,pins = 973 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 974 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 975 }; 976 977 pinctrl_gpio_keys: gpiokeysgrp { 978 fsl,pins = 979 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 980 }; 981 982 /* On-module I2C */ 983 pinctrl_i2c1: i2c1grp { 984 fsl,pins = 985 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 986 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 987 }; 988 989 pinctrl_i2c1_gpio: i2c1gpiogrp { 990 fsl,pins = 991 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 992 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 993 }; 994 995 /* Verdin I2C_4_CSI */ 996 pinctrl_i2c2: i2c2grp { 997 fsl,pins = 998 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 999 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 1000 }; 1001 1002 pinctrl_i2c2_gpio: i2c2gpiogrp { 1003 fsl,pins = 1004 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1005 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1006 }; 1007 1008 /* Verdin I2C_2_DSI */ 1009 pinctrl_i2c3: i2c3grp { 1010 fsl,pins = 1011 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1012 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1013 }; 1014 1015 pinctrl_i2c3_gpio: i2c3gpiogrp { 1016 fsl,pins = 1017 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1018 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1019 }; 1020 1021 /* Verdin I2C_1 */ 1022 pinctrl_i2c4: i2c4grp { 1023 fsl,pins = 1024 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1025 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1026 }; 1027 1028 pinctrl_i2c4_gpio: i2c4gpiogrp { 1029 fsl,pins = 1030 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1031 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1032 }; 1033 1034 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1035 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1036 fsl,pins = 1037 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1038 }; 1039 1040 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1041 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1042 fsl,pins = 1043 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1044 }; 1045 1046 pinctrl_pcie0: pcie0grp { 1047 fsl,pins = 1048 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1049 /* PMIC_EN_PCIe_CLK, unused */ 1050 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1051 }; 1052 1053 pinctrl_pmic: pmicirqgrp { 1054 fsl,pins = 1055 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1056 }; 1057 1058 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1059 pinctrl_pwm_1: pwm1grp { 1060 fsl,pins = 1061 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1062 }; 1063 1064 pinctrl_pwm_2: pwm2grp { 1065 fsl,pins = 1066 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1067 }; 1068 1069 pinctrl_pwm_3: pwm3grp { 1070 fsl,pins = 1071 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1072 }; 1073 1074 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1075 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1076 fsl,pins = 1077 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1078 }; 1079 1080 pinctrl_reg_eth: regethgrp { 1081 fsl,pins = 1082 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1083 }; 1084 1085 pinctrl_reg_usb1_en: regusb1engrp { 1086 fsl,pins = 1087 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1088 }; 1089 1090 pinctrl_reg_usb2_en: regusb2engrp { 1091 fsl,pins = 1092 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1093 }; 1094 1095 pinctrl_sai2: sai2grp { 1096 fsl,pins = 1097 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1098 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1099 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1100 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1101 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1102 }; 1103 1104 pinctrl_sai5: sai5grp { 1105 fsl,pins = 1106 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1107 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1108 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1109 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1110 }; 1111 1112 /* control signal for optional ATTPM20P or SE050 */ 1113 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1114 fsl,pins = 1115 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1116 }; 1117 1118 pinctrl_tsp: tspgrp { 1119 fsl,pins = 1120 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1121 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1122 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1123 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1124 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1125 }; 1126 1127 pinctrl_uart1: uart1grp { 1128 fsl,pins = 1129 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1130 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1131 }; 1132 1133 pinctrl_uart2: uart2grp { 1134 fsl,pins = 1135 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1136 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1137 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1138 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1139 }; 1140 1141 pinctrl_uart3: uart3grp { 1142 fsl,pins = 1143 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1144 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1145 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1146 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1147 }; 1148 1149 pinctrl_uart4: uart4grp { 1150 fsl,pins = 1151 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1152 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1153 }; 1154 1155 pinctrl_usdhc1: usdhc1grp { 1156 fsl,pins = 1157 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1158 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1159 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1160 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1161 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1162 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1163 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1164 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1165 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1166 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1167 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1168 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1169 }; 1170 1171 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1172 fsl,pins = 1173 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1174 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1175 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1176 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1177 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1178 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1179 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1180 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1181 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1182 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1183 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1184 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1185 }; 1186 1187 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1188 fsl,pins = 1189 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1190 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1191 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1192 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1193 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1194 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1195 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1196 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1197 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1198 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1199 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1200 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1201 }; 1202 1203 pinctrl_usdhc2_cd: usdhc2cdgrp { 1204 fsl,pins = 1205 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1206 }; 1207 1208 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1209 fsl,pins = 1210 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1211 }; 1212 1213 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1214 fsl,pins = 1215 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1216 }; 1217 1218 /* 1219 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1220 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1221 */ 1222 pinctrl_usdhc2: usdhc2grp { 1223 fsl,pins = 1224 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1225 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1226 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1227 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1228 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1229 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1230 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1231 }; 1232 1233 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1234 fsl,pins = 1235 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1236 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1237 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1238 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1239 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1240 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1241 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1242 }; 1243 1244 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1245 fsl,pins = 1246 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1247 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1248 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1249 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1250 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1251 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1252 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1253 }; 1254 1255 /* Avoid backfeeding with removed card power */ 1256 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1257 fsl,pins = 1258 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1259 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1260 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1261 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1262 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1263 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1264 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1265 }; 1266 1267 /* 1268 * On-module Wi-Fi/BT or type specific SDHC interface 1269 * (e.g. on X52 extension slot of Verdin Development Board) 1270 */ 1271 pinctrl_usdhc3: usdhc3grp { 1272 fsl,pins = 1273 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1274 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1275 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1276 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1277 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1278 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1279 }; 1280 1281 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1282 fsl,pins = 1283 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1284 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1285 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1286 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1287 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1288 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1289 }; 1290 1291 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1292 fsl,pins = 1293 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1294 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1295 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1296 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1297 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1298 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1299 }; 1300 1301 pinctrl_wdog: wdoggrp { 1302 fsl,pins = 1303 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1304 }; 1305 1306 pinctrl_wifi_ctrl: wifictrlgrp { 1307 fsl,pins = 1308 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1309 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1310 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1311 }; 1312 1313 pinctrl_wifi_i2s: bti2sgrp { 1314 fsl,pins = 1315 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1316 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1317 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1318 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1319 }; 1320 1321 pinctrl_wifi_pwr_en: wifipwrengrp { 1322 fsl,pins = 1323 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1324 }; 1325}; 1326