16a57f224SMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 26a57f224SMarcel Ziswiler/* 36a57f224SMarcel Ziswiler * Copyright 2022 Toradex 46a57f224SMarcel Ziswiler */ 56a57f224SMarcel Ziswiler 66a57f224SMarcel Ziswiler/ { 76a57f224SMarcel Ziswiler sound_card: sound-card { 86a57f224SMarcel Ziswiler compatible = "simple-audio-card"; 96a57f224SMarcel Ziswiler simple-audio-card,bitclock-master = <&dailink_master>; 106a57f224SMarcel Ziswiler simple-audio-card,format = "i2s"; 116a57f224SMarcel Ziswiler simple-audio-card,frame-master = <&dailink_master>; 120d1d030fSEmanuele Ghidoli simple-audio-card,mclk-fs = <256>; 13*7f699ed1SHiago De Franco simple-audio-card,name = "verdin-wm8904"; 146a57f224SMarcel Ziswiler simple-audio-card,routing = 156a57f224SMarcel Ziswiler "Headphone Jack", "HPOUTL", 166a57f224SMarcel Ziswiler "Headphone Jack", "HPOUTR", 176a57f224SMarcel Ziswiler "IN2L", "Line In Jack", 186a57f224SMarcel Ziswiler "IN2R", "Line In Jack", 196a57f224SMarcel Ziswiler "Headphone Jack", "MICBIAS", 206a57f224SMarcel Ziswiler "IN1L", "Headphone Jack"; 216a57f224SMarcel Ziswiler simple-audio-card,widgets = 226a57f224SMarcel Ziswiler "Microphone", "Headphone Jack", 236a57f224SMarcel Ziswiler "Headphone", "Headphone Jack", 246a57f224SMarcel Ziswiler "Line", "Line In Jack"; 256a57f224SMarcel Ziswiler 266a57f224SMarcel Ziswiler dailink_master: simple-audio-card,codec { 276a57f224SMarcel Ziswiler clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; 286a57f224SMarcel Ziswiler sound-dai = <&wm8904_1a>; 296a57f224SMarcel Ziswiler }; 306a57f224SMarcel Ziswiler 316a57f224SMarcel Ziswiler simple-audio-card,cpu { 326a57f224SMarcel Ziswiler sound-dai = <&sai2>; 336a57f224SMarcel Ziswiler }; 346a57f224SMarcel Ziswiler }; 351288f819SStefan Eichenberger 361288f819SStefan Eichenberger reg_usb_hub: regulator-usb-hub { 371288f819SStefan Eichenberger compatible = "regulator-fixed"; 381288f819SStefan Eichenberger enable-active-high; 391288f819SStefan Eichenberger /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 401288f819SStefan Eichenberger gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 411288f819SStefan Eichenberger regulator-boot-on; 421288f819SStefan Eichenberger regulator-name = "HUB_PWR_EN"; 431288f819SStefan Eichenberger }; 441288f819SStefan Eichenberger 451288f819SStefan Eichenberger reg_pcie: regulator-pcie { 461288f819SStefan Eichenberger compatible = "regulator-fixed"; 471288f819SStefan Eichenberger enable-active-high; 481288f819SStefan Eichenberger /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 491288f819SStefan Eichenberger gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 501288f819SStefan Eichenberger regulator-boot-on; 511288f819SStefan Eichenberger regulator-name = "PCIE_1_PWR_EN"; 521288f819SStefan Eichenberger startup-delay-us = <100000>; 531288f819SStefan Eichenberger }; 546a57f224SMarcel Ziswiler}; 556a57f224SMarcel Ziswiler 566a57f224SMarcel Ziswiler/* Verdin SPI_1 */ 576a57f224SMarcel Ziswiler&ecspi2 { 586a57f224SMarcel Ziswiler status = "okay"; 596a57f224SMarcel Ziswiler}; 606a57f224SMarcel Ziswiler 616a57f224SMarcel Ziswiler/* EEPROM on display adapter boards */ 626a57f224SMarcel Ziswiler&eeprom_display_adapter { 636a57f224SMarcel Ziswiler status = "okay"; 646a57f224SMarcel Ziswiler}; 656a57f224SMarcel Ziswiler 666a57f224SMarcel Ziswiler/* EEPROM on Verdin Development board */ 676a57f224SMarcel Ziswiler&eeprom_carrier_board { 686a57f224SMarcel Ziswiler status = "okay"; 696a57f224SMarcel Ziswiler}; 706a57f224SMarcel Ziswiler 716a57f224SMarcel Ziswiler&fec1 { 726a57f224SMarcel Ziswiler status = "okay"; 736a57f224SMarcel Ziswiler}; 746a57f224SMarcel Ziswiler 756a57f224SMarcel Ziswiler/* Verdin QSPI_1 */ 766a57f224SMarcel Ziswiler&flexspi { 776a57f224SMarcel Ziswiler status = "okay"; 786a57f224SMarcel Ziswiler}; 796a57f224SMarcel Ziswiler 809f06926eSStefan Eichenberger&gpio5 { 819f06926eSStefan Eichenberger pinctrl-names = "default"; 829f06926eSStefan Eichenberger pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 839f06926eSStefan Eichenberger}; 849f06926eSStefan Eichenberger 856a57f224SMarcel Ziswiler/* Current measurement into module VCC */ 866a57f224SMarcel Ziswiler&hwmon { 876a57f224SMarcel Ziswiler status = "okay"; 886a57f224SMarcel Ziswiler}; 896a57f224SMarcel Ziswiler 906a57f224SMarcel Ziswiler&hwmon_temp { 916a57f224SMarcel Ziswiler vs-supply = <®_1p8v>; 926a57f224SMarcel Ziswiler status = "okay"; 936a57f224SMarcel Ziswiler}; 946a57f224SMarcel Ziswiler 956a57f224SMarcel Ziswiler&i2c3 { 966a57f224SMarcel Ziswiler status = "okay"; 976a57f224SMarcel Ziswiler}; 986a57f224SMarcel Ziswiler 996a57f224SMarcel Ziswiler/* Verdin I2C_1 */ 1006a57f224SMarcel Ziswiler&i2c4 { 1016a57f224SMarcel Ziswiler status = "okay"; 1026a57f224SMarcel Ziswiler 1036a57f224SMarcel Ziswiler /* Audio Codec */ 1046a57f224SMarcel Ziswiler wm8904_1a: audio-codec@1a { 1056a57f224SMarcel Ziswiler compatible = "wlf,wm8904"; 1066a57f224SMarcel Ziswiler AVDD-supply = <®_3p3v>; 1076a57f224SMarcel Ziswiler clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; 1086a57f224SMarcel Ziswiler clock-names = "mclk"; 1096a57f224SMarcel Ziswiler CPVDD-supply = <®_3p3v>; 1106a57f224SMarcel Ziswiler DBVDD-supply = <®_3p3v>; 1116a57f224SMarcel Ziswiler DCVDD-supply = <®_3p3v>; 1126a57f224SMarcel Ziswiler MICVDD-supply = <®_3p3v>; 1136a57f224SMarcel Ziswiler reg = <0x1a>; 1146a57f224SMarcel Ziswiler #sound-dai-cells = <0>; 1156a57f224SMarcel Ziswiler }; 1166a57f224SMarcel Ziswiler}; 1176a57f224SMarcel Ziswiler 1186a57f224SMarcel Ziswiler/* Verdin PCIE_1 */ 1196a57f224SMarcel Ziswiler&pcie0 { 1201288f819SStefan Eichenberger vpcie-supply = <®_pcie>; 1216a57f224SMarcel Ziswiler status = "okay"; 1226a57f224SMarcel Ziswiler}; 1236a57f224SMarcel Ziswiler 1246a57f224SMarcel Ziswiler&pcie_phy { 1256a57f224SMarcel Ziswiler status = "okay"; 1266a57f224SMarcel Ziswiler}; 1276a57f224SMarcel Ziswiler 1286a57f224SMarcel Ziswiler/* Verdin PWM_3_DSI */ 1296a57f224SMarcel Ziswiler&pwm1 { 1306a57f224SMarcel Ziswiler status = "okay"; 1316a57f224SMarcel Ziswiler}; 1326a57f224SMarcel Ziswiler 1336a57f224SMarcel Ziswiler/* Verdin PWM_1 */ 1346a57f224SMarcel Ziswiler&pwm2 { 1356a57f224SMarcel Ziswiler status = "okay"; 1366a57f224SMarcel Ziswiler}; 1376a57f224SMarcel Ziswiler 1386a57f224SMarcel Ziswiler/* Verdin PWM_2 */ 1396a57f224SMarcel Ziswiler&pwm3 { 1406a57f224SMarcel Ziswiler status = "okay"; 1416a57f224SMarcel Ziswiler}; 1426a57f224SMarcel Ziswiler 1431288f819SStefan Eichenberger/* We support turning off sleep moci on Dahlia */ 1441288f819SStefan Eichenberger®_force_sleep_moci { 1451288f819SStefan Eichenberger status = "disabled"; 1461288f819SStefan Eichenberger}; 1471288f819SStefan Eichenberger 148473b34b8SMarcel Ziswiler/* Verdin I2S_1 */ 1496a57f224SMarcel Ziswiler&sai2 { 1506a57f224SMarcel Ziswiler status = "okay"; 1516a57f224SMarcel Ziswiler}; 1526a57f224SMarcel Ziswiler 1536a57f224SMarcel Ziswiler/* Verdin UART_3 */ 1546a57f224SMarcel Ziswiler&uart1 { 1556a57f224SMarcel Ziswiler status = "okay"; 1566a57f224SMarcel Ziswiler}; 1576a57f224SMarcel Ziswiler 1586a57f224SMarcel Ziswiler/* Verdin UART_1 */ 1596a57f224SMarcel Ziswiler&uart2 { 1606a57f224SMarcel Ziswiler status = "okay"; 1616a57f224SMarcel Ziswiler}; 1626a57f224SMarcel Ziswiler 1636a57f224SMarcel Ziswiler/* Verdin UART_2 */ 1646a57f224SMarcel Ziswiler&uart3 { 1656a57f224SMarcel Ziswiler status = "okay"; 1666a57f224SMarcel Ziswiler}; 1676a57f224SMarcel Ziswiler 1686a57f224SMarcel Ziswiler/* Verdin USB_1 */ 1696a57f224SMarcel Ziswiler&usbotg1 { 1704763009eSPhilippe Schenker disable-over-current; 1716a57f224SMarcel Ziswiler status = "okay"; 1726a57f224SMarcel Ziswiler}; 1736a57f224SMarcel Ziswiler 1746a57f224SMarcel Ziswiler/* Verdin USB_2 */ 1756a57f224SMarcel Ziswiler&usbotg2 { 1761288f819SStefan Eichenberger #address-cells = <1>; 1771288f819SStefan Eichenberger #size-cells = <0>; 1784763009eSPhilippe Schenker disable-over-current; 1796a57f224SMarcel Ziswiler status = "okay"; 1801288f819SStefan Eichenberger 1811288f819SStefan Eichenberger usb-hub@1 { 1821288f819SStefan Eichenberger compatible = "usb424,2744"; 1831288f819SStefan Eichenberger reg = <1>; 1841288f819SStefan Eichenberger vdd-supply = <®_usb_hub>; 1851288f819SStefan Eichenberger }; 1866a57f224SMarcel Ziswiler}; 1876a57f224SMarcel Ziswiler 1886a57f224SMarcel Ziswiler/* Verdin SD_1 */ 1896a57f224SMarcel Ziswiler&usdhc2 { 1906a57f224SMarcel Ziswiler status = "okay"; 1916a57f224SMarcel Ziswiler}; 192