1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7904 i.MX8MM board"; 17 compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm"; 18 19 aliases { 20 rtc0 = &gsc_rtc; 21 rtc1 = &snvs_rtc; 22 }; 23 24 chosen { 25 stdout-path = &uart2; 26 }; 27 28 memory@40000000 { 29 device_type = "memory"; 30 reg = <0x0 0x40000000 0 0x80000000>; 31 }; 32 33 gpio-keys { 34 compatible = "gpio-keys"; 35 36 key-0 { 37 label = "user_pb"; 38 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 39 linux,code = <BTN_0>; 40 }; 41 42 key-1 { 43 label = "user_pb1x"; 44 linux,code = <BTN_1>; 45 interrupt-parent = <&gsc>; 46 interrupts = <0>; 47 }; 48 49 key-2 { 50 label = "key_erased"; 51 linux,code = <BTN_2>; 52 interrupt-parent = <&gsc>; 53 interrupts = <1>; 54 }; 55 56 key-3 { 57 label = "eeprom_wp"; 58 linux,code = <BTN_3>; 59 interrupt-parent = <&gsc>; 60 interrupts = <2>; 61 }; 62 63 key-4 { 64 label = "switch_hold"; 65 linux,code = <BTN_5>; 66 interrupt-parent = <&gsc>; 67 interrupts = <7>; 68 }; 69 }; 70 71 led-controller { 72 compatible = "gpio-leds"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio_leds>; 75 76 led-0 { 77 function = LED_FUNCTION_STATUS; 78 color = <LED_COLOR_ID_GREEN>; 79 label = "led01_grn"; 80 gpios = <&gpioled 0 GPIO_ACTIVE_LOW>; 81 default-state = "off"; 82 }; 83 84 led-1 { 85 function = LED_FUNCTION_STATUS; 86 color = <LED_COLOR_ID_YELLOW>; 87 label = "led01_yel"; 88 gpios = <&gpioled 1 GPIO_ACTIVE_LOW>; 89 default-state = "off"; 90 }; 91 92 led-2 { 93 function = LED_FUNCTION_STATUS; 94 color = <LED_COLOR_ID_GREEN>; 95 label = "led02_grn"; 96 gpios = <&gpioled 2 GPIO_ACTIVE_LOW>; 97 default-state = "off"; 98 }; 99 100 led-3 { 101 function = LED_FUNCTION_STATUS; 102 color = <LED_COLOR_ID_YELLOW>; 103 label = "led02_yel"; 104 gpios = <&gpioled 3 GPIO_ACTIVE_LOW>; 105 default-state = "off"; 106 }; 107 108 led-4 { 109 function = LED_FUNCTION_STATUS; 110 color = <LED_COLOR_ID_GREEN>; 111 label = "led03_grn"; 112 gpios = <&gpioled 4 GPIO_ACTIVE_LOW>; 113 default-state = "off"; 114 }; 115 116 led-5 { 117 function = LED_FUNCTION_STATUS; 118 color = <LED_COLOR_ID_YELLOW>; 119 label = "led03_yel"; 120 gpios = <&gpioled 5 GPIO_ACTIVE_LOW>; 121 default-state = "off"; 122 }; 123 124 led-6 { 125 function = LED_FUNCTION_STATUS; 126 color = <LED_COLOR_ID_GREEN>; 127 label = "led04_grn"; 128 gpios = <&gpioled 6 GPIO_ACTIVE_LOW>; 129 default-state = "off"; 130 }; 131 132 led-7 { 133 function = LED_FUNCTION_STATUS; 134 color = <LED_COLOR_ID_YELLOW>; 135 label = "led04_yel"; 136 gpios = <&gpioled 7 GPIO_ACTIVE_LOW>; 137 default-state = "off"; 138 }; 139 140 led-8 { 141 function = LED_FUNCTION_STATUS; 142 color = <LED_COLOR_ID_GREEN>; 143 label = "led05_grn"; 144 gpios = <&gpioled 8 GPIO_ACTIVE_LOW>; 145 default-state = "off"; 146 }; 147 148 led-9 { 149 function = LED_FUNCTION_STATUS; 150 color = <LED_COLOR_ID_YELLOW>; 151 label = "led05_yel"; 152 gpios = <&gpioled 9 GPIO_ACTIVE_LOW>; 153 default-state = "off"; 154 }; 155 156 led-10 { 157 function = LED_FUNCTION_STATUS; 158 color = <LED_COLOR_ID_GREEN>; 159 label = "led06_grn"; 160 gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 161 default-state = "off"; 162 }; 163 164 led-11 { 165 function = LED_FUNCTION_STATUS; 166 color = <LED_COLOR_ID_RED>; 167 label = "led06_red"; 168 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 169 default-state = "off"; 170 }; 171 172 led-12 { 173 function = LED_FUNCTION_STATUS; 174 color = <LED_COLOR_ID_GREEN>; 175 label = "led07_grn"; 176 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 177 default-state = "off"; 178 }; 179 180 led-13 { 181 function = LED_FUNCTION_STATUS; 182 color = <LED_COLOR_ID_RED>; 183 label = "led07_red"; 184 gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 185 default-state = "off"; 186 }; 187 188 led-14 { 189 function = LED_FUNCTION_STATUS; 190 color = <LED_COLOR_ID_GREEN>; 191 label = "led08_grn"; 192 gpios = <&gpioled 10 GPIO_ACTIVE_LOW>; 193 default-state = "off"; 194 }; 195 196 led-15 { 197 function = LED_FUNCTION_STATUS; 198 color = <LED_COLOR_ID_YELLOW>; 199 label = "led08_yel"; 200 gpios = <&gpioled 11 GPIO_ACTIVE_LOW>; 201 default-state = "off"; 202 }; 203 204 led-16 { 205 function = LED_FUNCTION_STATUS; 206 color = <LED_COLOR_ID_GREEN>; 207 label = "led09_grn"; 208 gpios = <&gpioled 12 GPIO_ACTIVE_LOW>; 209 default-state = "off"; 210 }; 211 212 led-17 { 213 function = LED_FUNCTION_STATUS; 214 color = <LED_COLOR_ID_YELLOW>; 215 label = "led09_yel"; 216 gpios = <&gpioled 13 GPIO_ACTIVE_LOW>; 217 default-state = "off"; 218 }; 219 220 led-18 { 221 function = LED_FUNCTION_STATUS; 222 color = <LED_COLOR_ID_GREEN>; 223 label = "led10_grn"; 224 gpios = <&gpioled 14 GPIO_ACTIVE_LOW>; 225 default-state = "off"; 226 }; 227 228 led-19 { 229 function = LED_FUNCTION_STATUS; 230 color = <LED_COLOR_ID_YELLOW>; 231 label = "led10_yel"; 232 gpios = <&gpioled 15 GPIO_ACTIVE_LOW>; 233 default-state = "off"; 234 }; 235 }; 236 237 pcie0_refclk: pcie0-refclk { 238 compatible = "fixed-clock"; 239 #clock-cells = <0>; 240 clock-frequency = <100000000>; 241 }; 242 243 reg_3p3v: regulator-3p3v { 244 compatible = "regulator-fixed"; 245 regulator-name = "3P3V"; 246 regulator-min-microvolt = <3300000>; 247 regulator-max-microvolt = <3300000>; 248 regulator-always-on; 249 }; 250}; 251 252&A53_0 { 253 cpu-supply = <&buck2>; 254}; 255 256&A53_1 { 257 cpu-supply = <&buck2>; 258}; 259 260&A53_2 { 261 cpu-supply = <&buck2>; 262}; 263 264&A53_3 { 265 cpu-supply = <&buck2>; 266}; 267 268&ddrc { 269 operating-points-v2 = <&ddrc_opp_table>; 270 271 ddrc_opp_table: opp-table { 272 compatible = "operating-points-v2"; 273 274 opp-25000000 { 275 opp-hz = /bits/ 64 <25000000>; 276 }; 277 278 opp-100000000 { 279 opp-hz = /bits/ 64 <100000000>; 280 }; 281 282 opp-750000000 { 283 opp-hz = /bits/ 64 <750000000>; 284 }; 285 }; 286}; 287 288&fec1 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_fec1>; 291 phy-mode = "rgmii-id"; 292 phy-handle = <ðphy0>; 293 local-mac-address = [00 00 00 00 00 00]; 294 status = "okay"; 295 296 mdio { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 ethphy0: ethernet-phy@0 { 301 compatible = "ethernet-phy-ieee802.3-c22"; 302 reg = <0>; 303 }; 304 }; 305}; 306 307&gpio1 { 308 gpio-line-names = "", "", "", "", "", "", "", "", 309 "", "", "", "", "rs232_en#", "", "", "", 310 "", "", "", "", "", "", "", "", 311 "", "", "", "", "", "", "", ""; 312}; 313 314&gpio5 { 315 gpio-line-names = "", "", "", "", "", "", "", "", 316 "", "", "", "", "pci_wdis#", "", "", "", 317 "", "", "", "", "", "", "", "", 318 "", "", "", "", "", "", "", ""; 319}; 320 321&i2c1 { 322 clock-frequency = <100000>; 323 pinctrl-names = "default", "gpio"; 324 pinctrl-0 = <&pinctrl_i2c1>; 325 pinctrl-1 = <&pinctrl_i2c1_gpio>; 326 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 327 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 328 status = "okay"; 329 330 gsc: gsc@20 { 331 compatible = "gw,gsc"; 332 reg = <0x20>; 333 pinctrl-0 = <&pinctrl_gsc>; 334 interrupt-parent = <&gpio4>; 335 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 336 interrupt-controller; 337 #interrupt-cells = <1>; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 341 adc { 342 compatible = "gw,gsc-adc"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 channel@6 { 347 gw,mode = <0>; 348 reg = <0x06>; 349 label = "temp"; 350 }; 351 352 channel@82 { 353 gw,mode = <2>; 354 reg = <0x82>; 355 label = "vin"; 356 gw,voltage-divider-ohms = <22100 1000>; 357 gw,voltage-offset-microvolt = <700000>; 358 }; 359 360 channel@84 { 361 gw,mode = <2>; 362 reg = <0x84>; 363 label = "vdd_5p0"; 364 gw,voltage-divider-ohms = <10000 10000>; 365 }; 366 367 channel@86 { 368 gw,mode = <2>; 369 reg = <0x86>; 370 label = "vdd_3p3"; 371 gw,voltage-divider-ohms = <10000 10000>; 372 }; 373 374 channel@88 { 375 gw,mode = <2>; 376 reg = <0x88>; 377 label = "vdd_0p9"; 378 }; 379 380 channel@8c { 381 gw,mode = <2>; 382 reg = <0x8c>; 383 label = "vdd_soc"; 384 }; 385 386 channel@8e { 387 gw,mode = <2>; 388 reg = <0x8e>; 389 label = "vdd_arm"; 390 }; 391 392 channel@90 { 393 gw,mode = <2>; 394 reg = <0x90>; 395 label = "vdd_1p8"; 396 }; 397 398 channel@92 { 399 gw,mode = <2>; 400 reg = <0x92>; 401 label = "vdd_dram"; 402 }; 403 404 channel@a2 { 405 gw,mode = <2>; 406 reg = <0xa2>; 407 label = "vdd_gsc"; 408 gw,voltage-divider-ohms = <10000 10000>; 409 }; 410 }; 411 }; 412 413 gpio: gpio@23 { 414 compatible = "nxp,pca9555"; 415 reg = <0x23>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-parent = <&gsc>; 419 interrupts = <4>; 420 }; 421 422 eeprom@50 { 423 compatible = "atmel,24c02"; 424 reg = <0x50>; 425 pagesize = <16>; 426 }; 427 428 eeprom@51 { 429 compatible = "atmel,24c02"; 430 reg = <0x51>; 431 pagesize = <16>; 432 }; 433 434 eeprom@52 { 435 compatible = "atmel,24c02"; 436 reg = <0x52>; 437 pagesize = <16>; 438 }; 439 440 eeprom@53 { 441 compatible = "atmel,24c02"; 442 reg = <0x53>; 443 pagesize = <16>; 444 }; 445 446 gsc_rtc: rtc@68 { 447 compatible = "dallas,ds1672"; 448 reg = <0x68>; 449 }; 450}; 451 452&i2c2 { 453 clock-frequency = <400000>; 454 pinctrl-names = "default", "gpio"; 455 pinctrl-0 = <&pinctrl_i2c2>; 456 pinctrl-1 = <&pinctrl_i2c2_gpio>; 457 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 458 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 459 status = "okay"; 460 461 pmic@4b { 462 compatible = "rohm,bd71847"; 463 reg = <0x4b>; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_pmic>; 466 interrupt-parent = <&gpio3>; 467 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 468 rohm,reset-snvs-powered; 469 #clock-cells = <0>; 470 clocks = <&osc_32k>; 471 clock-output-names = "clk-32k-out"; 472 473 regulators { 474 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 475 BUCK1 { 476 regulator-name = "buck1"; 477 regulator-min-microvolt = <700000>; 478 regulator-max-microvolt = <1300000>; 479 regulator-boot-on; 480 regulator-always-on; 481 regulator-ramp-delay = <1250>; 482 }; 483 484 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 485 buck2: BUCK2 { 486 regulator-name = "buck2"; 487 regulator-min-microvolt = <700000>; 488 regulator-max-microvolt = <1300000>; 489 regulator-boot-on; 490 regulator-always-on; 491 regulator-ramp-delay = <1250>; 492 rohm,dvs-run-voltage = <1000000>; 493 rohm,dvs-idle-voltage = <900000>; 494 }; 495 496 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 497 BUCK3 { 498 regulator-name = "buck3"; 499 regulator-min-microvolt = <700000>; 500 regulator-max-microvolt = <1350000>; 501 regulator-boot-on; 502 regulator-always-on; 503 }; 504 505 /* vdd_3p3 */ 506 BUCK4 { 507 regulator-name = "buck4"; 508 regulator-min-microvolt = <3000000>; 509 regulator-max-microvolt = <3300000>; 510 regulator-boot-on; 511 regulator-always-on; 512 }; 513 514 /* vdd_1p8 */ 515 BUCK5 { 516 regulator-name = "buck5"; 517 regulator-min-microvolt = <1605000>; 518 regulator-max-microvolt = <1995000>; 519 regulator-boot-on; 520 regulator-always-on; 521 }; 522 523 /* vdd_dram */ 524 BUCK6 { 525 regulator-name = "buck6"; 526 regulator-min-microvolt = <800000>; 527 regulator-max-microvolt = <1400000>; 528 regulator-boot-on; 529 regulator-always-on; 530 }; 531 532 /* nvcc_snvs_1p8 */ 533 LDO1 { 534 regulator-name = "ldo1"; 535 regulator-min-microvolt = <1600000>; 536 regulator-max-microvolt = <1900000>; 537 regulator-boot-on; 538 regulator-always-on; 539 }; 540 541 /* vdd_snvs_0p8 */ 542 LDO2 { 543 regulator-name = "ldo2"; 544 regulator-min-microvolt = <800000>; 545 regulator-max-microvolt = <900000>; 546 regulator-boot-on; 547 regulator-always-on; 548 }; 549 550 /* vdda_1p8 */ 551 LDO3 { 552 regulator-name = "ldo3"; 553 regulator-min-microvolt = <1800000>; 554 regulator-max-microvolt = <3300000>; 555 regulator-boot-on; 556 regulator-always-on; 557 }; 558 559 LDO4 { 560 regulator-name = "ldo4"; 561 regulator-min-microvolt = <900000>; 562 regulator-max-microvolt = <1800000>; 563 regulator-boot-on; 564 regulator-always-on; 565 }; 566 567 LDO6 { 568 regulator-name = "ldo6"; 569 regulator-min-microvolt = <900000>; 570 regulator-max-microvolt = <1800000>; 571 regulator-boot-on; 572 regulator-always-on; 573 }; 574 }; 575 }; 576}; 577 578&i2c3 { 579 clock-frequency = <400000>; 580 pinctrl-names = "default", "gpio"; 581 pinctrl-0 = <&pinctrl_i2c3>; 582 pinctrl-1 = <&pinctrl_i2c3_gpio>; 583 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 584 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 585 status = "okay"; 586 587 accelerometer@19 { 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_accel>; 590 compatible = "st,lis2de12"; 591 reg = <0x19>; 592 st,drdy-int-pin = <1>; 593 interrupt-parent = <&gpio1>; 594 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 595 }; 596}; 597 598&i2c4 { 599 clock-frequency = <400000>; 600 pinctrl-names = "default", "gpio"; 601 pinctrl-0 = <&pinctrl_i2c4>; 602 pinctrl-1 = <&pinctrl_i2c4_gpio>; 603 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 604 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 605 status = "okay"; 606 607 gpioled: gpio@27 { 608 compatible = "nxp,pca9555"; 609 reg = <0x27>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 }; 613}; 614 615&pcie_phy { 616 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 617 fsl,clkreq-unsupported; 618 clocks = <&pcie0_refclk>; 619 clock-names = "ref"; 620 status = "okay"; 621}; 622 623&pcie0 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_pcie0>; 626 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; 627 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 628 <&clk IMX8MM_CLK_PCIE1_AUX>; 629 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 630 <&clk IMX8MM_CLK_PCIE1_CTRL>; 631 assigned-clock-rates = <10000000>, <250000000>; 632 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 633 <&clk IMX8MM_SYS_PLL2_250M>; 634 status = "okay"; 635}; 636 637&disp_blk_ctrl { 638 status = "disabled"; 639}; 640 641&pgc_mipi { 642 status = "disabled"; 643}; 644 645/* off-board RS232 */ 646&uart1 { 647 pinctrl-names = "default"; 648 pinctrl-0 = <&pinctrl_uart1>; 649 cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 650 rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; 651 status = "okay"; 652}; 653 654/* console */ 655&uart2 { 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pinctrl_uart2>; 658 status = "okay"; 659}; 660 661&usbotg1 { 662 dr_mode = "host"; 663 disable-over-current; 664 status = "okay"; 665}; 666 667/* microSD */ 668&usdhc2 { 669 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 670 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 671 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 672 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 673 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 674 bus-width = <4>; 675 vmmc-supply = <®_3p3v>; 676 status = "okay"; 677}; 678 679/* eMMC */ 680&usdhc3 { 681 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 682 pinctrl-0 = <&pinctrl_usdhc3>; 683 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 684 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 685 bus-width = <8>; 686 non-removable; 687 status = "okay"; 688}; 689 690&wdog1 { 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_wdog>; 693 fsl,ext-reset-output; 694 status = "okay"; 695}; 696 697&iomuxc { 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pinctrl_hog>; 700 701 pinctrl_hog: hoggrp { 702 fsl,pins = < 703 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ 704 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ 705 >; 706 }; 707 708 pinctrl_accel: accelgrp { 709 fsl,pins = < 710 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 711 >; 712 }; 713 714 pinctrl_fec1: fec1grp { 715 fsl,pins = < 716 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 717 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 718 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 719 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 720 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 721 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 722 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 723 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 724 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 725 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 726 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 727 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 728 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 729 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 730 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ 731 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ 732 >; 733 }; 734 735 pinctrl_gpio_leds: gpioledsgrp { 736 fsl,pins = < 737 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000019 738 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000019 739 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000019 740 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000019 741 >; 742 }; 743 744 pinctrl_gsc: gscgrp { 745 fsl,pins = < 746 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 747 >; 748 }; 749 750 pinctrl_i2c1: i2c1grp { 751 fsl,pins = < 752 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 753 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 754 >; 755 }; 756 757 pinctrl_i2c1_gpio: i2c1gpiogrp { 758 fsl,pins = < 759 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 760 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 761 >; 762 }; 763 764 pinctrl_i2c2: i2c2grp { 765 fsl,pins = < 766 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 767 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 768 >; 769 }; 770 771 pinctrl_i2c2_gpio: i2c2gpiogrp { 772 fsl,pins = < 773 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 774 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 775 >; 776 }; 777 778 pinctrl_i2c3: i2c3grp { 779 fsl,pins = < 780 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 781 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 782 >; 783 }; 784 785 pinctrl_i2c3_gpio: i2c3gpiogrp { 786 fsl,pins = < 787 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 788 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 789 >; 790 }; 791 792 pinctrl_i2c4: i2c4grp { 793 fsl,pins = < 794 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 795 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 796 >; 797 }; 798 799 pinctrl_i2c4_gpio: i2c4gpiogrp { 800 fsl,pins = < 801 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 802 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 803 >; 804 }; 805 806 pinctrl_pcie0: pciegrp { 807 fsl,pins = < 808 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 809 >; 810 }; 811 812 pinctrl_pmic: pmicgrp { 813 fsl,pins = < 814 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 815 >; 816 }; 817 818 pinctrl_uart1: uart1grp { 819 fsl,pins = < 820 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 821 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 822 MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */ 823 MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */ 824 >; 825 }; 826 827 pinctrl_uart2: uart2grp { 828 fsl,pins = < 829 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 830 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 831 >; 832 }; 833 834 pinctrl_usdhc2: usdhc2grp { 835 fsl,pins = < 836 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 837 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 838 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 839 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 840 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 841 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 842 >; 843 }; 844 845 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 846 fsl,pins = < 847 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 848 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 849 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 850 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 851 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 852 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 853 >; 854 }; 855 856 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 857 fsl,pins = < 858 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 859 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 860 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 861 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 862 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 863 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 864 >; 865 }; 866 867 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 868 fsl,pins = < 869 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 870 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 871 >; 872 }; 873 874 pinctrl_usdhc3: usdhc3grp { 875 fsl,pins = < 876 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 877 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 878 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 879 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 880 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 881 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 882 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 883 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 884 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 885 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 886 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 887 >; 888 }; 889 890 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 891 fsl,pins = < 892 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 893 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 894 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 895 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 896 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 897 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 898 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 899 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 900 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 901 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 902 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 903 >; 904 }; 905 906 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 907 fsl,pins = < 908 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 909 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 910 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 911 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 912 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 913 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 914 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 915 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 916 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 917 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 918 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 919 >; 920 }; 921 922 pinctrl_wdog: wdoggrp { 923 fsl,pins = < 924 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 925 >; 926 }; 927}; 928