1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7903 i.MX8MM board"; 17 compatible = "gw,imx8mm-gw7903", "fsl,imx8mm"; 18 19 aliases { 20 ethernet0 = &fec1; 21 rtc0 = &gsc_rtc; 22 rtc1 = &snvs_rtc; 23 usb0 = &usbotg1; 24 }; 25 26 chosen { 27 stdout-path = &uart2; 28 }; 29 30 memory@40000000 { 31 device_type = "memory"; 32 reg = <0x0 0x40000000 0 0x80000000>; 33 }; 34 35 gpio-keys { 36 compatible = "gpio-keys"; 37 38 key-user-pb { 39 label = "user_pb"; 40 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 41 linux,code = <BTN_0>; 42 }; 43 44 key-user-pb1x { 45 label = "user_pb1x"; 46 linux,code = <BTN_1>; 47 interrupt-parent = <&gsc>; 48 interrupts = <0>; 49 }; 50 51 key-erased { 52 label = "key_erased"; 53 linux,code = <BTN_2>; 54 interrupt-parent = <&gsc>; 55 interrupts = <1>; 56 }; 57 58 key-eeprom-wp { 59 label = "eeprom_wp"; 60 linux,code = <BTN_3>; 61 interrupt-parent = <&gsc>; 62 interrupts = <2>; 63 }; 64 65 switch-hold { 66 label = "switch_hold"; 67 linux,code = <BTN_5>; 68 interrupt-parent = <&gsc>; 69 interrupts = <7>; 70 }; 71 }; 72 73 led-controller { 74 compatible = "gpio-leds"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_gpio_leds>; 77 78 led-0 { 79 function = LED_FUNCTION_STATUS; 80 color = <LED_COLOR_ID_RED>; 81 label = "led01_red"; 82 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 83 default-state = "off"; 84 }; 85 86 led-1 { 87 function = LED_FUNCTION_STATUS; 88 color = <LED_COLOR_ID_GREEN>; 89 label = "led01_grn"; 90 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 91 default-state = "off"; 92 }; 93 94 led-2 { 95 function = LED_FUNCTION_STATUS; 96 color = <LED_COLOR_ID_RED>; 97 label = "led02_red"; 98 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 102 led-3 { 103 function = LED_FUNCTION_STATUS; 104 color = <LED_COLOR_ID_GREEN>; 105 label = "led02_grn"; 106 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 107 default-state = "off"; 108 }; 109 110 led-4 { 111 function = LED_FUNCTION_STATUS; 112 color = <LED_COLOR_ID_RED>; 113 label = "led03_red"; 114 gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 115 default-state = "off"; 116 }; 117 118 led-5 { 119 function = LED_FUNCTION_STATUS; 120 color = <LED_COLOR_ID_GREEN>; 121 label = "led03_grn"; 122 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 123 default-state = "off"; 124 }; 125 126 led-6 { 127 function = LED_FUNCTION_STATUS; 128 color = <LED_COLOR_ID_RED>; 129 label = "led04_red"; 130 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 131 default-state = "off"; 132 }; 133 134 led-7 { 135 function = LED_FUNCTION_STATUS; 136 color = <LED_COLOR_ID_GREEN>; 137 label = "led04_grn"; 138 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 139 default-state = "off"; 140 }; 141 142 led-8 { 143 function = LED_FUNCTION_STATUS; 144 color = <LED_COLOR_ID_RED>; 145 label = "led05_red"; 146 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 147 default-state = "off"; 148 }; 149 150 led-9 { 151 function = LED_FUNCTION_STATUS; 152 color = <LED_COLOR_ID_GREEN>; 153 label = "led05_grn"; 154 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; 155 default-state = "off"; 156 }; 157 158 led-a { 159 function = LED_FUNCTION_STATUS; 160 color = <LED_COLOR_ID_RED>; 161 label = "led06_red"; 162 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 166 led-b { 167 function = LED_FUNCTION_STATUS; 168 color = <LED_COLOR_ID_GREEN>; 169 label = "led06_grn"; 170 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 171 default-state = "off"; 172 }; 173 }; 174 175 pcie0_refclk: pcie0-refclk { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <100000000>; 179 }; 180 181 reg_3p3v: regulator-3p3v { 182 compatible = "regulator-fixed"; 183 regulator-name = "3P3V"; 184 regulator-min-microvolt = <3300000>; 185 regulator-max-microvolt = <3300000>; 186 regulator-always-on; 187 }; 188}; 189 190&A53_0 { 191 cpu-supply = <&buck2>; 192}; 193 194&A53_1 { 195 cpu-supply = <&buck2>; 196}; 197 198&A53_2 { 199 cpu-supply = <&buck2>; 200}; 201 202&A53_3 { 203 cpu-supply = <&buck2>; 204}; 205 206&ddrc { 207 operating-points-v2 = <&ddrc_opp_table>; 208 209 ddrc_opp_table: opp-table { 210 compatible = "operating-points-v2"; 211 212 opp-25000000 { 213 opp-hz = /bits/ 64 <25000000>; 214 }; 215 216 opp-100000000 { 217 opp-hz = /bits/ 64 <100000000>; 218 }; 219 220 opp-750000000 { 221 opp-hz = /bits/ 64 <750000000>; 222 }; 223 }; 224}; 225 226&fec1 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_fec1>; 229 phy-mode = "rgmii-id"; 230 phy-handle = <ðphy0>; 231 local-mac-address = [00 00 00 00 00 00]; 232 status = "okay"; 233 234 mdio { 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 ethphy0: ethernet-phy@0 { 239 compatible = "ethernet-phy-ieee802.3-c22"; 240 reg = <0>; 241 rx-internal-delay-ps = <2000>; 242 tx-internal-delay-ps = <2500>; 243 }; 244 }; 245}; 246 247&gpio1 { 248 gpio-line-names = "", "", "", "", "", "", "", "", 249 "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "", 250 "", "", "", "", "", "", "", "", 251 "", "", "", "", "", "", "", ""; 252}; 253 254&gpio2 { 255 gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "", 256 "dig1_out#", "dig1_in", "", "", "", "", "", "", 257 "", "", "", "", "", "", "", "", 258 "", "", "", "", "", "", "", ""; 259}; 260 261&gpio5 { 262 gpio-line-names = "", "", "", "", "", "", "", "sim1_det#", 263 "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "", 264 "", "", "", "", "", "", "", "", 265 "", "", "", "", "", "", "", ""; 266}; 267 268&i2c1 { 269 clock-frequency = <100000>; 270 pinctrl-names = "default", "gpio"; 271 pinctrl-0 = <&pinctrl_i2c1>; 272 pinctrl-1 = <&pinctrl_i2c1_gpio>; 273 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 274 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 275 status = "okay"; 276 277 gsc: gsc@20 { 278 compatible = "gw,gsc"; 279 reg = <0x20>; 280 pinctrl-0 = <&pinctrl_gsc>; 281 interrupt-parent = <&gpio4>; 282 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 283 interrupt-controller; 284 #interrupt-cells = <1>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 adc { 289 compatible = "gw,gsc-adc"; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 293 channel@6 { 294 gw,mode = <0>; 295 reg = <0x06>; 296 label = "temp"; 297 }; 298 299 channel@8 { 300 gw,mode = <3>; 301 reg = <0x08>; 302 label = "vdd_bat"; 303 }; 304 305 channel@82 { 306 gw,mode = <2>; 307 reg = <0x82>; 308 label = "vin"; 309 gw,voltage-divider-ohms = <22100 1000>; 310 gw,voltage-offset-microvolt = <700000>; 311 }; 312 313 channel@84 { 314 gw,mode = <2>; 315 reg = <0x84>; 316 label = "vdd_5p0"; 317 gw,voltage-divider-ohms = <10000 10000>; 318 }; 319 320 channel@86 { 321 gw,mode = <2>; 322 reg = <0x86>; 323 label = "vdd_3p3"; 324 gw,voltage-divider-ohms = <10000 10000>; 325 }; 326 327 channel@88 { 328 gw,mode = <2>; 329 reg = <0x88>; 330 label = "vdd_0p9"; 331 }; 332 333 channel@8c { 334 gw,mode = <2>; 335 reg = <0x8c>; 336 label = "vdd_soc"; 337 }; 338 339 channel@8e { 340 gw,mode = <2>; 341 reg = <0x8e>; 342 label = "vdd_arm"; 343 }; 344 345 channel@90 { 346 gw,mode = <2>; 347 reg = <0x90>; 348 label = "vdd_1p8"; 349 }; 350 351 channel@92 { 352 gw,mode = <2>; 353 reg = <0x92>; 354 label = "vdd_dram"; 355 }; 356 357 channel@a2 { 358 gw,mode = <2>; 359 reg = <0xa2>; 360 label = "vdd_gsc"; 361 gw,voltage-divider-ohms = <10000 10000>; 362 }; 363 }; 364 }; 365 366 gpio: gpio@23 { 367 compatible = "nxp,pca9555"; 368 reg = <0x23>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-parent = <&gsc>; 372 interrupts = <4>; 373 }; 374 375 eeprom@50 { 376 compatible = "atmel,24c02"; 377 reg = <0x50>; 378 pagesize = <16>; 379 }; 380 381 eeprom@51 { 382 compatible = "atmel,24c02"; 383 reg = <0x51>; 384 pagesize = <16>; 385 }; 386 387 eeprom@52 { 388 compatible = "atmel,24c02"; 389 reg = <0x52>; 390 pagesize = <16>; 391 }; 392 393 eeprom@53 { 394 compatible = "atmel,24c02"; 395 reg = <0x53>; 396 pagesize = <16>; 397 }; 398 399 gsc_rtc: rtc@68 { 400 compatible = "dallas,ds1672"; 401 reg = <0x68>; 402 }; 403}; 404 405&i2c2 { 406 clock-frequency = <400000>; 407 pinctrl-names = "default", "gpio"; 408 pinctrl-0 = <&pinctrl_i2c2>; 409 pinctrl-1 = <&pinctrl_i2c2_gpio>; 410 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 411 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 412 status = "okay"; 413 414 pmic@4b { 415 compatible = "rohm,bd71847"; 416 reg = <0x4b>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_pmic>; 419 interrupt-parent = <&gpio3>; 420 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 421 rohm,reset-snvs-powered; 422 #clock-cells = <0>; 423 clocks = <&osc_32k>; 424 clock-output-names = "clk-32k-out"; 425 426 regulators { 427 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 428 BUCK1 { 429 regulator-name = "buck1"; 430 regulator-min-microvolt = <700000>; 431 regulator-max-microvolt = <1300000>; 432 regulator-boot-on; 433 regulator-always-on; 434 regulator-ramp-delay = <1250>; 435 }; 436 437 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 438 buck2: BUCK2 { 439 regulator-name = "buck2"; 440 regulator-min-microvolt = <700000>; 441 regulator-max-microvolt = <1300000>; 442 regulator-boot-on; 443 regulator-always-on; 444 regulator-ramp-delay = <1250>; 445 rohm,dvs-run-voltage = <1000000>; 446 rohm,dvs-idle-voltage = <900000>; 447 }; 448 449 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 450 BUCK3 { 451 regulator-name = "buck3"; 452 regulator-min-microvolt = <700000>; 453 regulator-max-microvolt = <1350000>; 454 regulator-boot-on; 455 regulator-always-on; 456 }; 457 458 /* vdd_3p3 */ 459 BUCK4 { 460 regulator-name = "buck4"; 461 regulator-min-microvolt = <3000000>; 462 regulator-max-microvolt = <3300000>; 463 regulator-boot-on; 464 regulator-always-on; 465 }; 466 467 /* vdd_1p8 */ 468 BUCK5 { 469 regulator-name = "buck5"; 470 regulator-min-microvolt = <1605000>; 471 regulator-max-microvolt = <1995000>; 472 regulator-boot-on; 473 regulator-always-on; 474 }; 475 476 /* vdd_dram */ 477 BUCK6 { 478 regulator-name = "buck6"; 479 regulator-min-microvolt = <800000>; 480 regulator-max-microvolt = <1400000>; 481 regulator-boot-on; 482 regulator-always-on; 483 }; 484 485 /* nvcc_snvs_1p8 */ 486 LDO1 { 487 regulator-name = "ldo1"; 488 regulator-min-microvolt = <1600000>; 489 regulator-max-microvolt = <1900000>; 490 regulator-boot-on; 491 regulator-always-on; 492 }; 493 494 /* vdd_snvs_0p8 */ 495 LDO2 { 496 regulator-name = "ldo2"; 497 regulator-min-microvolt = <800000>; 498 regulator-max-microvolt = <900000>; 499 regulator-boot-on; 500 regulator-always-on; 501 }; 502 503 /* vdda_1p8 */ 504 LDO3 { 505 regulator-name = "ldo3"; 506 regulator-min-microvolt = <1800000>; 507 regulator-max-microvolt = <3300000>; 508 regulator-boot-on; 509 regulator-always-on; 510 }; 511 512 LDO4 { 513 regulator-name = "ldo4"; 514 regulator-min-microvolt = <900000>; 515 regulator-max-microvolt = <1800000>; 516 regulator-boot-on; 517 regulator-always-on; 518 }; 519 520 LDO6 { 521 regulator-name = "ldo6"; 522 regulator-min-microvolt = <900000>; 523 regulator-max-microvolt = <1800000>; 524 regulator-boot-on; 525 regulator-always-on; 526 }; 527 }; 528 }; 529}; 530 531&i2c3 { 532 clock-frequency = <400000>; 533 pinctrl-names = "default", "gpio"; 534 pinctrl-0 = <&pinctrl_i2c3>; 535 pinctrl-1 = <&pinctrl_i2c3_gpio>; 536 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 537 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 538 status = "okay"; 539 540 accelerometer@19 { 541 pinctrl-names = "default"; 542 pinctrl-0 = <&pinctrl_accel>; 543 compatible = "st,lis2de12"; 544 reg = <0x19>; 545 st,drdy-int-pin = <1>; 546 interrupt-parent = <&gpio1>; 547 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 548 }; 549}; 550 551&pcie_phy { 552 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 553 fsl,clkreq-unsupported; 554 clocks = <&pcie0_refclk>; 555 clock-names = "ref"; 556 status = "okay"; 557}; 558 559&pcie0 { 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_pcie0>; 562 reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; 563 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 564 <&clk IMX8MM_CLK_PCIE1_AUX>; 565 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 566 <&clk IMX8MM_CLK_PCIE1_CTRL>; 567 assigned-clock-rates = <10000000>, <250000000>; 568 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 569 <&clk IMX8MM_SYS_PLL2_250M>; 570 status = "okay"; 571}; 572 573&disp_blk_ctrl { 574 status = "disabled"; 575}; 576 577&pgc_mipi { 578 status = "disabled"; 579}; 580 581/* off-board RS232/RS485/RS422 */ 582&uart1 { 583 pinctrl-names = "default"; 584 pinctrl-0 = <&pinctrl_uart1>; 585 cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 586 rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 587 dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 588 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 589 dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; 590 status = "okay"; 591}; 592 593/* console */ 594&uart2 { 595 pinctrl-names = "default"; 596 pinctrl-0 = <&pinctrl_uart2>; 597 status = "okay"; 598}; 599 600&usbotg1 { 601 dr_mode = "host"; 602 disable-over-current; 603 status = "okay"; 604}; 605 606/* microSD */ 607&usdhc2 { 608 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 609 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 610 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 611 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 612 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 613 bus-width = <4>; 614 vmmc-supply = <®_3p3v>; 615 status = "okay"; 616}; 617 618/* eMMC */ 619&usdhc3 { 620 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 621 pinctrl-0 = <&pinctrl_usdhc3>; 622 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 623 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 624 bus-width = <8>; 625 non-removable; 626 status = "okay"; 627}; 628 629&wdog1 { 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pinctrl_wdog>; 632 fsl,ext-reset-output; 633 status = "okay"; 634}; 635 636&iomuxc { 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pinctrl_hog>; 639 640 pinctrl_hog: hoggrp { 641 fsl,pins = < 642 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */ 643 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */ 644 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ 645 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ 646 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ 647 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */ 648 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x40000041 /* DIG2_CTL */ 649 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ 650 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ 651 MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ 652 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */ 653 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */ 654 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ 655 >; 656 }; 657 658 pinctrl_accel: accelgrp { 659 fsl,pins = < 660 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 661 >; 662 }; 663 664 pinctrl_fec1: fec1grp { 665 fsl,pins = < 666 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 667 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 668 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 669 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 670 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 671 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 672 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 673 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 674 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 675 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 676 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 677 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 678 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 679 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 680 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ 681 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ 682 >; 683 }; 684 685 pinctrl_gsc: gscgrp { 686 fsl,pins = < 687 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 688 >; 689 }; 690 691 pinctrl_i2c1: i2c1grp { 692 fsl,pins = < 693 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 694 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 695 >; 696 }; 697 698 pinctrl_i2c1_gpio: i2c1gpiogrp { 699 fsl,pins = < 700 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 701 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 702 >; 703 }; 704 705 pinctrl_i2c2: i2c2grp { 706 fsl,pins = < 707 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 708 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 709 >; 710 }; 711 712 pinctrl_i2c2_gpio: i2c2gpiogrp { 713 fsl,pins = < 714 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 715 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 716 >; 717 }; 718 719 pinctrl_i2c3: i2c3grp { 720 fsl,pins = < 721 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 722 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 723 >; 724 }; 725 726 pinctrl_i2c3_gpio: i2c3gpiogrp { 727 fsl,pins = < 728 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 729 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 730 >; 731 }; 732 733 pinctrl_gpio_leds: gpioledgrp { 734 fsl,pins = < 735 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 736 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 737 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 738 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 739 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 740 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 741 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 742 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 743 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 744 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 745 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 746 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 747 >; 748 }; 749 750 pinctrl_pcie0: pciegrp { 751 fsl,pins = < 752 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 753 >; 754 }; 755 756 pinctrl_pmic: pmicgrp { 757 fsl,pins = < 758 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 759 >; 760 }; 761 762 pinctrl_uart1: uart1grp { 763 fsl,pins = < 764 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 765 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 766 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 767 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 768 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 769 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140 770 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 771 >; 772 }; 773 774 pinctrl_uart2: uart2grp { 775 fsl,pins = < 776 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 777 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 778 >; 779 }; 780 781 pinctrl_usdhc2: usdhc2grp { 782 fsl,pins = < 783 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 784 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 785 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 786 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 787 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 788 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 789 >; 790 }; 791 792 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 793 fsl,pins = < 794 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 795 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 796 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 797 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 798 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 799 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 800 >; 801 }; 802 803 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 804 fsl,pins = < 805 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 806 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 807 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 808 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 809 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 810 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 811 >; 812 }; 813 814 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 815 fsl,pins = < 816 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 817 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 818 >; 819 }; 820 821 pinctrl_usdhc3: usdhc3grp { 822 fsl,pins = < 823 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 824 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 825 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 826 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 827 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 828 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 829 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 830 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 831 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 832 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 833 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 834 >; 835 }; 836 837 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 838 fsl,pins = < 839 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 840 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 841 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 842 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 843 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 844 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 845 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 846 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 847 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 848 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 849 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 850 >; 851 }; 852 853 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 854 fsl,pins = < 855 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 856 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 857 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 858 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 859 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 860 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 861 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 862 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 863 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 864 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 865 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 866 >; 867 }; 868 869 pinctrl_wdog: wdoggrp { 870 fsl,pins = < 871 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 872 >; 873 }; 874}; 875