1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-imx8-pcie.h> 13 14#include "imx8mm.dtsi" 15 16/ { 17 model = "Gateworks Venice GW7902 i.MX8MM board"; 18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; 19 20 aliases { 21 ethernet1 = ð1; 22 rtc0 = &gsc_rtc; 23 rtc1 = &snvs_rtc; 24 usb0 = &usbotg1; 25 usb1 = &usbotg2; 26 }; 27 28 chosen { 29 stdout-path = &uart2; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0x80000000>; 35 }; 36 37 can20m: can20m { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <20000000>; 41 clock-output-names = "can20m"; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 47 key-user-pb { 48 label = "user_pb"; 49 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 50 linux,code = <BTN_0>; 51 }; 52 53 key-user-pb1x { 54 label = "user_pb1x"; 55 linux,code = <BTN_1>; 56 interrupt-parent = <&gsc>; 57 interrupts = <0>; 58 }; 59 60 key-erased { 61 label = "key_erased"; 62 linux,code = <BTN_2>; 63 interrupt-parent = <&gsc>; 64 interrupts = <1>; 65 }; 66 67 key-eeprom-wp { 68 label = "eeprom_wp"; 69 linux,code = <BTN_3>; 70 interrupt-parent = <&gsc>; 71 interrupts = <2>; 72 }; 73 74 key-tamper { 75 label = "tamper"; 76 linux,code = <BTN_4>; 77 interrupt-parent = <&gsc>; 78 interrupts = <5>; 79 }; 80 81 switch-hold { 82 label = "switch_hold"; 83 linux,code = <BTN_5>; 84 interrupt-parent = <&gsc>; 85 interrupts = <7>; 86 }; 87 }; 88 89 led-controller { 90 compatible = "gpio-leds"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_gpio_leds>; 93 94 led-0 { 95 function = LED_FUNCTION_STATUS; 96 color = <LED_COLOR_ID_GREEN>; 97 label = "panel1"; 98 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 99 default-state = "off"; 100 }; 101 102 led-1 { 103 function = LED_FUNCTION_STATUS; 104 color = <LED_COLOR_ID_GREEN>; 105 label = "panel2"; 106 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 107 default-state = "off"; 108 }; 109 110 led-2 { 111 function = LED_FUNCTION_STATUS; 112 color = <LED_COLOR_ID_GREEN>; 113 label = "panel3"; 114 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 115 default-state = "off"; 116 }; 117 118 led-3 { 119 function = LED_FUNCTION_STATUS; 120 color = <LED_COLOR_ID_GREEN>; 121 label = "panel4"; 122 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 123 default-state = "off"; 124 }; 125 126 led-4 { 127 function = LED_FUNCTION_STATUS; 128 color = <LED_COLOR_ID_GREEN>; 129 label = "panel5"; 130 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 131 default-state = "off"; 132 }; 133 }; 134 135 pcie0_refclk: pcie0-refclk { 136 compatible = "fixed-clock"; 137 #clock-cells = <0>; 138 clock-frequency = <100000000>; 139 }; 140 141 pps { 142 compatible = "pps-gpio"; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_pps>; 145 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 146 status = "okay"; 147 }; 148 149 reg_3p3v: regulator-3p3v { 150 compatible = "regulator-fixed"; 151 regulator-name = "3P3V"; 152 regulator-min-microvolt = <3300000>; 153 regulator-max-microvolt = <3300000>; 154 regulator-always-on; 155 }; 156 157 reg_usb1_vbus: regulator-usb1 { 158 compatible = "regulator-fixed"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_reg_usb1>; 161 regulator-name = "usb_usb1_vbus"; 162 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; 163 enable-active-high; 164 regulator-min-microvolt = <5000000>; 165 regulator-max-microvolt = <5000000>; 166 }; 167 168 reg_wifi: regulator-wifi { 169 compatible = "regulator-fixed"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_reg_wl>; 172 regulator-name = "wifi"; 173 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 174 enable-active-high; 175 startup-delay-us = <100>; 176 regulator-min-microvolt = <3300000>; 177 regulator-max-microvolt = <3300000>; 178 }; 179}; 180 181&A53_0 { 182 cpu-supply = <&buck2>; 183}; 184 185&A53_1 { 186 cpu-supply = <&buck2>; 187}; 188 189&A53_2 { 190 cpu-supply = <&buck2>; 191}; 192 193&A53_3 { 194 cpu-supply = <&buck2>; 195}; 196 197&ddrc { 198 operating-points-v2 = <&ddrc_opp_table>; 199 200 ddrc_opp_table: opp-table { 201 compatible = "operating-points-v2"; 202 203 opp-25000000 { 204 opp-hz = /bits/ 64 <25000000>; 205 }; 206 207 opp-100000000 { 208 opp-hz = /bits/ 64 <100000000>; 209 }; 210 211 opp-750000000 { 212 opp-hz = /bits/ 64 <750000000>; 213 }; 214 }; 215}; 216 217&ecspi1 { 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_spi1>; 220 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 221 status = "okay"; 222 223 can@0 { 224 compatible = "microchip,mcp2515"; 225 reg = <0>; 226 clocks = <&can20m>; 227 interrupt-parent = <&gpio2>; 228 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 229 spi-max-frequency = <10000000>; 230 }; 231}; 232 233/* off-board header */ 234&ecspi2 { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_spi2>; 237 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 238 status = "okay"; 239}; 240 241&fec1 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_fec1>; 244 phy-mode = "rgmii-id"; 245 phy-handle = <ðphy0>; 246 local-mac-address = [00 00 00 00 00 00]; 247 status = "okay"; 248 249 mdio { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 253 ethphy0: ethernet-phy@0 { 254 compatible = "ethernet-phy-ieee802.3-c22"; 255 reg = <0>; 256 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 257 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 258 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 259 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 260 }; 261 }; 262}; 263 264&gpio1 { 265 gpio-line-names = "", "", "", "", "", "", "", "", 266 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", 267 "", "", "", "", "", "", "", "", 268 "", "", "", "", "", "", "", ""; 269}; 270 271&gpio2 { 272 gpio-line-names = "", "", "", "", "", "", "", "", 273 "uart2_en#", "", "", "", "", "", "", "", 274 "", "", "", "", "", "", "", "", 275 "", "", "", "", "", "", "", ""; 276}; 277 278&gpio3 { 279 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", 280 "", "", "", "", "", "", "", "", 281 "", "", "", "", "", "", "", "", 282 "", "", "", "", "", "", "", ""; 283}; 284 285&gpio4 { 286 gpio-line-names = "", "", "", "", "", "", "", "", 287 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", 288 "lte_pwr#", "lte_rst", "lte_int", "", 289 "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", 290 "", "uart1_term", "uart1_half", "app_gpio2", 291 "mipi_gpio1", "", "", ""; 292}; 293 294&gpio5 { 295 gpio-line-names = "", "", "", "mipi_gpio4", 296 "mipi_gpio3", "mipi_gpio2", "", "", 297 "", "", "", "", "", "", "", "", 298 "", "", "", "", "", "", "", "", 299 "", "", "", "", "", "", "", ""; 300}; 301 302&i2c1 { 303 clock-frequency = <100000>; 304 pinctrl-names = "default", "gpio"; 305 pinctrl-0 = <&pinctrl_i2c1>; 306 pinctrl-1 = <&pinctrl_i2c1_gpio>; 307 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 308 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 309 status = "okay"; 310 311 gsc: gsc@20 { 312 compatible = "gw,gsc"; 313 reg = <0x20>; 314 pinctrl-0 = <&pinctrl_gsc>; 315 interrupt-parent = <&gpio2>; 316 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 317 interrupt-controller; 318 #interrupt-cells = <1>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322 adc { 323 compatible = "gw,gsc-adc"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 channel@6 { 328 gw,mode = <0>; 329 reg = <0x06>; 330 label = "temp"; 331 }; 332 333 channel@8 { 334 gw,mode = <3>; 335 reg = <0x08>; 336 label = "vdd_bat"; 337 }; 338 339 channel@82 { 340 gw,mode = <2>; 341 reg = <0x82>; 342 label = "vin"; 343 gw,voltage-divider-ohms = <22100 1000>; 344 gw,voltage-offset-microvolt = <700000>; 345 }; 346 347 channel@84 { 348 gw,mode = <2>; 349 reg = <0x84>; 350 label = "vin_4p0"; 351 gw,voltage-divider-ohms = <10000 10000>; 352 }; 353 354 channel@86 { 355 gw,mode = <2>; 356 reg = <0x86>; 357 label = "vdd_3p3"; 358 gw,voltage-divider-ohms = <10000 10000>; 359 }; 360 361 channel@88 { 362 gw,mode = <2>; 363 reg = <0x88>; 364 label = "vdd_0p9"; 365 }; 366 367 channel@8c { 368 gw,mode = <2>; 369 reg = <0x8c>; 370 label = "vdd_soc"; 371 }; 372 373 channel@8e { 374 gw,mode = <2>; 375 reg = <0x8e>; 376 label = "vdd_arm"; 377 }; 378 379 channel@90 { 380 gw,mode = <2>; 381 reg = <0x90>; 382 label = "vdd_1p8"; 383 }; 384 385 channel@92 { 386 gw,mode = <2>; 387 reg = <0x92>; 388 label = "vdd_dram"; 389 }; 390 391 channel@98 { 392 gw,mode = <2>; 393 reg = <0x98>; 394 label = "vdd_1p0"; 395 }; 396 397 channel@9a { 398 gw,mode = <2>; 399 reg = <0x9a>; 400 label = "vdd_2p5"; 401 gw,voltage-divider-ohms = <10000 10000>; 402 }; 403 404 channel@9c { 405 gw,mode = <2>; 406 reg = <0x9c>; 407 label = "vdd_5p0"; 408 gw,voltage-divider-ohms = <10000 10000>; 409 }; 410 411 channel@a2 { 412 gw,mode = <2>; 413 reg = <0xa2>; 414 label = "vdd_gsc"; 415 gw,voltage-divider-ohms = <10000 10000>; 416 }; 417 }; 418 }; 419 420 gpio: gpio@23 { 421 compatible = "nxp,pca9555"; 422 reg = <0x23>; 423 gpio-controller; 424 #gpio-cells = <2>; 425 interrupt-parent = <&gsc>; 426 interrupts = <4>; 427 }; 428 429 pmic@4b { 430 compatible = "rohm,bd71847"; 431 reg = <0x4b>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_pmic>; 434 interrupt-parent = <&gpio3>; 435 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 436 rohm,reset-snvs-powered; 437 #clock-cells = <0>; 438 clocks = <&osc_32k>; 439 clock-output-names = "clk-32k-out"; 440 441 regulators { 442 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 443 BUCK1 { 444 regulator-name = "buck1"; 445 regulator-min-microvolt = <700000>; 446 regulator-max-microvolt = <1300000>; 447 regulator-boot-on; 448 regulator-always-on; 449 regulator-ramp-delay = <1250>; 450 }; 451 452 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 453 buck2: BUCK2 { 454 regulator-name = "buck2"; 455 regulator-min-microvolt = <700000>; 456 regulator-max-microvolt = <1300000>; 457 regulator-boot-on; 458 regulator-always-on; 459 regulator-ramp-delay = <1250>; 460 rohm,dvs-run-voltage = <1000000>; 461 rohm,dvs-idle-voltage = <900000>; 462 }; 463 464 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 465 BUCK3 { 466 regulator-name = "buck3"; 467 regulator-min-microvolt = <700000>; 468 regulator-max-microvolt = <1350000>; 469 regulator-boot-on; 470 regulator-always-on; 471 }; 472 473 /* vdd_3p3 */ 474 BUCK4 { 475 regulator-name = "buck4"; 476 regulator-min-microvolt = <3000000>; 477 regulator-max-microvolt = <3300000>; 478 regulator-boot-on; 479 regulator-always-on; 480 }; 481 482 /* vdd_1p8 */ 483 BUCK5 { 484 regulator-name = "buck5"; 485 regulator-min-microvolt = <1605000>; 486 regulator-max-microvolt = <1995000>; 487 regulator-boot-on; 488 regulator-always-on; 489 }; 490 491 /* vdd_dram */ 492 BUCK6 { 493 regulator-name = "buck6"; 494 regulator-min-microvolt = <800000>; 495 regulator-max-microvolt = <1400000>; 496 regulator-boot-on; 497 regulator-always-on; 498 }; 499 500 /* nvcc_snvs_1p8 */ 501 LDO1 { 502 regulator-name = "ldo1"; 503 regulator-min-microvolt = <1600000>; 504 regulator-max-microvolt = <1900000>; 505 regulator-boot-on; 506 regulator-always-on; 507 }; 508 509 /* vdd_snvs_0p8 */ 510 LDO2 { 511 regulator-name = "ldo2"; 512 regulator-min-microvolt = <800000>; 513 regulator-max-microvolt = <900000>; 514 regulator-boot-on; 515 regulator-always-on; 516 }; 517 518 /* vdda_1p8 */ 519 LDO3 { 520 regulator-name = "ldo3"; 521 regulator-min-microvolt = <1800000>; 522 regulator-max-microvolt = <3300000>; 523 regulator-boot-on; 524 regulator-always-on; 525 }; 526 527 LDO4 { 528 regulator-name = "ldo4"; 529 regulator-min-microvolt = <900000>; 530 regulator-max-microvolt = <1800000>; 531 regulator-boot-on; 532 regulator-always-on; 533 }; 534 535 LDO6 { 536 regulator-name = "ldo6"; 537 regulator-min-microvolt = <900000>; 538 regulator-max-microvolt = <1800000>; 539 regulator-boot-on; 540 regulator-always-on; 541 }; 542 }; 543 }; 544 545 eeprom@50 { 546 compatible = "atmel,24c02"; 547 reg = <0x50>; 548 pagesize = <16>; 549 }; 550 551 eeprom@51 { 552 compatible = "atmel,24c02"; 553 reg = <0x51>; 554 pagesize = <16>; 555 }; 556 557 eeprom@52 { 558 compatible = "atmel,24c02"; 559 reg = <0x52>; 560 pagesize = <16>; 561 }; 562 563 eeprom@53 { 564 compatible = "atmel,24c02"; 565 reg = <0x53>; 566 pagesize = <16>; 567 }; 568 569 gsc_rtc: rtc@68 { 570 compatible = "dallas,ds1672"; 571 reg = <0x68>; 572 }; 573}; 574 575&i2c2 { 576 clock-frequency = <400000>; 577 pinctrl-names = "default", "gpio"; 578 pinctrl-0 = <&pinctrl_i2c2>; 579 pinctrl-1 = <&pinctrl_i2c2_gpio>; 580 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 581 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 582 status = "okay"; 583 584 accelerometer@19 { 585 compatible = "st,lis2de12"; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_accel>; 588 reg = <0x19>; 589 st,drdy-int-pin = <1>; 590 interrupt-parent = <&gpio1>; 591 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 592 }; 593}; 594 595/* off-board header */ 596&i2c3 { 597 clock-frequency = <400000>; 598 pinctrl-names = "default", "gpio"; 599 pinctrl-0 = <&pinctrl_i2c3>; 600 pinctrl-1 = <&pinctrl_i2c3_gpio>; 601 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 602 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 603 status = "okay"; 604}; 605 606/* off-board header */ 607&i2c4 { 608 clock-frequency = <400000>; 609 pinctrl-names = "default", "gpio"; 610 pinctrl-0 = <&pinctrl_i2c4>; 611 pinctrl-1 = <&pinctrl_i2c4_gpio>; 612 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 613 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 614 status = "okay"; 615}; 616 617&pcie_phy { 618 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 619 fsl,clkreq-unsupported; 620 clocks = <&pcie0_refclk>; 621 clock-names = "ref"; 622 status = "okay"; 623}; 624 625&pcie0 { 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pinctrl_pcie0>; 628 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; 629 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 630 <&clk IMX8MM_CLK_PCIE1_AUX>; 631 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 632 <&clk IMX8MM_CLK_PCIE1_CTRL>; 633 assigned-clock-rates = <10000000>, <250000000>; 634 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 635 <&clk IMX8MM_SYS_PLL2_250M>; 636 status = "okay"; 637 638 pcie@0,0 { 639 reg = <0x0000 0 0 0 0>; 640 device_type = "pci"; 641 #address-cells = <3>; 642 #size-cells = <2>; 643 ranges; 644 645 eth1: ethernet@0,0 { 646 reg = <0x0000 0 0 0 0>; 647 #address-cells = <3>; 648 #size-cells = <2>; 649 ranges; 650 651 local-mac-address = [00 00 00 00 00 00]; 652 }; 653 }; 654}; 655 656/* off-board header */ 657&sai3 { 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pinctrl_sai3>; 660 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 661 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 662 assigned-clock-rates = <24576000>; 663 status = "okay"; 664}; 665 666/* RS232/RS485/RS422 selectable */ 667&uart1 { 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 670 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 671 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 672 status = "okay"; 673}; 674 675/* RS232 console */ 676&uart2 { 677 pinctrl-names = "default"; 678 pinctrl-0 = <&pinctrl_uart2>; 679 status = "okay"; 680}; 681 682/* bluetooth HCI */ 683&uart3 { 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 686 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 687 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 688 status = "okay"; 689 690 bluetooth { 691 compatible = "brcm,bcm4330-bt"; 692 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 693 }; 694}; 695 696/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ 697&uart4 { 698 pinctrl-names = "default"; 699 pinctrl-0 = <&pinctrl_uart4>; 700 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 701 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; 702 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; 703 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; 704 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; 705 status = "okay"; 706}; 707 708&usbotg1 { 709 dr_mode = "host"; 710 vbus-supply = <®_usb1_vbus>; 711 disable-over-current; 712 status = "okay"; 713}; 714 715&usbotg2 { 716 dr_mode = "host"; 717 disable-over-current; 718 status = "okay"; 719}; 720 721/* SDIO WiFi */ 722&usdhc2 { 723 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 724 pinctrl-0 = <&pinctrl_usdhc2>; 725 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 726 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 727 bus-width = <4>; 728 non-removable; 729 vmmc-supply = <®_wifi>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "okay"; 733 734 wifi@0 { 735 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 736 reg = <0>; 737 }; 738}; 739 740/* eMMC */ 741&usdhc3 { 742 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 743 pinctrl-0 = <&pinctrl_usdhc3>; 744 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 745 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 746 bus-width = <8>; 747 non-removable; 748 status = "okay"; 749}; 750 751&wdog1 { 752 pinctrl-names = "default"; 753 pinctrl-0 = <&pinctrl_wdog>; 754 fsl,ext-reset-output; 755 status = "okay"; 756}; 757 758&iomuxc { 759 pinctrl-names = "default"; 760 pinctrl-0 = <&pinctrl_hog>; 761 762 pinctrl_hog: hoggrp { 763 fsl,pins = < 764 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 765 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ 766 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ 767 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 768 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 769 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ 770 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ 771 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ 772 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ 773 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ 774 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ 775 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ 776 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ 777 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ 778 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ 779 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ 780 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ 781 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ 782 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ 783 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ 784 >; 785 }; 786 787 pinctrl_accel: accelgrp { 788 fsl,pins = < 789 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 790 >; 791 }; 792 793 pinctrl_fec1: fec1grp { 794 fsl,pins = < 795 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 796 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 797 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 798 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 799 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 800 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 801 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 802 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 803 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 804 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 805 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 806 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 807 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 808 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 809 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ 810 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ 811 >; 812 }; 813 814 pinctrl_gsc: gscgrp { 815 fsl,pins = < 816 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 817 >; 818 }; 819 820 pinctrl_i2c1: i2c1grp { 821 fsl,pins = < 822 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 823 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 824 >; 825 }; 826 827 pinctrl_i2c1_gpio: i2c1gpiogrp { 828 fsl,pins = < 829 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 830 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 831 >; 832 }; 833 834 pinctrl_i2c2: i2c2grp { 835 fsl,pins = < 836 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 837 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 838 >; 839 }; 840 841 pinctrl_i2c2_gpio: i2c2gpiogrp { 842 fsl,pins = < 843 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 844 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 845 >; 846 }; 847 848 pinctrl_i2c3: i2c3grp { 849 fsl,pins = < 850 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 851 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 852 >; 853 }; 854 855 pinctrl_i2c3_gpio: i2c3gpiogrp { 856 fsl,pins = < 857 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 858 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 859 >; 860 }; 861 862 pinctrl_i2c4: i2c4grp { 863 fsl,pins = < 864 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 865 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 866 >; 867 }; 868 869 pinctrl_i2c4_gpio: i2c4gpiogrp { 870 fsl,pins = < 871 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 872 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 873 >; 874 }; 875 876 pinctrl_gpio_leds: gpioledgrp { 877 fsl,pins = < 878 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 879 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 880 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 881 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 882 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 883 >; 884 }; 885 886 pinctrl_pcie0: pciegrp { 887 fsl,pins = < 888 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 889 >; 890 }; 891 892 pinctrl_pmic: pmicgrp { 893 fsl,pins = < 894 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 895 >; 896 }; 897 898 pinctrl_pps: ppsgrp { 899 fsl,pins = < 900 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ 901 >; 902 }; 903 904 pinctrl_reg_wl: regwlgrp { 905 fsl,pins = < 906 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ 907 >; 908 }; 909 910 pinctrl_reg_usb1: regusb1grp { 911 fsl,pins = < 912 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 913 >; 914 }; 915 916 pinctrl_sai3: sai3grp { 917 fsl,pins = < 918 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 919 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 920 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 921 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 922 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 923 >; 924 }; 925 926 pinctrl_spi1: spi1grp { 927 fsl,pins = < 928 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 929 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 930 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 931 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 932 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ 933 >; 934 }; 935 936 pinctrl_spi2: spi2grp { 937 fsl,pins = < 938 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 939 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 940 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 941 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ 942 >; 943 }; 944 945 pinctrl_uart1: uart1grp { 946 fsl,pins = < 947 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 948 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 949 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ 950 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ 951 >; 952 }; 953 954 pinctrl_uart1_gpio: uart1gpiogrp { 955 fsl,pins = < 956 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ 957 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ 958 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ 959 >; 960 }; 961 962 pinctrl_uart2: uart2grp { 963 fsl,pins = < 964 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 965 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 966 >; 967 }; 968 969 pinctrl_uart3_gpio: uart3_gpiogrp { 970 fsl,pins = < 971 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ 972 >; 973 }; 974 975 pinctrl_uart3: uart3grp { 976 fsl,pins = < 977 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 978 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 979 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ 980 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ 981 >; 982 }; 983 984 pinctrl_uart4: uart4grp { 985 fsl,pins = < 986 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 987 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 988 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ 989 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ 990 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ 991 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ 992 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ 993 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ 994 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ 995 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ 996 >; 997 }; 998 999 pinctrl_usdhc2: usdhc2grp { 1000 fsl,pins = < 1001 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 1002 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 1003 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 1004 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 1005 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 1006 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 1007 >; 1008 }; 1009 1010 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1011 fsl,pins = < 1012 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 1013 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 1014 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 1015 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 1016 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 1017 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 1018 >; 1019 }; 1020 1021 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1022 fsl,pins = < 1023 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 1024 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 1025 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 1026 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 1027 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 1028 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 1029 >; 1030 }; 1031 1032 pinctrl_usdhc3: usdhc3grp { 1033 fsl,pins = < 1034 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 1035 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 1036 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 1037 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 1038 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 1039 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 1040 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 1041 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 1042 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 1043 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 1044 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 1045 >; 1046 }; 1047 1048 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1049 fsl,pins = < 1050 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 1051 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 1052 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 1053 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 1054 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 1055 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 1056 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 1057 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 1058 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 1059 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 1060 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 1061 >; 1062 }; 1063 1064 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1065 fsl,pins = < 1066 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 1067 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1068 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 1069 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 1070 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 1071 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1072 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1073 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1074 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1075 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1076 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1077 >; 1078 }; 1079 1080 pinctrl_wdog: wdoggrp { 1081 fsl,pins = < 1082 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1083 >; 1084 }; 1085}; 1086