1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7901 i.MX8MM board"; 17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; 18 19 aliases { 20 ethernet0 = &fec1; 21 ethernet1 = &lan1; 22 ethernet2 = &lan2; 23 ethernet3 = &lan3; 24 ethernet4 = &lan4; 25 usb0 = &usbotg1; 26 usb1 = &usbotg2; 27 }; 28 29 chosen { 30 stdout-path = &uart2; 31 }; 32 33 memory@40000000 { 34 device_type = "memory"; 35 reg = <0x0 0x40000000 0 0x80000000>; 36 }; 37 38 gpio-keys { 39 compatible = "gpio-keys"; 40 41 key-user-pb { 42 label = "user_pb"; 43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 44 linux,code = <BTN_0>; 45 }; 46 47 key-user-pb1x { 48 label = "user_pb1x"; 49 linux,code = <BTN_1>; 50 interrupt-parent = <&gsc>; 51 interrupts = <0>; 52 }; 53 54 key-erased { 55 label = "key_erased"; 56 linux,code = <BTN_2>; 57 interrupt-parent = <&gsc>; 58 interrupts = <1>; 59 }; 60 61 key-eeprom-wp { 62 label = "eeprom_wp"; 63 linux,code = <BTN_3>; 64 interrupt-parent = <&gsc>; 65 interrupts = <2>; 66 }; 67 68 key-tamper { 69 label = "tamper"; 70 linux,code = <BTN_4>; 71 interrupt-parent = <&gsc>; 72 interrupts = <5>; 73 }; 74 75 switch-hold { 76 label = "switch_hold"; 77 linux,code = <BTN_5>; 78 interrupt-parent = <&gsc>; 79 interrupts = <7>; 80 }; 81 }; 82 83 led-controller { 84 compatible = "gpio-leds"; 85 86 led-0 { 87 function = LED_FUNCTION_STATUS; 88 color = <LED_COLOR_ID_RED>; 89 label = "led01_red"; 90 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; 91 default-state = "off"; 92 }; 93 94 led-1 { 95 function = LED_FUNCTION_STATUS; 96 color = <LED_COLOR_ID_GREEN>; 97 label = "led01_grn"; 98 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 102 led-2 { 103 function = LED_FUNCTION_STATUS; 104 color = <LED_COLOR_ID_RED>; 105 label = "led02_red"; 106 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; 107 default-state = "off"; 108 }; 109 110 led-3 { 111 function = LED_FUNCTION_STATUS; 112 color = <LED_COLOR_ID_GREEN>; 113 label = "led02_grn"; 114 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; 115 default-state = "off"; 116 }; 117 118 led-4 { 119 function = LED_FUNCTION_STATUS; 120 color = <LED_COLOR_ID_RED>; 121 label = "led03_red"; 122 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; 123 default-state = "off"; 124 }; 125 126 led-5 { 127 function = LED_FUNCTION_STATUS; 128 color = <LED_COLOR_ID_GREEN>; 129 label = "led03_grn"; 130 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; 131 default-state = "off"; 132 }; 133 134 led-6 { 135 function = LED_FUNCTION_STATUS; 136 color = <LED_COLOR_ID_RED>; 137 label = "led04_red"; 138 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; 139 default-state = "off"; 140 }; 141 142 led-7 { 143 function = LED_FUNCTION_STATUS; 144 color = <LED_COLOR_ID_GREEN>; 145 label = "led04_grn"; 146 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; 147 default-state = "off"; 148 }; 149 150 led-8 { 151 function = LED_FUNCTION_STATUS; 152 color = <LED_COLOR_ID_RED>; 153 label = "led05_red"; 154 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; 155 default-state = "off"; 156 }; 157 158 led-9 { 159 function = LED_FUNCTION_STATUS; 160 color = <LED_COLOR_ID_GREEN>; 161 label = "led05_grn"; 162 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 166 led-a { 167 function = LED_FUNCTION_STATUS; 168 color = <LED_COLOR_ID_RED>; 169 label = "led06_red"; 170 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; 171 default-state = "off"; 172 }; 173 174 led-b { 175 function = LED_FUNCTION_STATUS; 176 color = <LED_COLOR_ID_GREEN>; 177 label = "led06_grn"; 178 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; 179 default-state = "off"; 180 }; 181 }; 182 183 pcie0_refclk: pcie0-refclk { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <100000000>; 187 }; 188 189 reg_3p3v: regulator-3p3v { 190 compatible = "regulator-fixed"; 191 regulator-name = "3P3V"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 }; 195 196 regulator-ioexp { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_reg_ioexp>; 199 compatible = "regulator-fixed"; 200 regulator-name = "ioexp"; 201 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 202 enable-active-high; 203 startup-delay-us = <100>; 204 regulator-min-microvolt = <3300000>; 205 regulator-max-microvolt = <3300000>; 206 regulator-always-on; 207 }; 208 209 regulator-isouart { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_reg_isouart>; 212 compatible = "regulator-fixed"; 213 regulator-name = "iso_uart"; 214 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; 215 startup-delay-us = <100>; 216 regulator-min-microvolt = <3300000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-always-on; 219 }; 220 221 reg_usb2_vbus: regulator-usb2 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_reg_usb2>; 224 compatible = "regulator-fixed"; 225 regulator-name = "usb_usb2_vbus"; 226 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 227 enable-active-high; 228 regulator-min-microvolt = <5000000>; 229 regulator-max-microvolt = <5000000>; 230 }; 231 232 reg_wifi: regulator-wifi { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_reg_wl>; 235 compatible = "regulator-fixed"; 236 regulator-name = "wifi"; 237 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 238 enable-active-high; 239 startup-delay-us = <100>; 240 regulator-min-microvolt = <3300000>; 241 regulator-max-microvolt = <3300000>; 242 }; 243}; 244 245&A53_0 { 246 cpu-supply = <&buck2>; 247}; 248 249&A53_1 { 250 cpu-supply = <&buck2>; 251}; 252 253&A53_2 { 254 cpu-supply = <&buck2>; 255}; 256 257&A53_3 { 258 cpu-supply = <&buck2>; 259}; 260 261&ddrc { 262 operating-points-v2 = <&ddrc_opp_table>; 263 264 ddrc_opp_table: opp-table { 265 compatible = "operating-points-v2"; 266 267 opp-25000000 { 268 opp-hz = /bits/ 64 <25000000>; 269 }; 270 271 opp-100000000 { 272 opp-hz = /bits/ 64 <100000000>; 273 }; 274 275 opp-750000000 { 276 opp-hz = /bits/ 64 <750000000>; 277 }; 278 }; 279}; 280 281&disp_blk_ctrl { 282 status = "disabled"; 283}; 284 285&ecspi1 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_spi1>; 288 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 289 <&gpio4 24 GPIO_ACTIVE_LOW>; 290 status = "okay"; 291 292 flash@0 { 293 compatible = "jedec,spi-nor"; 294 reg = <0>; 295 spi-max-frequency = <40000000>; 296 status = "okay"; 297 }; 298 299 tpm@1 { 300 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 301 reg = <0x1>; 302 spi-max-frequency = <36000000>; 303 }; 304}; 305 306&fec1 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_fec1>; 309 phy-mode = "rgmii-id"; 310 local-mac-address = [00 00 00 00 00 00]; 311 status = "okay"; 312 313 fixed-link { 314 speed = <1000>; 315 full-duplex; 316 }; 317}; 318 319&gpio1 { 320 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", 321 "", "uart1_rs232#", "dig1_in", "dig1_out", 322 "", "", "", "", "", "", "", "", 323 "", "", "", "", "", "", "", "", 324 "", "", "", "", "", "", "", ""; 325}; 326 327&gpio4 { 328 gpio-line-names = "", "", "", "", 329 "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", 330 "uart3_rs485#", "", "", "", "", "", "", "", 331 "", "", "", "", "", "", "", "", 332 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; 333}; 334 335&gpio5 { 336 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", 337 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", 338 "", "", "", "", "", "", "", "", 339 "", "", "", "", "", "", "", ""; 340}; 341 342&gpu_2d { 343 status = "disabled"; 344}; 345 346&gpu_3d { 347 status = "disabled"; 348}; 349 350&i2c1 { 351 clock-frequency = <100000>; 352 pinctrl-names = "default", "gpio"; 353 pinctrl-0 = <&pinctrl_i2c1>; 354 pinctrl-1 = <&pinctrl_i2c1_gpio>; 355 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 356 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 357 status = "okay"; 358 359 gsc: gsc@20 { 360 compatible = "gw,gsc"; 361 reg = <0x20>; 362 pinctrl-0 = <&pinctrl_gsc>; 363 interrupt-parent = <&gpio4>; 364 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 365 interrupt-controller; 366 #interrupt-cells = <1>; 367 368 adc { 369 compatible = "gw,gsc-adc"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 373 channel@6 { 374 gw,mode = <0>; 375 reg = <0x06>; 376 label = "temp"; 377 }; 378 379 channel@8 { 380 gw,mode = <3>; 381 reg = <0x08>; 382 label = "vdd_bat"; 383 }; 384 385 channel@82 { 386 gw,mode = <2>; 387 reg = <0x82>; 388 label = "vin_aux1"; 389 gw,voltage-divider-ohms = <22100 1000>; 390 }; 391 392 channel@84 { 393 gw,mode = <2>; 394 reg = <0x84>; 395 label = "vin_aux2"; 396 gw,voltage-divider-ohms = <22100 1000>; 397 }; 398 399 channel@86 { 400 gw,mode = <2>; 401 reg = <0x86>; 402 label = "vdd_vin"; 403 gw,voltage-divider-ohms = <22100 1000>; 404 }; 405 406 channel@88 { 407 gw,mode = <2>; 408 reg = <0x88>; 409 label = "vdd_3p3"; 410 gw,voltage-divider-ohms = <10000 10000>; 411 }; 412 413 channel@8c { 414 gw,mode = <2>; 415 reg = <0x8c>; 416 label = "vdd_2p5"; 417 gw,voltage-divider-ohms = <10000 10000>; 418 }; 419 420 channel@8e { 421 gw,mode = <2>; 422 reg = <0x8e>; 423 label = "vdd_0p95"; 424 }; 425 426 channel@90 { 427 gw,mode = <2>; 428 reg = <0x90>; 429 label = "vdd_soc"; 430 }; 431 432 channel@92 { 433 gw,mode = <2>; 434 reg = <0x92>; 435 label = "vdd_arm"; 436 }; 437 438 channel@98 { 439 gw,mode = <2>; 440 reg = <0x98>; 441 label = "vdd_1p8"; 442 }; 443 444 channel@9a { 445 gw,mode = <2>; 446 reg = <0x9a>; 447 label = "vdd_1p2"; 448 }; 449 450 channel@9c { 451 gw,mode = <2>; 452 reg = <0x9c>; 453 label = "vdd_dram"; 454 }; 455 456 channel@a2 { 457 gw,mode = <2>; 458 reg = <0xa2>; 459 label = "vdd_gsc"; 460 gw,voltage-divider-ohms = <10000 10000>; 461 }; 462 }; 463 }; 464 465 gpio: gpio@23 { 466 compatible = "nxp,pca9555"; 467 reg = <0x23>; 468 gpio-controller; 469 #gpio-cells = <2>; 470 interrupt-parent = <&gsc>; 471 interrupts = <4>; 472 }; 473 474 eeprom@50 { 475 compatible = "atmel,24c02"; 476 reg = <0x50>; 477 pagesize = <16>; 478 }; 479 480 eeprom@51 { 481 compatible = "atmel,24c02"; 482 reg = <0x51>; 483 pagesize = <16>; 484 }; 485 486 eeprom@52 { 487 compatible = "atmel,24c02"; 488 reg = <0x52>; 489 pagesize = <16>; 490 }; 491 492 eeprom@53 { 493 compatible = "atmel,24c02"; 494 reg = <0x53>; 495 pagesize = <16>; 496 }; 497 498 rtc@68 { 499 compatible = "dallas,ds1672"; 500 reg = <0x68>; 501 }; 502}; 503 504&i2c2 { 505 clock-frequency = <400000>; 506 pinctrl-names = "default", "gpio"; 507 pinctrl-0 = <&pinctrl_i2c2>; 508 pinctrl-1 = <&pinctrl_i2c2_gpio>; 509 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 510 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 511 status = "okay"; 512 513 pmic@4b { 514 compatible = "rohm,bd71847"; 515 reg = <0x4b>; 516 pinctrl-names = "default"; 517 pinctrl-0 = <&pinctrl_pmic>; 518 interrupt-parent = <&gpio3>; 519 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 520 rohm,reset-snvs-powered; 521 #clock-cells = <0>; 522 clocks = <&osc_32k>; 523 clock-output-names = "clk-32k-out"; 524 525 regulators { 526 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 527 BUCK1 { 528 regulator-name = "buck1"; 529 regulator-min-microvolt = <700000>; 530 regulator-max-microvolt = <1300000>; 531 regulator-boot-on; 532 regulator-always-on; 533 regulator-ramp-delay = <1250>; 534 }; 535 536 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 537 buck2: BUCK2 { 538 regulator-name = "buck2"; 539 regulator-min-microvolt = <700000>; 540 regulator-max-microvolt = <1300000>; 541 regulator-boot-on; 542 regulator-always-on; 543 regulator-ramp-delay = <1250>; 544 rohm,dvs-run-voltage = <1000000>; 545 rohm,dvs-idle-voltage = <900000>; 546 }; 547 548 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 549 BUCK3 { 550 regulator-name = "buck3"; 551 regulator-min-microvolt = <700000>; 552 regulator-max-microvolt = <1350000>; 553 regulator-boot-on; 554 regulator-always-on; 555 }; 556 557 /* vdd_3p3 */ 558 BUCK4 { 559 regulator-name = "buck4"; 560 regulator-min-microvolt = <3000000>; 561 regulator-max-microvolt = <3300000>; 562 regulator-boot-on; 563 regulator-always-on; 564 }; 565 566 /* vdd_1p8 */ 567 BUCK5 { 568 regulator-name = "buck5"; 569 regulator-min-microvolt = <1605000>; 570 regulator-max-microvolt = <1995000>; 571 regulator-boot-on; 572 regulator-always-on; 573 }; 574 575 /* vdd_dram */ 576 BUCK6 { 577 regulator-name = "buck6"; 578 regulator-min-microvolt = <800000>; 579 regulator-max-microvolt = <1400000>; 580 regulator-boot-on; 581 regulator-always-on; 582 }; 583 584 /* nvcc_snvs_1p8 */ 585 LDO1 { 586 regulator-name = "ldo1"; 587 regulator-min-microvolt = <1600000>; 588 regulator-max-microvolt = <1900000>; 589 regulator-boot-on; 590 regulator-always-on; 591 }; 592 593 /* vdd_snvs_0p8 */ 594 LDO2 { 595 regulator-name = "ldo2"; 596 regulator-min-microvolt = <800000>; 597 regulator-max-microvolt = <900000>; 598 regulator-boot-on; 599 regulator-always-on; 600 }; 601 602 /* vdda_1p8 */ 603 LDO3 { 604 regulator-name = "ldo3"; 605 regulator-min-microvolt = <1800000>; 606 regulator-max-microvolt = <3300000>; 607 regulator-boot-on; 608 regulator-always-on; 609 }; 610 611 LDO4 { 612 regulator-name = "ldo4"; 613 regulator-min-microvolt = <900000>; 614 regulator-max-microvolt = <1800000>; 615 regulator-boot-on; 616 regulator-always-on; 617 }; 618 619 LDO6 { 620 regulator-name = "ldo6"; 621 regulator-min-microvolt = <900000>; 622 regulator-max-microvolt = <1800000>; 623 regulator-boot-on; 624 regulator-always-on; 625 }; 626 }; 627 }; 628}; 629 630&i2c3 { 631 clock-frequency = <400000>; 632 pinctrl-names = "default", "gpio"; 633 pinctrl-0 = <&pinctrl_i2c3>; 634 pinctrl-1 = <&pinctrl_i2c3_gpio>; 635 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 636 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 637 status = "okay"; 638 639 leds_gpio: gpio@20 { 640 compatible = "nxp,pca9555"; 641 reg = <0x20>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 }; 645 646 switch: switch@5f { 647 compatible = "microchip,ksz9897"; 648 reg = <0x5f>; 649 pinctrl-0 = <&pinctrl_ksz>; 650 interrupt-parent = <&gpio4>; 651 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 652 653 ports { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 657 lan1: port@0 { 658 reg = <0>; 659 label = "lan1"; 660 phy-mode = "internal"; 661 local-mac-address = [00 00 00 00 00 00]; 662 }; 663 664 lan2: port@1 { 665 reg = <1>; 666 label = "lan2"; 667 phy-mode = "internal"; 668 local-mac-address = [00 00 00 00 00 00]; 669 }; 670 671 lan3: port@2 { 672 reg = <2>; 673 label = "lan3"; 674 phy-mode = "internal"; 675 local-mac-address = [00 00 00 00 00 00]; 676 }; 677 678 lan4: port@3 { 679 reg = <3>; 680 label = "lan4"; 681 phy-mode = "internal"; 682 local-mac-address = [00 00 00 00 00 00]; 683 }; 684 685 port@5 { 686 reg = <5>; 687 ethernet = <&fec1>; 688 phy-mode = "rgmii-id"; 689 690 fixed-link { 691 speed = <1000>; 692 full-duplex; 693 }; 694 }; 695 }; 696 }; 697 698 crypto@60 { 699 compatible = "atmel,atecc508a"; 700 reg = <0x60>; 701 }; 702}; 703 704&i2c4 { 705 clock-frequency = <400000>; 706 pinctrl-names = "default", "gpio"; 707 pinctrl-0 = <&pinctrl_i2c4>; 708 pinctrl-1 = <&pinctrl_i2c4_gpio>; 709 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 710 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 711 status = "okay"; 712}; 713 714&pcie_phy { 715 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 716 fsl,clkreq-unsupported; 717 clocks = <&pcie0_refclk>; 718 clock-names = "ref"; 719 status = "okay"; 720}; 721 722&pcie0 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_pcie0>; 725 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 726 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 727 <&clk IMX8MM_CLK_PCIE1_AUX>; 728 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 729 <&clk IMX8MM_CLK_PCIE1_CTRL>; 730 assigned-clock-rates = <10000000>, <250000000>; 731 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 732 <&clk IMX8MM_SYS_PLL2_250M>; 733 status = "okay"; 734}; 735 736&pgc_gpu { 737 status = "disabled"; 738}; 739 740&pgc_gpumix { 741 status = "disabled"; 742}; 743 744&pgc_mipi { 745 status = "disabled"; 746}; 747 748&uart1 { 749 pinctrl-names = "default"; 750 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 751 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 752 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 753 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 754 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 755 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 756 status = "okay"; 757}; 758 759/* console */ 760&uart2 { 761 pinctrl-names = "default"; 762 pinctrl-0 = <&pinctrl_uart2>; 763 status = "okay"; 764}; 765 766&uart3 { 767 pinctrl-names = "default"; 768 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 769 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 770 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 771 status = "okay"; 772}; 773 774&uart4 { 775 pinctrl-names = "default"; 776 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; 777 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 778 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 779 status = "okay"; 780}; 781 782&usbotg1 { 783 dr_mode = "host"; 784 disable-over-current; 785 status = "okay"; 786}; 787 788&usbotg2 { 789 dr_mode = "host"; 790 vbus-supply = <®_usb2_vbus>; 791 over-current-active-low; 792 status = "okay"; 793}; 794 795/* SDIO WiFi */ 796&usdhc1 { 797 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 798 pinctrl-0 = <&pinctrl_usdhc1>; 799 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 800 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 801 bus-width = <4>; 802 non-removable; 803 vmmc-supply = <®_wifi>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "okay"; 807 808 wifi@0 { 809 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 810 reg = <0>; 811 }; 812}; 813 814/* microSD */ 815&usdhc2 { 816 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 817 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 818 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 819 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 820 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 821 bus-width = <4>; 822 vmmc-supply = <®_3p3v>; 823 status = "okay"; 824}; 825 826/* eMMC */ 827&usdhc3 { 828 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 829 pinctrl-0 = <&pinctrl_usdhc3>; 830 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 831 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 832 bus-width = <8>; 833 non-removable; 834 status = "okay"; 835}; 836 837&wdog1 { 838 pinctrl-names = "default"; 839 pinctrl-0 = <&pinctrl_wdog>; 840 fsl,ext-reset-output; 841 status = "okay"; 842}; 843 844&iomuxc { 845 pinctrl-names = "default"; 846 pinctrl-0 = <&pinctrl_hog>; 847 848 pinctrl_hog: hoggrp { 849 fsl,pins = < 850 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ 851 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ 852 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ 853 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ 854 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ 855 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ 856 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ 857 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ 858 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ 859 >; 860 }; 861 862 pinctrl_fec1: fec1grp { 863 fsl,pins = < 864 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 865 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 866 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 867 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 868 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 869 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 870 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 871 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 872 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 873 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 874 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 875 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 876 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 877 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 878 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ 879 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ 880 >; 881 }; 882 883 pinctrl_gsc: gscgrp { 884 fsl,pins = < 885 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 886 >; 887 }; 888 889 pinctrl_i2c1: i2c1grp { 890 fsl,pins = < 891 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 892 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 893 >; 894 }; 895 896 pinctrl_i2c1_gpio: i2c1gpiogrp { 897 fsl,pins = < 898 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 899 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 900 >; 901 }; 902 903 pinctrl_i2c2: i2c2grp { 904 fsl,pins = < 905 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 906 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 907 >; 908 }; 909 910 pinctrl_i2c2_gpio: i2c2gpiogrp { 911 fsl,pins = < 912 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 913 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 914 >; 915 }; 916 917 pinctrl_i2c3: i2c3grp { 918 fsl,pins = < 919 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 920 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 921 >; 922 }; 923 924 pinctrl_i2c3_gpio: i2c3gpiogrp { 925 fsl,pins = < 926 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 927 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 928 >; 929 }; 930 931 pinctrl_i2c4: i2c4grp { 932 fsl,pins = < 933 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 934 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 935 >; 936 }; 937 938 pinctrl_i2c4_gpio: i2c4gpiogrp { 939 fsl,pins = < 940 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 941 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 942 >; 943 }; 944 945 pinctrl_ksz: kszgrp { 946 fsl,pins = < 947 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 948 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ 949 >; 950 }; 951 952 pinctrl_pcie0: pciegrp { 953 fsl,pins = < 954 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ 955 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 956 >; 957 }; 958 959 pinctrl_pmic: pmicgrp { 960 fsl,pins = < 961 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 962 >; 963 }; 964 965 pinctrl_reg_isouart: regisouartgrp { 966 fsl,pins = < 967 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 968 >; 969 }; 970 971 pinctrl_reg_ioexp: regioexpgrp { 972 fsl,pins = < 973 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 974 >; 975 }; 976 977 pinctrl_reg_wl: regwlgrp { 978 fsl,pins = < 979 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 980 >; 981 }; 982 983 pinctrl_reg_usb2: regusb1grp { 984 fsl,pins = < 985 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 986 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 987 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 988 >; 989 }; 990 991 pinctrl_spi1: spi1grp { 992 fsl,pins = < 993 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 994 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 995 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 996 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 997 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 998 >; 999 }; 1000 1001 pinctrl_uart1: uart1grp { 1002 fsl,pins = < 1003 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 1004 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 1005 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 1006 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 1007 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 1008 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 1009 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 1010 >; 1011 }; 1012 1013 pinctrl_uart1_gpio: uart1gpiogrp { 1014 fsl,pins = < 1015 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ 1016 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ 1017 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ 1018 >; 1019 }; 1020 1021 pinctrl_uart2: uart2grp { 1022 fsl,pins = < 1023 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 1024 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 1025 >; 1026 }; 1027 1028 pinctrl_uart3: uart3grp { 1029 fsl,pins = < 1030 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 1031 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 1032 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 1033 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 1034 >; 1035 }; 1036 1037 pinctrl_uart3_gpio: uart3gpiogrp { 1038 fsl,pins = < 1039 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ 1040 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ 1041 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ 1042 >; 1043 }; 1044 1045 pinctrl_uart4: uart4grp { 1046 fsl,pins = < 1047 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 1048 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 1049 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 1050 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 1051 >; 1052 }; 1053 1054 pinctrl_uart4_gpio: uart4gpiogrp { 1055 fsl,pins = < 1056 1057 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ 1058 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ 1059 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ 1060 >; 1061 }; 1062 1063 pinctrl_usdhc1: usdhc1grp { 1064 fsl,pins = < 1065 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 1066 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 1067 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 1068 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 1069 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 1070 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 1071 >; 1072 }; 1073 1074 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1075 fsl,pins = < 1076 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 1077 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 1078 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 1079 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 1080 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 1081 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 1082 >; 1083 }; 1084 1085 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1086 fsl,pins = < 1087 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 1088 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 1089 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 1090 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 1091 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 1092 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 1093 >; 1094 }; 1095 1096 pinctrl_usdhc2: usdhc2grp { 1097 fsl,pins = < 1098 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 1099 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 1100 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 1101 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 1102 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 1103 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 1104 >; 1105 }; 1106 1107 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1108 fsl,pins = < 1109 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 1110 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 1111 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 1112 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 1113 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 1114 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 1115 >; 1116 }; 1117 1118 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1119 fsl,pins = < 1120 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 1121 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 1122 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 1123 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 1124 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 1125 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 1126 >; 1127 }; 1128 1129 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1130 fsl,pins = < 1131 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 1132 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 1133 >; 1134 }; 1135 1136 pinctrl_usdhc3: usdhc3grp { 1137 fsl,pins = < 1138 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 1139 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 1140 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 1141 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 1142 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 1143 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 1144 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 1145 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 1146 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 1147 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 1148 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 1149 >; 1150 }; 1151 1152 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1153 fsl,pins = < 1154 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 1155 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 1156 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 1157 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 1158 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 1159 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 1160 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 1161 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 1162 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 1163 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 1164 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 1165 >; 1166 }; 1167 1168 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1169 fsl,pins = < 1170 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 1171 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1172 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 1173 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 1174 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 1175 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1176 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1177 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1178 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1179 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1180 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1181 >; 1182 }; 1183 1184 pinctrl_wdog: wdoggrp { 1185 fsl,pins = < 1186 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1187 >; 1188 }; 1189}; 1190