1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7901 i.MX8MM board"; 17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; 18 19 aliases { 20 ethernet0 = &fec1; 21 ethernet1 = &lan1; 22 ethernet2 = &lan2; 23 ethernet3 = &lan3; 24 ethernet4 = &lan4; 25 rtc0 = &gsc_rtc; 26 rtc1 = &snvs_rtc; 27 usb0 = &usbotg1; 28 usb1 = &usbotg2; 29 }; 30 31 chosen { 32 stdout-path = &uart2; 33 }; 34 35 memory@40000000 { 36 device_type = "memory"; 37 reg = <0x0 0x40000000 0 0x80000000>; 38 }; 39 40 gpio-keys { 41 compatible = "gpio-keys"; 42 43 key-user-pb { 44 label = "user_pb"; 45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 46 linux,code = <BTN_0>; 47 }; 48 49 key-user-pb1x { 50 label = "user_pb1x"; 51 linux,code = <BTN_1>; 52 interrupt-parent = <&gsc>; 53 interrupts = <0>; 54 }; 55 56 key-erased { 57 label = "key_erased"; 58 linux,code = <BTN_2>; 59 interrupt-parent = <&gsc>; 60 interrupts = <1>; 61 }; 62 63 key-eeprom-wp { 64 label = "eeprom_wp"; 65 linux,code = <BTN_3>; 66 interrupt-parent = <&gsc>; 67 interrupts = <2>; 68 }; 69 70 key-tamper { 71 label = "tamper"; 72 linux,code = <BTN_4>; 73 interrupt-parent = <&gsc>; 74 interrupts = <5>; 75 }; 76 77 switch-hold { 78 label = "switch_hold"; 79 linux,code = <BTN_5>; 80 interrupt-parent = <&gsc>; 81 interrupts = <7>; 82 }; 83 }; 84 85 led-controller { 86 compatible = "gpio-leds"; 87 88 led-0 { 89 function = LED_FUNCTION_STATUS; 90 color = <LED_COLOR_ID_RED>; 91 label = "led01_red"; 92 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; 93 default-state = "off"; 94 }; 95 96 led-1 { 97 function = LED_FUNCTION_STATUS; 98 color = <LED_COLOR_ID_GREEN>; 99 label = "led01_grn"; 100 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; 101 default-state = "off"; 102 }; 103 104 led-2 { 105 function = LED_FUNCTION_STATUS; 106 color = <LED_COLOR_ID_RED>; 107 label = "led02_red"; 108 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; 109 default-state = "off"; 110 }; 111 112 led-3 { 113 function = LED_FUNCTION_STATUS; 114 color = <LED_COLOR_ID_GREEN>; 115 label = "led02_grn"; 116 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; 117 default-state = "off"; 118 }; 119 120 led-4 { 121 function = LED_FUNCTION_STATUS; 122 color = <LED_COLOR_ID_RED>; 123 label = "led03_red"; 124 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; 125 default-state = "off"; 126 }; 127 128 led-5 { 129 function = LED_FUNCTION_STATUS; 130 color = <LED_COLOR_ID_GREEN>; 131 label = "led03_grn"; 132 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; 133 default-state = "off"; 134 }; 135 136 led-6 { 137 function = LED_FUNCTION_STATUS; 138 color = <LED_COLOR_ID_RED>; 139 label = "led04_red"; 140 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; 141 default-state = "off"; 142 }; 143 144 led-7 { 145 function = LED_FUNCTION_STATUS; 146 color = <LED_COLOR_ID_GREEN>; 147 label = "led04_grn"; 148 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; 149 default-state = "off"; 150 }; 151 152 led-8 { 153 function = LED_FUNCTION_STATUS; 154 color = <LED_COLOR_ID_RED>; 155 label = "led05_red"; 156 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; 157 default-state = "off"; 158 }; 159 160 led-9 { 161 function = LED_FUNCTION_STATUS; 162 color = <LED_COLOR_ID_GREEN>; 163 label = "led05_grn"; 164 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; 165 default-state = "off"; 166 }; 167 168 led-a { 169 function = LED_FUNCTION_STATUS; 170 color = <LED_COLOR_ID_RED>; 171 label = "led06_red"; 172 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; 173 default-state = "off"; 174 }; 175 176 led-b { 177 function = LED_FUNCTION_STATUS; 178 color = <LED_COLOR_ID_GREEN>; 179 label = "led06_grn"; 180 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; 181 default-state = "off"; 182 }; 183 }; 184 185 pcie0_refclk: pcie0-refclk { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <100000000>; 189 }; 190 191 reg_3p3v: regulator-3p3v { 192 compatible = "regulator-fixed"; 193 regulator-name = "3P3V"; 194 regulator-min-microvolt = <3300000>; 195 regulator-max-microvolt = <3300000>; 196 }; 197 198 regulator-ioexp { 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_reg_ioexp>; 201 compatible = "regulator-fixed"; 202 regulator-name = "ioexp"; 203 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 204 enable-active-high; 205 startup-delay-us = <100>; 206 regulator-min-microvolt = <3300000>; 207 regulator-max-microvolt = <3300000>; 208 regulator-always-on; 209 }; 210 211 regulator-isouart { 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_reg_isouart>; 214 compatible = "regulator-fixed"; 215 regulator-name = "iso_uart"; 216 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; 217 startup-delay-us = <100>; 218 regulator-min-microvolt = <3300000>; 219 regulator-max-microvolt = <3300000>; 220 regulator-always-on; 221 }; 222 223 reg_usb2_vbus: regulator-usb2 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_reg_usb2>; 226 compatible = "regulator-fixed"; 227 regulator-name = "usb_usb2_vbus"; 228 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 229 enable-active-high; 230 regulator-min-microvolt = <5000000>; 231 regulator-max-microvolt = <5000000>; 232 }; 233 234 reg_wifi: regulator-wifi { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_reg_wl>; 237 compatible = "regulator-fixed"; 238 regulator-name = "wifi"; 239 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 240 enable-active-high; 241 startup-delay-us = <100>; 242 regulator-min-microvolt = <3300000>; 243 regulator-max-microvolt = <3300000>; 244 }; 245}; 246 247&A53_0 { 248 cpu-supply = <&buck2>; 249}; 250 251&A53_1 { 252 cpu-supply = <&buck2>; 253}; 254 255&A53_2 { 256 cpu-supply = <&buck2>; 257}; 258 259&A53_3 { 260 cpu-supply = <&buck2>; 261}; 262 263&ddrc { 264 operating-points-v2 = <&ddrc_opp_table>; 265 266 ddrc_opp_table: opp-table { 267 compatible = "operating-points-v2"; 268 269 opp-25000000 { 270 opp-hz = /bits/ 64 <25000000>; 271 }; 272 273 opp-100000000 { 274 opp-hz = /bits/ 64 <100000000>; 275 }; 276 277 opp-750000000 { 278 opp-hz = /bits/ 64 <750000000>; 279 }; 280 }; 281}; 282 283&disp_blk_ctrl { 284 status = "disabled"; 285}; 286 287&ecspi1 { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_spi1>; 290 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 291 <&gpio4 24 GPIO_ACTIVE_LOW>; 292 status = "okay"; 293 294 flash@0 { 295 compatible = "jedec,spi-nor"; 296 reg = <0>; 297 spi-max-frequency = <40000000>; 298 status = "okay"; 299 }; 300 301 tpm@1 { 302 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 303 reg = <0x1>; 304 spi-max-frequency = <36000000>; 305 }; 306}; 307 308&fec1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_fec1>; 311 phy-mode = "rgmii-id"; 312 local-mac-address = [00 00 00 00 00 00]; 313 status = "okay"; 314 315 fixed-link { 316 speed = <1000>; 317 full-duplex; 318 }; 319}; 320 321&gpio1 { 322 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", 323 "", "uart1_rs232#", "dig1_in", "dig1_out", 324 "", "", "", "", "", "", "", "", 325 "", "", "", "", "", "", "", "", 326 "", "", "", "", "", "", "", ""; 327}; 328 329&gpio4 { 330 gpio-line-names = "", "", "", "", 331 "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", 332 "uart3_rs485#", "", "", "", "", "", "", "", 333 "", "", "", "", "", "", "", "", 334 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; 335}; 336 337&gpio5 { 338 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", 339 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", 340 "", "", "", "", "", "", "", "", 341 "", "", "", "", "", "", "", ""; 342}; 343 344&gpu_2d { 345 status = "disabled"; 346}; 347 348&gpu_3d { 349 status = "disabled"; 350}; 351 352&i2c1 { 353 clock-frequency = <100000>; 354 pinctrl-names = "default", "gpio"; 355 pinctrl-0 = <&pinctrl_i2c1>; 356 pinctrl-1 = <&pinctrl_i2c1_gpio>; 357 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 358 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 359 status = "okay"; 360 361 gsc: gsc@20 { 362 compatible = "gw,gsc"; 363 reg = <0x20>; 364 pinctrl-0 = <&pinctrl_gsc>; 365 interrupt-parent = <&gpio4>; 366 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 367 interrupt-controller; 368 #interrupt-cells = <1>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 372 adc { 373 compatible = "gw,gsc-adc"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 377 channel@6 { 378 gw,mode = <0>; 379 reg = <0x06>; 380 label = "temp"; 381 }; 382 383 channel@8 { 384 gw,mode = <3>; 385 reg = <0x08>; 386 label = "vdd_bat"; 387 }; 388 389 channel@82 { 390 gw,mode = <2>; 391 reg = <0x82>; 392 label = "vin_aux1"; 393 gw,voltage-divider-ohms = <22100 1000>; 394 }; 395 396 channel@84 { 397 gw,mode = <2>; 398 reg = <0x84>; 399 label = "vin_aux2"; 400 gw,voltage-divider-ohms = <22100 1000>; 401 }; 402 403 channel@86 { 404 gw,mode = <2>; 405 reg = <0x86>; 406 label = "vdd_vin"; 407 gw,voltage-divider-ohms = <22100 1000>; 408 }; 409 410 channel@88 { 411 gw,mode = <2>; 412 reg = <0x88>; 413 label = "vdd_3p3"; 414 gw,voltage-divider-ohms = <10000 10000>; 415 }; 416 417 channel@8c { 418 gw,mode = <2>; 419 reg = <0x8c>; 420 label = "vdd_2p5"; 421 gw,voltage-divider-ohms = <10000 10000>; 422 }; 423 424 channel@8e { 425 gw,mode = <2>; 426 reg = <0x8e>; 427 label = "vdd_0p95"; 428 }; 429 430 channel@90 { 431 gw,mode = <2>; 432 reg = <0x90>; 433 label = "vdd_soc"; 434 }; 435 436 channel@92 { 437 gw,mode = <2>; 438 reg = <0x92>; 439 label = "vdd_arm"; 440 }; 441 442 channel@98 { 443 gw,mode = <2>; 444 reg = <0x98>; 445 label = "vdd_1p8"; 446 }; 447 448 channel@9a { 449 gw,mode = <2>; 450 reg = <0x9a>; 451 label = "vdd_1p2"; 452 }; 453 454 channel@9c { 455 gw,mode = <2>; 456 reg = <0x9c>; 457 label = "vdd_dram"; 458 }; 459 460 channel@a2 { 461 gw,mode = <2>; 462 reg = <0xa2>; 463 label = "vdd_gsc"; 464 gw,voltage-divider-ohms = <10000 10000>; 465 }; 466 }; 467 }; 468 469 gpio: gpio@23 { 470 compatible = "nxp,pca9555"; 471 reg = <0x23>; 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-parent = <&gsc>; 475 interrupts = <4>; 476 }; 477 478 eeprom@50 { 479 compatible = "atmel,24c02"; 480 reg = <0x50>; 481 pagesize = <16>; 482 }; 483 484 eeprom@51 { 485 compatible = "atmel,24c02"; 486 reg = <0x51>; 487 pagesize = <16>; 488 }; 489 490 eeprom@52 { 491 compatible = "atmel,24c02"; 492 reg = <0x52>; 493 pagesize = <16>; 494 }; 495 496 eeprom@53 { 497 compatible = "atmel,24c02"; 498 reg = <0x53>; 499 pagesize = <16>; 500 }; 501 502 gsc_rtc: rtc@68 { 503 compatible = "dallas,ds1672"; 504 reg = <0x68>; 505 }; 506}; 507 508&i2c2 { 509 clock-frequency = <400000>; 510 pinctrl-names = "default", "gpio"; 511 pinctrl-0 = <&pinctrl_i2c2>; 512 pinctrl-1 = <&pinctrl_i2c2_gpio>; 513 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 514 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 515 status = "okay"; 516 517 pmic@4b { 518 compatible = "rohm,bd71847"; 519 reg = <0x4b>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pinctrl_pmic>; 522 interrupt-parent = <&gpio3>; 523 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 524 rohm,reset-snvs-powered; 525 #clock-cells = <0>; 526 clocks = <&osc_32k>; 527 clock-output-names = "clk-32k-out"; 528 529 regulators { 530 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 531 BUCK1 { 532 regulator-name = "buck1"; 533 regulator-min-microvolt = <700000>; 534 regulator-max-microvolt = <1300000>; 535 regulator-boot-on; 536 regulator-always-on; 537 regulator-ramp-delay = <1250>; 538 }; 539 540 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 541 buck2: BUCK2 { 542 regulator-name = "buck2"; 543 regulator-min-microvolt = <700000>; 544 regulator-max-microvolt = <1300000>; 545 regulator-boot-on; 546 regulator-always-on; 547 regulator-ramp-delay = <1250>; 548 rohm,dvs-run-voltage = <1000000>; 549 rohm,dvs-idle-voltage = <900000>; 550 }; 551 552 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 553 BUCK3 { 554 regulator-name = "buck3"; 555 regulator-min-microvolt = <700000>; 556 regulator-max-microvolt = <1350000>; 557 regulator-boot-on; 558 regulator-always-on; 559 }; 560 561 /* vdd_3p3 */ 562 BUCK4 { 563 regulator-name = "buck4"; 564 regulator-min-microvolt = <3000000>; 565 regulator-max-microvolt = <3300000>; 566 regulator-boot-on; 567 regulator-always-on; 568 }; 569 570 /* vdd_1p8 */ 571 BUCK5 { 572 regulator-name = "buck5"; 573 regulator-min-microvolt = <1605000>; 574 regulator-max-microvolt = <1995000>; 575 regulator-boot-on; 576 regulator-always-on; 577 }; 578 579 /* vdd_dram */ 580 BUCK6 { 581 regulator-name = "buck6"; 582 regulator-min-microvolt = <800000>; 583 regulator-max-microvolt = <1400000>; 584 regulator-boot-on; 585 regulator-always-on; 586 }; 587 588 /* nvcc_snvs_1p8 */ 589 LDO1 { 590 regulator-name = "ldo1"; 591 regulator-min-microvolt = <1600000>; 592 regulator-max-microvolt = <1900000>; 593 regulator-boot-on; 594 regulator-always-on; 595 }; 596 597 /* vdd_snvs_0p8 */ 598 LDO2 { 599 regulator-name = "ldo2"; 600 regulator-min-microvolt = <800000>; 601 regulator-max-microvolt = <900000>; 602 regulator-boot-on; 603 regulator-always-on; 604 }; 605 606 /* vdda_1p8 */ 607 LDO3 { 608 regulator-name = "ldo3"; 609 regulator-min-microvolt = <1800000>; 610 regulator-max-microvolt = <3300000>; 611 regulator-boot-on; 612 regulator-always-on; 613 }; 614 615 LDO4 { 616 regulator-name = "ldo4"; 617 regulator-min-microvolt = <900000>; 618 regulator-max-microvolt = <1800000>; 619 regulator-boot-on; 620 regulator-always-on; 621 }; 622 623 LDO6 { 624 regulator-name = "ldo6"; 625 regulator-min-microvolt = <900000>; 626 regulator-max-microvolt = <1800000>; 627 regulator-boot-on; 628 regulator-always-on; 629 }; 630 }; 631 }; 632}; 633 634&i2c3 { 635 clock-frequency = <400000>; 636 pinctrl-names = "default", "gpio"; 637 pinctrl-0 = <&pinctrl_i2c3>; 638 pinctrl-1 = <&pinctrl_i2c3_gpio>; 639 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 640 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 641 status = "okay"; 642 643 leds_gpio: gpio@20 { 644 compatible = "nxp,pca9555"; 645 reg = <0x20>; 646 gpio-controller; 647 #gpio-cells = <2>; 648 }; 649 650 switch: switch@5f { 651 compatible = "microchip,ksz9897"; 652 reg = <0x5f>; 653 pinctrl-0 = <&pinctrl_ksz>; 654 interrupt-parent = <&gpio4>; 655 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 656 657 ports { 658 #address-cells = <1>; 659 #size-cells = <0>; 660 661 lan1: port@0 { 662 reg = <0>; 663 label = "lan1"; 664 phy-mode = "internal"; 665 local-mac-address = [00 00 00 00 00 00]; 666 }; 667 668 lan2: port@1 { 669 reg = <1>; 670 label = "lan2"; 671 phy-mode = "internal"; 672 local-mac-address = [00 00 00 00 00 00]; 673 }; 674 675 lan3: port@2 { 676 reg = <2>; 677 label = "lan3"; 678 phy-mode = "internal"; 679 local-mac-address = [00 00 00 00 00 00]; 680 }; 681 682 lan4: port@3 { 683 reg = <3>; 684 label = "lan4"; 685 phy-mode = "internal"; 686 local-mac-address = [00 00 00 00 00 00]; 687 }; 688 689 port@5 { 690 reg = <5>; 691 ethernet = <&fec1>; 692 phy-mode = "rgmii-id"; 693 694 fixed-link { 695 speed = <1000>; 696 full-duplex; 697 }; 698 }; 699 }; 700 }; 701 702 crypto@60 { 703 compatible = "atmel,atecc508a"; 704 reg = <0x60>; 705 }; 706}; 707 708&i2c4 { 709 clock-frequency = <400000>; 710 pinctrl-names = "default", "gpio"; 711 pinctrl-0 = <&pinctrl_i2c4>; 712 pinctrl-1 = <&pinctrl_i2c4_gpio>; 713 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 714 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 715 status = "okay"; 716}; 717 718&pcie_phy { 719 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 720 fsl,clkreq-unsupported; 721 clocks = <&pcie0_refclk>; 722 clock-names = "ref"; 723 status = "okay"; 724}; 725 726&pcie0 { 727 pinctrl-names = "default"; 728 pinctrl-0 = <&pinctrl_pcie0>; 729 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 730 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 731 <&clk IMX8MM_CLK_PCIE1_AUX>; 732 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 733 <&clk IMX8MM_CLK_PCIE1_CTRL>; 734 assigned-clock-rates = <10000000>, <250000000>; 735 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 736 <&clk IMX8MM_SYS_PLL2_250M>; 737 status = "okay"; 738}; 739 740&pgc_gpu { 741 status = "disabled"; 742}; 743 744&pgc_gpumix { 745 status = "disabled"; 746}; 747 748&pgc_mipi { 749 status = "disabled"; 750}; 751 752&uart1 { 753 pinctrl-names = "default"; 754 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 755 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 756 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 757 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 758 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 759 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 760 status = "okay"; 761}; 762 763/* console */ 764&uart2 { 765 pinctrl-names = "default"; 766 pinctrl-0 = <&pinctrl_uart2>; 767 status = "okay"; 768}; 769 770&uart3 { 771 pinctrl-names = "default"; 772 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 773 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 774 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 775 status = "okay"; 776}; 777 778&uart4 { 779 pinctrl-names = "default"; 780 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; 781 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 782 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 783 status = "okay"; 784}; 785 786&usbotg1 { 787 dr_mode = "host"; 788 disable-over-current; 789 status = "okay"; 790}; 791 792&usbotg2 { 793 dr_mode = "host"; 794 vbus-supply = <®_usb2_vbus>; 795 over-current-active-low; 796 status = "okay"; 797}; 798 799/* SDIO WiFi */ 800&usdhc1 { 801 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 802 pinctrl-0 = <&pinctrl_usdhc1>; 803 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 804 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 805 bus-width = <4>; 806 non-removable; 807 vmmc-supply = <®_wifi>; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "okay"; 811 812 wifi@0 { 813 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 814 reg = <0>; 815 }; 816}; 817 818/* microSD */ 819&usdhc2 { 820 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 821 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 822 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 823 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 824 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 825 bus-width = <4>; 826 vmmc-supply = <®_3p3v>; 827 status = "okay"; 828}; 829 830/* eMMC */ 831&usdhc3 { 832 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 833 pinctrl-0 = <&pinctrl_usdhc3>; 834 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 835 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 836 bus-width = <8>; 837 non-removable; 838 status = "okay"; 839}; 840 841&wdog1 { 842 pinctrl-names = "default"; 843 pinctrl-0 = <&pinctrl_wdog>; 844 fsl,ext-reset-output; 845 status = "okay"; 846}; 847 848&iomuxc { 849 pinctrl-names = "default"; 850 pinctrl-0 = <&pinctrl_hog>; 851 852 pinctrl_hog: hoggrp { 853 fsl,pins = < 854 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ 855 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ 856 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ 857 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ 858 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ 859 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ 860 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ 861 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ 862 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ 863 >; 864 }; 865 866 pinctrl_fec1: fec1grp { 867 fsl,pins = < 868 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 869 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 870 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 871 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 872 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 873 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 874 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 875 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 876 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 877 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 878 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 879 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 880 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 881 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 882 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ 883 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ 884 >; 885 }; 886 887 pinctrl_gsc: gscgrp { 888 fsl,pins = < 889 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 890 >; 891 }; 892 893 pinctrl_i2c1: i2c1grp { 894 fsl,pins = < 895 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 896 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 897 >; 898 }; 899 900 pinctrl_i2c1_gpio: i2c1gpiogrp { 901 fsl,pins = < 902 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 903 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 904 >; 905 }; 906 907 pinctrl_i2c2: i2c2grp { 908 fsl,pins = < 909 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 910 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 911 >; 912 }; 913 914 pinctrl_i2c2_gpio: i2c2gpiogrp { 915 fsl,pins = < 916 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 917 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 918 >; 919 }; 920 921 pinctrl_i2c3: i2c3grp { 922 fsl,pins = < 923 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 924 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 925 >; 926 }; 927 928 pinctrl_i2c3_gpio: i2c3gpiogrp { 929 fsl,pins = < 930 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 931 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 932 >; 933 }; 934 935 pinctrl_i2c4: i2c4grp { 936 fsl,pins = < 937 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 938 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 939 >; 940 }; 941 942 pinctrl_i2c4_gpio: i2c4gpiogrp { 943 fsl,pins = < 944 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 945 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 946 >; 947 }; 948 949 pinctrl_ksz: kszgrp { 950 fsl,pins = < 951 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 952 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ 953 >; 954 }; 955 956 pinctrl_pcie0: pciegrp { 957 fsl,pins = < 958 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ 959 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 960 >; 961 }; 962 963 pinctrl_pmic: pmicgrp { 964 fsl,pins = < 965 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 966 >; 967 }; 968 969 pinctrl_reg_isouart: regisouartgrp { 970 fsl,pins = < 971 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 972 >; 973 }; 974 975 pinctrl_reg_ioexp: regioexpgrp { 976 fsl,pins = < 977 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 978 >; 979 }; 980 981 pinctrl_reg_wl: regwlgrp { 982 fsl,pins = < 983 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 984 >; 985 }; 986 987 pinctrl_reg_usb2: regusb1grp { 988 fsl,pins = < 989 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 990 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 991 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 992 >; 993 }; 994 995 pinctrl_spi1: spi1grp { 996 fsl,pins = < 997 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 998 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 999 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 1000 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 1001 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 1002 >; 1003 }; 1004 1005 pinctrl_uart1: uart1grp { 1006 fsl,pins = < 1007 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 1008 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 1009 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 1010 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 1011 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 1012 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 1013 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 1014 >; 1015 }; 1016 1017 pinctrl_uart1_gpio: uart1gpiogrp { 1018 fsl,pins = < 1019 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ 1020 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ 1021 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ 1022 >; 1023 }; 1024 1025 pinctrl_uart2: uart2grp { 1026 fsl,pins = < 1027 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 1028 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 1029 >; 1030 }; 1031 1032 pinctrl_uart3: uart3grp { 1033 fsl,pins = < 1034 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 1035 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 1036 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 1037 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 1038 >; 1039 }; 1040 1041 pinctrl_uart3_gpio: uart3gpiogrp { 1042 fsl,pins = < 1043 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ 1044 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ 1045 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ 1046 >; 1047 }; 1048 1049 pinctrl_uart4: uart4grp { 1050 fsl,pins = < 1051 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 1052 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 1053 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 1054 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 1055 >; 1056 }; 1057 1058 pinctrl_uart4_gpio: uart4gpiogrp { 1059 fsl,pins = < 1060 1061 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ 1062 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ 1063 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ 1064 >; 1065 }; 1066 1067 pinctrl_usdhc1: usdhc1grp { 1068 fsl,pins = < 1069 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 1070 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 1071 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 1072 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 1073 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 1074 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 1075 >; 1076 }; 1077 1078 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1079 fsl,pins = < 1080 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 1081 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 1082 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 1083 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 1084 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 1085 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 1086 >; 1087 }; 1088 1089 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1090 fsl,pins = < 1091 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 1092 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 1093 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 1094 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 1095 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 1096 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 1097 >; 1098 }; 1099 1100 pinctrl_usdhc2: usdhc2grp { 1101 fsl,pins = < 1102 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 1103 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 1104 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 1105 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 1106 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 1107 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 1108 >; 1109 }; 1110 1111 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1112 fsl,pins = < 1113 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 1114 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 1115 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 1116 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 1117 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 1118 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 1119 >; 1120 }; 1121 1122 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1123 fsl,pins = < 1124 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 1125 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 1126 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 1127 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 1128 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 1129 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 1130 >; 1131 }; 1132 1133 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1134 fsl,pins = < 1135 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 1136 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 1137 >; 1138 }; 1139 1140 pinctrl_usdhc3: usdhc3grp { 1141 fsl,pins = < 1142 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 1143 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 1144 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 1145 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 1146 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 1147 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 1148 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 1149 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 1150 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 1151 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 1152 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 1153 >; 1154 }; 1155 1156 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1157 fsl,pins = < 1158 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 1159 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 1160 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 1161 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 1162 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 1163 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 1164 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 1165 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 1166 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 1167 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 1168 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 1169 >; 1170 }; 1171 1172 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1173 fsl,pins = < 1174 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 1175 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1176 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 1177 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 1178 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 1179 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1180 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1181 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1182 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1183 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1184 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1185 >; 1186 }; 1187 1188 pinctrl_wdog: wdoggrp { 1189 fsl,pins = < 1190 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1191 >; 1192 }; 1193}; 1194