1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 15 16 led-0 { 17 function = LED_FUNCTION_STATUS; 18 color = <LED_COLOR_ID_GREEN>; 19 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 20 default-state = "on"; 21 linux,default-trigger = "heartbeat"; 22 }; 23 24 led-1 { 25 function = LED_FUNCTION_STATUS; 26 color = <LED_COLOR_ID_RED>; 27 gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; 28 default-state = "off"; 29 }; 30 }; 31 32 pcie0_refclk: clock-pcie0 { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <100000000>; 36 }; 37 38 pps { 39 compatible = "pps-gpio"; 40 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_pps>; 42 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 43 status = "okay"; 44 }; 45 46 reg_usb2_vbus: regulator-usb2-vbus { 47 compatible = "regulator-fixed"; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_reg_usb2_en>; 50 regulator-name = "usb2_vbus"; 51 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 regulator-min-microvolt = <5000000>; 54 regulator-max-microvolt = <5000000>; 55 }; 56 57 reg_usdhc2_vmmc: regulator-usdhc2 { 58 compatible = "regulator-fixed"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 61 regulator-name = "SD2_3P3V"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 65 enable-active-high; 66 }; 67}; 68 69/* off-board header */ 70&ecspi2 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_spi2>; 73 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 74 status = "okay"; 75}; 76 77&gpio1 { 78 gpio-line-names = 79 "", "", "", "", 80 "", "", "", "", 81 "", "", "", "", 82 "", "gpioa", "gpiob", "", 83 "", "", "", "", 84 "", "", "", "", 85 "", "", "", "", 86 "", "", "", ""; 87}; 88 89&gpio4 { 90 gpio-line-names = 91 "", "", "", "pci_usb_sel", 92 "", "", "", "pci_wdis#", 93 "", "", "", "", 94 "", "", "", "", 95 "", "", "", "", 96 "", "", "", "", 97 "", "", "", "", 98 "", "", "", ""; 99}; 100 101&gpio5 { 102 gpio-line-names = 103 "", "", "", "", 104 "gpioc", "gpiod", "", "", 105 "", "", "", "", 106 "", "", "", "", 107 "", "", "", "", 108 "", "", "", "", 109 "", "", "", "", 110 "", "", "", ""; 111}; 112 113&i2c2 { 114 clock-frequency = <400000>; 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_i2c2>; 117 status = "okay"; 118 119 accelerometer@19 { 120 compatible = "st,lis2de12"; 121 reg = <0x19>; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_accel>; 124 interrupt-parent = <&gpio5>; 125 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 126 st,drdy-int-pin = <1>; 127 }; 128 129 eeprom@52 { 130 compatible = "atmel,24c32"; 131 reg = <0x52>; 132 pagesize = <32>; 133 }; 134}; 135 136/* off-board header */ 137&i2c3 { 138 clock-frequency = <400000>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_i2c3>; 141 status = "okay"; 142}; 143 144&pcie_phy { 145 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 146 fsl,clkreq-unsupported; 147 clocks = <&pcie0_refclk>; 148 clock-names = "ref"; 149 status = "okay"; 150}; 151 152&pcie0 { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_pcie0>; 155 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; 156 status = "okay"; 157}; 158 159/* GPS */ 160&uart1 { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_uart1>; 163 status = "okay"; 164}; 165 166/* USB1 - Type C front panel SINK port J14 */ 167&usbotg1 { 168 dr_mode = "peripheral"; 169 status = "okay"; 170}; 171 172/* USB2 4-port USB3.0 HUB: 173 * P1 - USBC connector (host only) 174 * P2 - USB2 test connector 175 * P3 - miniPCIe full card 176 * P4 - miniPCIe half card 177 */ 178&usbotg2 { 179 dr_mode = "host"; 180 vbus-supply = <®_usb2_vbus>; 181 status = "okay"; 182}; 183 184/* microSD */ 185&usdhc2 { 186 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 187 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 188 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 189 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 190 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 191 vmmc-supply = <®_usdhc2_vmmc>; 192 bus-width = <4>; 193 status = "okay"; 194}; 195 196&iomuxc { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_hog>; 199 200 pinctrl_hog: hoggrp { 201 fsl,pins = < 202 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ 203 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ 204 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ 205 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ 206 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ 207 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ 208 >; 209 }; 210 211 pinctrl_accel: accelgrp { 212 fsl,pins = < 213 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x159 214 >; 215 }; 216 217 pinctrl_gpio_leds: gpioledgrp { 218 fsl,pins = < 219 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ 220 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ 221 >; 222 }; 223 224 pinctrl_i2c2: i2c2grp { 225 fsl,pins = < 226 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 227 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 228 >; 229 }; 230 231 pinctrl_i2c3: i2c3grp { 232 fsl,pins = < 233 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 234 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 235 >; 236 }; 237 238 pinctrl_pcie0: pciegrp { 239 fsl,pins = < 240 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 241 >; 242 }; 243 244 pinctrl_pps: ppsgrp { 245 fsl,pins = < 246 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 247 >; 248 }; 249 250 pinctrl_reg_usb2_en: regusb2grp { 251 fsl,pins = < 252 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ 253 >; 254 }; 255 256 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 257 fsl,pins = < 258 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 259 >; 260 }; 261 262 pinctrl_spi2: spi2grp { 263 fsl,pins = < 264 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 265 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 266 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 267 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 268 >; 269 }; 270 271 pinctrl_uart1: uart1grp { 272 fsl,pins = < 273 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 274 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 275 >; 276 }; 277 278 pinctrl_usdhc2: usdhc2grp { 279 fsl,pins = < 280 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 281 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 282 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 283 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 284 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 285 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 286 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 287 >; 288 }; 289 290 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 291 fsl,pins = < 292 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 293 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 294 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 295 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 296 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 297 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 298 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 299 >; 300 }; 301 302 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 303 fsl,pins = < 304 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 305 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 306 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 307 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 308 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 309 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 310 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 311 >; 312 }; 313 314 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 315 fsl,pins = < 316 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 317 >; 318 }; 319}; 320