1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 aliases { 12 ethernet1 = ð1; 13 usb0 = &usbotg1; 14 usb1 = &usbotg2; 15 }; 16 17 led-controller { 18 compatible = "gpio-leds"; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&pinctrl_gpio_leds>; 21 22 led-0 { 23 function = LED_FUNCTION_STATUS; 24 color = <LED_COLOR_ID_GREEN>; 25 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 26 default-state = "on"; 27 linux,default-trigger = "heartbeat"; 28 }; 29 30 led-1 { 31 function = LED_FUNCTION_STATUS; 32 color = <LED_COLOR_ID_RED>; 33 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 34 default-state = "off"; 35 }; 36 }; 37 38 pcie0_refclk: pcie0-refclk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <100000000>; 42 }; 43 44 pps { 45 compatible = "pps-gpio"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_pps>; 48 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 49 status = "okay"; 50 }; 51 52 reg_1p8v: regulator-1p8v { 53 compatible = "regulator-fixed"; 54 regulator-name = "1P8V"; 55 regulator-min-microvolt = <1800000>; 56 regulator-max-microvolt = <1800000>; 57 regulator-always-on; 58 }; 59 60 reg_3p3v: regulator-3p3v { 61 compatible = "regulator-fixed"; 62 regulator-name = "3P3V"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 regulator-always-on; 66 }; 67 68 reg_usb_otg1_vbus: regulator-usb-otg1 { 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_reg_usb1_en>; 71 compatible = "regulator-fixed"; 72 regulator-name = "usb_otg1_vbus"; 73 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 74 enable-active-high; 75 regulator-min-microvolt = <5000000>; 76 regulator-max-microvolt = <5000000>; 77 }; 78 79 reg_usb_otg2_vbus: regulator-usb-otg2 { 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_reg_usb2_en>; 82 compatible = "regulator-fixed"; 83 regulator-name = "usb_otg2_vbus"; 84 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 regulator-min-microvolt = <5000000>; 87 regulator-max-microvolt = <5000000>; 88 }; 89 90 reg_wifi_en: regulator-wifi-en { 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_reg_wl>; 93 compatible = "regulator-fixed"; 94 regulator-name = "wl"; 95 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 96 startup-delay-us = <100>; 97 enable-active-high; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 }; 101}; 102 103/* off-board header */ 104&ecspi2 { 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_spi2>; 107 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 108 <&gpio1 10 GPIO_ACTIVE_LOW>; 109 status = "okay"; 110 111 tpm@1 { 112 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 113 reg = <0x1>; 114 spi-max-frequency = <36000000>; 115 }; 116}; 117 118&gpio1 { 119 gpio-line-names = "rs485_term", "mipi_gpio4", "", "", 120 "", "", "pci_usb_sel", "dio0", 121 "", "dio1", "", "", "", "", "", "", 122 "", "", "", "", "", "", "", "", 123 "", "", "", "", "", "", "", ""; 124}; 125 126&gpio4 { 127 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", 128 "mipi_gpio1", "", "", "pci_wdis#", 129 "", "", "", "", "", "", "", "", 130 "", "", "", "", "", "", "", "", 131 "", "", "", "", "", "", "", ""; 132}; 133 134&i2c2 { 135 clock-frequency = <400000>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_i2c2>; 138 status = "okay"; 139 140 accelerometer@19 { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_accel>; 143 compatible = "st,lis2de12"; 144 reg = <0x19>; 145 st,drdy-int-pin = <1>; 146 interrupt-parent = <&gpio4>; 147 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 148 }; 149}; 150 151/* off-board header */ 152&i2c3 { 153 clock-frequency = <400000>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_i2c3>; 156 status = "okay"; 157}; 158 159&pcie_phy { 160 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 161 fsl,clkreq-unsupported; 162 clocks = <&pcie0_refclk>; 163 clock-names = "ref"; 164 status = "okay"; 165}; 166 167&pcie0 { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_pcie0>; 170 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; 171 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 172 <&clk IMX8MM_CLK_PCIE1_AUX>; 173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 174 <&clk IMX8MM_CLK_PCIE1_CTRL>; 175 assigned-clock-rates = <10000000>, <250000000>; 176 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 177 <&clk IMX8MM_SYS_PLL2_250M>; 178 status = "okay"; 179 180 pcie@0,0 { 181 reg = <0x0000 0 0 0 0>; 182 device_type = "pci"; 183 #address-cells = <3>; 184 #size-cells = <2>; 185 ranges; 186 187 pcie@0,0 { 188 reg = <0x0000 0 0 0 0>; 189 device_type = "pci"; 190 #address-cells = <3>; 191 #size-cells = <2>; 192 ranges; 193 194 pcie@4,0 { 195 reg = <0x2000 0 0 0 0>; 196 device_type = "pci"; 197 #address-cells = <3>; 198 #size-cells = <2>; 199 ranges; 200 201 eth1: ethernet@0,0 { 202 reg = <0x0000 0 0 0 0>; 203 #address-cells = <3>; 204 #size-cells = <2>; 205 ranges; 206 207 local-mac-address = [00 00 00 00 00 00]; 208 }; 209 }; 210 }; 211 }; 212}; 213 214/* off-board header */ 215&sai3 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_sai3>; 218 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 219 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 220 assigned-clock-rates = <24576000>; 221 status = "okay"; 222}; 223 224/* GPS */ 225&uart1 { 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_uart1>; 228 status = "okay"; 229}; 230 231/* bluetooth HCI */ 232&uart3 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; 235 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 236 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 237 status = "okay"; 238 239 bluetooth { 240 compatible = "brcm,bcm4330-bt"; 241 shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 242 }; 243}; 244 245/* RS232 */ 246&uart4 { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_uart4>; 249 status = "okay"; 250}; 251 252&usbotg1 { 253 dr_mode = "otg"; 254 over-current-active-low; 255 vbus-supply = <®_usb_otg1_vbus>; 256 status = "okay"; 257}; 258 259&usbotg2 { 260 dr_mode = "host"; 261 disable-over-current; 262 vbus-supply = <®_usb_otg2_vbus>; 263 status = "okay"; 264}; 265 266/* SDIO WiFi */ 267&usdhc1 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_usdhc1>; 270 bus-width = <4>; 271 non-removable; 272 vmmc-supply = <®_wifi_en>; 273 status = "okay"; 274}; 275 276/* microSD */ 277&usdhc2 { 278 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 279 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 280 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 281 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 282 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 283 bus-width = <4>; 284 vmmc-supply = <®_3p3v>; 285 status = "okay"; 286}; 287 288&iomuxc { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_hog>; 291 292 pinctrl_hog: hoggrp { 293 fsl,pins = < 294 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ 295 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ 296 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ 297 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ 298 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ 299 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ 300 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ 301 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ 302 >; 303 }; 304 305 pinctrl_accel: accelgrp { 306 fsl,pins = < 307 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 308 >; 309 }; 310 311 pinctrl_bten: btengrp { 312 fsl,pins = < 313 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 314 >; 315 }; 316 317 pinctrl_gpio_leds: gpioledgrp { 318 fsl,pins = < 319 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 320 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 321 >; 322 }; 323 324 pinctrl_i2c3: i2c3grp { 325 fsl,pins = < 326 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 327 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 328 >; 329 }; 330 331 pinctrl_pcie0: pcie0grp { 332 fsl,pins = < 333 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 334 >; 335 }; 336 337 pinctrl_pps: ppsgrp { 338 fsl,pins = < 339 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 340 >; 341 }; 342 343 pinctrl_reg_wl: regwlgrp { 344 fsl,pins = < 345 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 346 >; 347 }; 348 349 pinctrl_reg_usb1_en: regusb1grp { 350 fsl,pins = < 351 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 352 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 353 >; 354 }; 355 356 pinctrl_reg_usb2_en: regusb2grp { 357 fsl,pins = < 358 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 359 >; 360 }; 361 362 pinctrl_sai3: sai3grp { 363 fsl,pins = < 364 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 365 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 366 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 367 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 368 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 369 >; 370 }; 371 372 pinctrl_spi2: spi2grp { 373 fsl,pins = < 374 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 375 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 376 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 377 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 378 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 379 >; 380 }; 381 382 pinctrl_uart1: uart1grp { 383 fsl,pins = < 384 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 385 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 386 >; 387 }; 388 389 pinctrl_uart3: uart3grp { 390 fsl,pins = < 391 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 392 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 393 MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140 394 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 395 >; 396 }; 397 398 pinctrl_uart4: uart4grp { 399 fsl,pins = < 400 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 401 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 402 >; 403 }; 404 405 pinctrl_usdhc1: usdhc1grp { 406 fsl,pins = < 407 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 408 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 409 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 410 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 411 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 412 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 413 >; 414 }; 415 416 pinctrl_usdhc2: usdhc2grp { 417 fsl,pins = < 418 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 419 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 420 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 421 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 422 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 423 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 424 >; 425 }; 426 427 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 428 fsl,pins = < 429 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 430 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 431 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 432 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 433 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 434 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 435 >; 436 }; 437 438 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 439 fsl,pins = < 440 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 441 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 442 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 443 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 444 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 445 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 446 >; 447 }; 448 449 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 450 fsl,pins = < 451 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 452 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 453 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 454 >; 455 }; 456}; 457